LIBRARY OF THE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN bi.Q .^4 ttop. & 510. W ^j/C'^ Re P° rt No - ^ 6 3 COO-2118-OOlU CONTROL POINT DESIGN USING MODULAR LOGIC by Christian A. Rey June 1971 DEPARTMENT OF COMPUTER SCIENCE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN URBANA, ILLINOIS jQJ£ LIBRARY OF SEP 9 1971 .UNIVERSITY OF ffW-VA-CHAMPAIflN COO-2118-OOlU Report No. U63 CONTROL POINT DESIGN USING MODULAR LOGIC by Christian A. Rey June 1970 Department of Computer Science University of Illinois Urbana, Illinois 6l801 This work was supported by Contract AT(ll-l)-21l8 with the U. S. Atomic Energy Commission. Digitized by the Internet Archive in 2013 http://archive.org/details/controlpointdesi463reyc in Abstract The purpose of this note is to introduce h basic building blocks, or modules, with which one can very easily convert a flow-chart design into a logical network which accomplishes the same coordination of tasks. The implementation utilizes an asynchronous or pseudo-asynchronous "control point" strategy. [l] The conversion ( flow-chart — ^network) is systematic in that one "box" in the flow-chart corresponds to one module. The problem of minimizing the circuit realization of a given coordination is therefore reflected back into the related problem of "minimizing the flow-chart" representing this coordination. Preliminary remarks on this latter process are outlined at the end of the paper. IV TABLE OF CONTENTS Page 1. Conventions 1 2 . Flow-cnart conversion 6 3. Four basic modules 7 3 . 1 The DO-module 7 3 . 2 The Sequence-module 10 3.3 The Wait-module 10 3.3.1 The ¥2-module 10 3.3.2 The Wl-module 10 3.3.3 Properties and applications of the Wj (n) -module 12 k. Properties and applications of the four basic modules .... lk k. 1 Asynchronous mode lk k.2 Pseudo-asynchronous mode lk k.3 Control sequenced by external signal IT k.k Costs 19 k.5 Example 20 5. Simplification of logical network 25 5 . 1 Unconditional parallel chains 25 5.2 Cascaded Sequence modules 27 5.3 Cascaded Wait modules 29 5.^ Conditional Task 31 5 . 5 Example 31 6. Conclusion 3^ -1- 1. Conventions In our flow-charts, k different symbol boxes are used: i. - the task box: i - the decision box (the two directional branch): • • • - the circle: {~J V - the dotted circle: - the fan-out point: A The task box represents a task to be performed. We mean by "task" a set of "elementary micros-operations" to be done in parallel, (Figure l). For instance, "add register R2 to Rl" is a task; similarly, "call routine SUB and set flip-flop F" is considered as one task. It is important to note that we exclude the conditional micro operations from characterizing a task. For example, "reset Fl if a = or reset F2 if a = l" is not a task, although the individual operations "reset Fl" and "reset F2" are tasks. Exceptions to this rule are described in section 5.4. The decision box (the two-directional branch) has the following meaning: when the control flow reaches the decision -2- ADD R2 TO Rl (a) CALL ROUTINE SUB AND RESET F (b) RESET Fl IFa = RESET F2 IF a=l RESET Fl RESET F2 t (O (a), (b),(d),(e) ARE tasks (c) IS NOT A TASK (d) (e) Figure 1 Task Conventions -3- box, it is directed to the "l subbranch" if the condition within the box is satisfied and to the "0 subbranch" otherwise. An important assumption is that the condition within the search box must be expressed by one and only one variable. This is not a restrictive assumption since we can always preprocess the conditional variables within the branch box in order to obtain a final variable X which is "l" if the condition is satisfied and "0" otherwise. Some examples are given in Figure 2. The circle (Figure 3. a): if the control flow hits the circle from any one of the n incoming branches , then the control flow propagates through the outgoing branch. The dotted circle , (Figure 3.b): if the control flow reaches all of the n incoming branches of a dotted circle, then and only then the flow propagates through the outgoing branch. Typically, a dotted circle is used to wait for the accomplish- ment of two or more parallel tasks. Figure 3c shows a complex coordination where circles and dotted circles are combined. The fan- out point is a point in the flow-chart, where a signal splits into m signals. This point corresponds in the actual design to the output of a gate with a fan-out greater than one. Figure 3d shows some conventions and equivalences concerning fan-out points, circles and dotted circles. Several non-restrictive assumptions are made in what follows. For instance, we assume that the control signal is normally one and that it becomes a negative pulse (l-0-l) when it activates a device. (This assumption comes from the fact that only NAND gates are used in our design.) We also suppose that the flow-chart is "safe", i.e. it is free of any loops etc. which could cause actual design malfunction, -U- (a) (b) Figure 2 Sequence Conventions -5- (a) CIRCLE (b) DOTTED CIRCLE (d) Figure 3 Circle and Dotted Circle Conventions -6- 2. Flow chart conversion What can we consider to be the simplest way to convert a flow-chart into an actual logic design? The response to this question should take into account factors such as: - conversion duration - operator qualifications - ease of resulting logic drawing interpretation Further considerations concerning the design itself are: - speed of resulting logical network - degree of modularity - minimality (cost) The idea of converting a flow-chart into actual logic using a "box-to-box" conversion scheme has several of the advantages emphasized above. In particular, it shortens drastically the design duration by giving the logic the same overall topology as the flow- chart. Moreover, since the conversion is systematic, the designer no longer needs to be an "artist" as before. As far as the quality of the design itself is concerned, its modularity is unquestionable, due to the presence of a limited number of building blocks. We will see later that a factor such as speed may be improved in the final logic design if some preprocessing of the flow-chart is done first. It is now our purpose to introduce four basic logical hardware modules corresponding to the four basic flow-chart "boxes". -7- 3. Four "basic modules 3.1 The DO-module This module is the logical equivalent of a task box initiated from n places (Figure 1+) . There are two possible designs for the DO-modules, which correspond to two different modes: asynchronous and pseudo- asynchronous . In the first case the DO-module, called DOA(n) , does the following. When one of the advance-in lines Ail,...Ain drops to "0", the memory element is set and the DO-module is said to be primed . When Ail,. . . ,Ain return back to 1 , the task signal DO, becomes "0". This resets the whole system: DO goes back to "l". In this way a negative pulse appears at the DO and Ao lines. The length of this pulse depends primarily on the propagation delay through gate (3). In conclusion, the DOA(n) module sends a negative pulse on the DO and Ao lines when a negative pulse has been seen at one of the Ail,..., Ain lines. In the second case, the DO-module, called DO(n), not only does what the DOA(n) does but also "simulates" the task duration with a "timing stage", as shown. When DO goes to "0" , the upper input of gate (5) becomes "l" and C is charged. After a delay A depending on R and C, the second input of gate (5) becomes "l" thus making Ao = "0" which resets the whole system as seen previously. Again a negative pulse appears at the DO line and at the Ao line. The length of the DO pulse depends on A whereas that of the Ao pulse depends only on the propagation delay through the various gates. -8- (a) FLOWCHART (b) ASYNCHRONOUS MODE DO * CC (c)PSEUDO -ASYNCHRONOUS MODE ▲ DO >Ao ► Ao *CC Figure k DO-Modules -9- An interesting property of the DO-module is that the Ai's, DO and A Q signals are all of the same polarity (negative pulse), and thus can be used for the same purpose. For instance, the Ao line is normally used as the advance-in Ai of a next DO-module. This can also he done using the DO line. In this case, this signal acts as a calling signal and is, in general, used (as in software) by a main sequence (program) to initiate some other sequence (routine) which -will later "return" using a reply signal, (Figure 11 ). Another useful property is that A is selectable according to the choice of the capacitor C. It is shown [l] that A obeys the relation: A (in nanosecond) = 1.5 x C _ if R = 8.2k (IC 7^00 Series). A more powerful property of the DO-module is that it exhibits the same topology as the flow-chart box which represents it: both have the same number of control (flow) input /output lines (n input lines : Ail,...,Ain ; one output line : Ao). -10- 3.2 Sequence-module This module assumes the function of a two-directional branch. According to external condition(s) , it directs an input negative-going pulse towards one of two directions. The flow- chart and logical design of the Sequence-module, termed S(n), are shown in Figure 5. Again, input and output signals are all of the same nature. Thus, a S(n)-module is compatible with a D0(n)-module and with other S(n)-modules. Notice that the Sequence Condition , S, controlling the action of the module must be reached before any signal Si hits gate (l). Also, there is the same number of control input /output lines in the flow-chart box as in the module (input S is an input condition). 3.3 Wait -module 3.3.1 W2-module The third module to be introduced here is called the W2(n) module. The flow-chart of this module together with its design is shown in Figure 6. When a negative pulse has appeared at all the lines Wl,...,Wn all the flip-flops are set and the output gate (3) is sensitized to the Wait Condition W. When W = "l" , the W2(n)-module resumes its cycle by resetting all the flip-flops, thus producing a negative pulse at line Wd". 3.3.2 Wl-module Another module, called Wl ( n ) -module , is introduced here. It may appear to be redundant with one of those already defined, since it can be realized using a S(n+l) -module. However, since the flow-chart configuration it implements is ■11- (a) FLOWCHART Sl«- Sn»- S(n) IS (b) LOGIC DESIGN Figure 5 Sequence Module >SO, -► SO L (a) FLOWCHART ,,CC iw (b) LOGIC DESIGN ► WO Figure 6 W2-Module -12- quite frequent, a cheaper design is proposed (Figure 7 )• When any of Wl,...,Wn goes to "0" the flip-flop is set. If W = "1", Wo drops to "0" thus resetting the flip-flop which in turn causes Wo itself to go back to "l". Let us notice that if n = 1, a Wl(l)-module is equivalent to a W2(l)-module. Since this case often occurs, we give the name W-module to this kind of module. 3.3.3 Properties and applications of the Wj (n)-module The Wl and W2 modules have a very similar structure and therefore exhibit very similar properties. First of all, inputs and outputs are negative pulses which give these modules a full compatibility with the modules previously defined, However, special attention must be given to studying the speed of such units as well as the output pulse length they produce. Assuming W = "l", the propagation delay through a Wj(n) unit is only a function of gates (l) and (3) whereas the pulse length is related to the delay in gates (l), (2) and (3). Hence it is advisable to use fast gates (l) and (3) and a slow gate (2) which will alone give the output pulse its required length. Typically if gates (l) and (3) are taken from the IC series 7^00 and gate (2) is a 7^L00, a propagation delay through the Wj(n) unit of 20ns may be expected together with a pulse length of 50 ns at the output. Also, modules Wl and W2 have the same topology as the flow-chart they implement: same number of inputs (Wl,...,Wn) and outputs (Wo)(W is a conditional input and CC is the "common clear" line used to reset the system at the very beginning). -13- (a) FLOWCHART SI Sn«- S(n + 1) §0\ lw (b) S(n+1) REALIZATION >S0 1 Wl. Wn« — - *CC AW (c) WL(n) - MODULE -► wo Figure 7 Wl-Module -lU- k. Properties and applications of the four basic modules It is shown in what follows that these blocks may be used to implement control logic using any of the three basic modes: asynchronous, pseudo-asynchronous or clocKed. The main difference between these 3 modes is the way in which task boxes are implemented. k.l Asynchronous mode In asynchronous logic, a task is activated when some reply from the previous task is received. Two cases are possible: this reply is a level (produced by a reply flip-flop) or it is a pulse (produced by the last DO-module in the routine. In the first case, the configuration of Figure 8b may be used efficiently if A is such that flip-flop Fl is reset by CALL SUB before F2 is set. It is important to notice that the same configuration may be used to call an entire routine or to do a simple micro operation. When the reply signal is a pulse, the configuration of Figure 8d may be used. Note that in this case a DOA module is needed instead of a DO-module. A more complicated situation is illustrated in Figure 9. Note that in this case, two replies are pulses (l-0-l), and one is a level. As said before, some preprocessing on these replies is necessary to obtain a single composite variable X which is "l" when all replies have been received and "0" otherwise. A W2 -module may be used, as shown, to obtain this variable X. 4.2 Pseudo-asynchronous mode In this mode, the DO-module (with timing stage) is used. As indicated by the mode name, a pseudo-reply is produced by this -15- CALL ROUTINE SUB Ail DO CC ROUTINE SUB TASK 2 (a) FLOWCHART Ail DO CALL SUB DO A tO CC Ao Wl W SUB REPLY ( _T ) w F2 wo TO TASK 2 Tr- ee (b) DESIGN ( REPLY = LEVEL) CALL ROUTINE SUB Ail DO CC ROUTINE SUB Ail DOA CALL SUB DO DO DO CC Ao Wl W V SUB REPLY ( _Jl_ ) w wo -► TO TASK 2 (c) FLOWCHART CC Ice (d) DESIGN (REPLY = PULSE) Figure 8 Calling Program Implementations -16- CALL SUB1, SUB2 , SUB3 (TASK 1 ) TASK 2 (a) FLOWCHART r DO DO DO _ROUTI N E _S_UB1 _ J r R2 DO • • • 00 DO L J*J?v TJhe _ s i|B2_ r "1 DO DO DO R3 _ ROUJI NE _SUB 3 w Wl w~2 CALL SUB1, SUB2, SUB3 W2 All DO DO A £0 Ao WO -H cc Wl CALLING SEQUENCE w w wo TO TASK 2 CC cc ( b) DESIGN Figure 9 Parallel Execution of Subroutines. -17- timing stage after a certain delay A which merely simulates duration of the task performed. If this task is a micro operation, A can be easily computed and using a DO-module to perform the task is straight forward. If the task is an entire routine, its duration may be variable and hence it may be difficult to assign a specific duration A to this routine. In this case, the pseudo-asynchronous mode cannot be used and the problem is solved in an asynchronous manner, as shown in Figures 8 and 9. k.3 Control sequenced by external signal A slight variation of the previous mode can be devised with the task duration simulated by a clock instead of a timing stage. In this case, the system becomes synchronous and may be implemented as in Figure 10. -18- TASK A TASK B TASK A WO Ail DOA TASK B Ao Wi W cc cc CLOCK WO Ail DOA Ao Wl w cc W CC wo w Figure 10 Operations Sequenced by External Signal -19- k.k Costs In Table 1, modules are listed together with the NAND gates and cost required to implement them. A cost is also computed based on the following costs: Inverter: 5 units; 2 input NAND: 6 units; 3 input WAND: 8 units; k input NAM): 13 units, (l unit - 5<£). module inverter 2-NAND 3-NAND 4-NAND Cost /module D0(1) 1 3 1 31 D0(2) 1 1 3 35 D0(3) 2 3 2 kk DO(lt) 2 3 1 1 ^9 DOA(l) 2 1 20 . D0A(2) 3 2U DOA-3) 1 2. 2 33 DOA(U) 1 2 1 1 38 S(l) 2 2 22 8(2) 1 3 23 S(3) 1 2 1 25 s(iO 1 2 1 30 W=W1(1) 2 1 20 Wl(2) 1 2 22 Wl(3) 1 1 1 27 W2(2) 2 3 36 W2(3) 3 3 1 55 Table 1: Module List -20- For each of the modules in this table, the cost is computed for the cheapest design shown in Figure 11. We are now able to compare the efficiency of this new method with the efficiency of any other method. k, 5 Example To make this comparison meaningful, we have chosen to implement a routine which was already designed and implemented using the "artist" approach instead of the systematic approach presented here. The routine 'SAMPLE' occurs in the Beam Motion Control of ILLIAC III SMV Scan-Display Controller. The flow- chart is shown in Figure 12. Use of the four basic modules described earlier to convert the flow-chart is quite straight forward. What one needs to do is just to try to match the flow-chart of each of the four basic modules with the segments of the flow-chart of the system to be realized. This is done in Figure 12. Costs are computed in Table 2 for the new and old designs of SAMPLE routine (Figure 13). Cost (Modular design): Cost (Old design) lxD0(2) = 35 8xD0(l) = 2U8 8xinverters = ^0 10x2-NAND = 60 2x3-NAND = _l6 Total = 399 2xD0A(l) = ko lxD0A(2) = 2k lxDO(l) = 31 lxDO ( 2 ) = 35 3xW = 60 lxWl(2) = 22 3xS(l) = 66 Total = 278 Table 2: Comparison of Old Design and New Design n = 2 n = 3 (a) DO OR DOA MODULES Sl- S2- Sl- S2 S3" n = 2 (b) SEQUENCE MODULES S2- _/— 53 S4 n = 3 >- n = 4 WO Wl Wl- W2" Wl(l) n = 1 WL(2) Wl - W2- W3" (c) Wl-MODULES wi Wl W2 W3 (d) W2- MODULES Figure 11 Lowest Cost Designs for Modules -22- D0A(2) CALL E-ROUTINE CI = VBOL + VEFD-LINC C2= VEFD C3 = (R = X] C4= EFD CALL B- ROUTINE DO(2) o TASK B (SAMPLE REPLY) Figure 12 Flow chart of SAMPLE and. its Modular Logic Segmentation -23- B REPLY C3 C2 CALL SAMPLE CI E REPLY C4 FLY REPLY CC ■v TO DO(2) -t»l ^Z> V > A t DO(l) fc DO(l) TO DO(l) CALL B TASK A W>rl OO(l) D0(2) M TO 00(2) uo> •-«3- :^> HdO(2) ■fco- -Ch 3>— i "TO 0(1) -t» L> CALL E SAMPLE REPLY CALL FLY Figure 13 Old Design of SAMPLE .2k- Table 2 shows that a substantial savings is realized as veil in time as in money when the systematic method pro- posed in this paper is applied. Even greater savings can he made if the logic drawing resulting from the use of the modules is closely inspected for the presence of obvious redundant logic. Although the modules are individually optimal, a set of converted modules may not represent an optimal implementation. For this reason some of the most frequent flow- chart configurations are considered next with suggestions to optimize their realization. •25- 5. Simplification of logical net -works Although the last example has shown that a considerable savings in time and money can "be realized by applying the above systematic procedure, the design itself is not claimed to be "minimal" since it is only composed of locally minimal subnetworks. For example, another flow-chart representing the same routine might lead to a cheaper realization. It is , therefore, believed that some preprocessing must be done on the flow-chart in order for this one to lead to a "near minimal" realization. Since a "box" in a flow-chart corresponds to a,. module in the design, it is reasonable to try first to minimize the number of such boxes. The essential rules for doing this are stated next. 5.1 Unconditional parallel chains Unconditional parallel chains of tasks are sequences of task which are performed at the same time (in parallel), /vi example is shown in Figure lU where three chains are entered at the same time. In order to reduce the amount of logic needed for such a coordination, it may be advisable to follow the next rule (the operator is supposed to have some information about the relative duration of each of the tasks mentioned in this figure before applying this rule: the number in parenthesis represents these durations). Rule 1 : If boxes located at the top or at the bottom of n parallel branches represent tasks which have approximately the same duration, these tasks can be merged into one box (and there- fore be performed by only one DO, or DOA module). In our case, -26- TASK A (10) ] ' TAS < D (40) 3 ' TASL < G (30) TASK B (ID TASK E TASKS A,B,C (II) (50) TASK C (ID TASK F (30) (a) DESIGN @ THE NUMBER IN PARENTHESES REPRESENTS ESTIMATED DURATION OF TASK TASK D (40) TASKS G,F (30) TASK E (50) (b) DESIGN -27- tasks A, B and C have approximately the same duration, and so are merged into one box (duration = ll). Let us notice that if we had "duration of A" = "duration of B" = 10 and "duration of C" = 30, then we could have merged only A and B. This, is done for tasks G,F and E. 5.2 Cascaded sequence modules In the definition of a two-directional branch, we have said that conditions within branches-boxes were expressed with only one variable (Ci). This corresponds as it is shown next to a cheaper design. Figure 15 represents two designs implementing the same sequence. In design A, the condition Ci = A + BC is, in fact, realized with a set of cascaded sequence modules, whereas in design B, variables A, B and C are preprocessed and the resulting variable X is the variable used in the sequence module. Design B is obviously cheaper than design A. This can be generalized in the following way. Let f = f ( Al,A2,. . . ,An) be the boolean function characterizing the sequence condition. Let n be the number of variables in f and p the number of minterm in the expression of f . It can be shown that 1 _< p _< 2 . In Table 3, we evaluate designs A and B in terms of their cost as functions of n and p. -28- r (a) DESIGN (A): THREE S(l)- MODULES NEEDED COST= 66 -| B C "I so so, (b) DESIGN ® ! ONE S(l)-MODULE PLUS ADDITIONAL LOGIC COST= 39 Figure 15 Rule 2: Cascaded Sequence Modules -29- 2 1 2xS(l) 2 P 3xS(l) 3 1 3xS(l) 3 2 UxS(l) 3 3 6xS(l) 3 k TxS(l) 4U 33 66 Uo 66 35 88 UU 132 U6 15^ 67 n p Design A Design B Cost of A Cost of B S(l)+lx2inpN+lxinv S(l)+3x2 " S(l)+lx3 " +lxinv S(l)+2x3 " +lx2inpN S(l)+Ux3 " + " S(l)+Ux3 " +lxi+inpN Table 3: Evaluation of Designs A and B From this table we deduce: Rule 2: When a set of sequence modules exists such that there exists one input line to this set and no more than two out- put lines, such a set may be replaced by only one sequence module. This property can be generalized: Number of output lines in the set Sufficient number of Sequence module 2 1 3 -2 n n-1 5.3 Cascaded Wait -modules A similar rule may be applied to cascaded Wait-modules. Rule 3: In any case, cascaded Wait-modules may be replaced by only one fed by a preprocessed variable X. Figure l6 shows an example of application of this rule. It is interesting to notice that Rules 2 and 3 not only decrease the cost, but also increase the speed of the control. -30- Wl Wl W2 W3 w w w w w w (a) DESIGN <§) : THREE W- MODULES COST= 60 WO Wl W2 W3 Wl "I W W wo (b) DESIGN (D ! ONE W-MODULE PLUS ADDITIONAL LOGIC COST= 33 Figure l6 Rule 3: Cascaded Wait Modules -31- 5.1+ Conditional Task In the definition of a task (paragraph l) we have excluded a case such as "reset Fl if a = or F2 if a= l" because this task can be expanded using a t"wo-directional branch and two task boxes (Figure 17), However, if the two tasks "reset Fl" "reset F2" have approximately the same duration, such an expansion technique might not be advisable from an economy standpoint since it would result in the use of one S(l) -module two DO-modules whereas one DO-module (plus additional "task logic") is sufficient as shown in Figure 17. Hence the following rule: Rule k: If boxes located at the output of a multi-directional branch correspond to tasks having approximately the same duration, these boxes and this branch may be merged into one single box representing a "conditional task". 5.5 Example An example which shows how efficiently these rules may be applied is represented in Figure 18. The original flow-chart represents a cost of U07, whereas the final one has a cost of around 180 (part of the reduced logic is "transformed" into task logic). -32- 1 s n >►. . \ Lt >^ F 2 = i A Fi=l A (a) FLOW CHART Ail ENTRY a SI so< DO DO Ao cc SOi Ai (b) EXPANDED LOGIC TASK LOGIC DO DO A Ao CC ENTRY A (c) REDUCED LOGIC CC ; .- n [ Rul»» k: Using ';.oK ] ■ '«?i ■• -33- THE NUMBER IN PARENTHESES REPRESENTS ESTIMATED DURATION OF TASK C if a =i Difq= i(20) F if (Py +/3S) = 1 G if £8 = i E if Py = 1 (10) C if a =i D if a = 1(20] H (40) E F if (Py + /3S): = i G if /3S = i E if py -- = i I IN ANY CASE (10) (b) RULE 1,2,3,4 APPLIED (C) FINAL (RULE i) Figure 18 Flow chart condensation using rules 1-1* : An Example -3U- 6. Conclusi on We have presented a modular approach to the problem of designing control logic using the so-called " Control Point Technique." Compared to the "old" heuristic method, this approach has the advantage of being systematic and of leading to an economical realization. For the last point to be achieved, some "preprocessing" of the initial flow-chart is sometimes necessary. A set of heuristics can be formulated to do that. Although these heuristics can be applied systematically, in certain cases it might not be advisable to apply them. For instance, applying Rule 1 can destroy a certain mod- ularity in the design because of the merging of two parallel chains. Therefore, at this stage of the design, the skill and experience of the designer are still needed. ■35- REFERENCE [l] Rey, Christian A. , "Control Point Strategy and Its Automated Diagnosis", Department of Computer Science Report No. U50, June 1971. FormAEC-427 U.S. ATOMIC ENERGY COMMISSION .,SJ 01 UNIVERSITY-TYPE CONTRACTOR'S RECOMMENDATION FOR DISPOSITION OF SCIENTiFiC AND TECHNICAL DOCUMENT ( See Instructions on Reverse Side ) 1. AEC REPORT NO. Report No. k63 COO-2118-OOlU 2. TITLE CONTROL POINT DESIGN USING MODULAR LOGIC 3. TYPE OF DOCUMENT (Check one): Pra, Scientific and technical report I - ! b. Conference paper not to be published in a journal: Title of conference Date of conference Exact location of conference. Sponsoring organization □ c. Other (Specify) 4. RECOMMENDED ANNOUNCEMENT AND DISTRIBUTION (Check one): 14- a. AEC's normal announcement and distribution procedures may be followed. I~l b. Make available only within AEC and to AEC contractors and other U.S. Government agencies and their contractors. I~l c. Make no announcement or distrubution. 5. REASON FOR RECOMMENDED RESTRICTIONS: 6. SUBMITTED BY: NAME AND POSITION (Please print or type) Christian A. Rey Research Assistant Organization University of Illinois Department of Computer Science Urbana, Illinois Date June U. 1971 IR AEC USE ONLY 7. AEC CONTRACT ADMINISTRATOR'S COMMENTS, IF ANY, ON ABOVE ANNOUNCEMENT AND DISTRIBUTION RECOMMENDATION: PATENT CLEARANCE: □ a. AEC patent clearance has been granted by responsible AEC patent group. □ b. Report has been sent to responsible AEC patent group for clearance. LJ c. Patent clearance not required.