510.84- Iflfer no. 32.3 cop. 2- LIBRARY OF THE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN 510.84 Ij6r no. 523 cop. 2 the person charging this material is re- sponsible for its return to the library from which it was withdrawn on or before the Latest Date stamped below. Theft, mutilation, and underlining of books are reasons for disciplinary action and may result in dismissal from the University. UNIVERSITY OF ILLINOIS LIBRARY AT URBANA-CHAMPAIGN r\U6 23 L161 — O-1096 Report No. 323 DEC PDP-7 Interface to IBM 2701-PDA COO-1469-0116 by C. E. Carter H . E . Lopeman R. L. Miller A. D. Whaley E NOV 9, 972 DEPARTMENT OF COMPI UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN URBANA, ILLINOIS COO-1U69-0116 Report No. 323 DEC PDP-T Interface to IBM 2701-PDA by C. E. Carter H . E . Lopeman R. L. Miller A. D. Whaley Digitized by the Internet Archive in 2013 http://archive.org/details/decpdp7interface323cart 5/0.84- TJlCcr CONTENTS 0. Introduction 1 . Hardware 2. PDP-7 Programming of Channel lU 3. 360 Programming of Channel 23 Appendix A (PDP-7 Computer) 27 Appendix B (2701 PDA) Ul Appendix C (cost) 52 Introduction The history leading up to this described equipment "began in May of 1965 when we were interested in attaching a communications satellite computer to our own computer "Illiac II." At that time we had a small time sharing teletype project operating on the special registers of Illiac II. Because each character from each teletype interrupted the central processor, it was decided that some controlled buffering would be very useful. The P. D. P. 7-630 configuration was acquired from Digital Equip- ment Corporation to serve the purposes of telephone line scanning and teletype line buffering. This system was attached to an 1/0 channel of Illiac II through the data break hardware of the P.D.P.7- An experimental time sharing system was developed using this hardware. When it was learned that such a service would be generally useful some work began on the connection of the same P. D. P. 7-630 to a 360/50 in our computer service organization. Since there was a need to continue the Illiac II time sharing while the IBM time sharing was being developed a four-port multiplexor was added to the data break feature of the P.D.P.7- With the multiplexor more than one device could make use of the data break feature to and from the core memory of the P.D.P.7. At one time it was thought that tying the P.D.P.7 directly to one of the channels of the 360 mod. 50 was the best hardware approach. After looking at the interface requirements of a 360 channel it was decided that there were easier ways. The particular interface that seemed easiest to do was to the 2701 Parallel Data Adapter. This was chosen and cards were purchased from Digital Equipment Corpor- -1- ation to build the interface and multiplexor. Only at the direct points of interchange with IBM were any special circuits needed. These were built on D.E.C. cards and all of the hardware was mounted in one of the P.D.P.7 cabinets. This report is meant to be used as a maintenance manual for those who maintain the hardware and as a source of information for anyone wanting to make a similar connection in hardware of their own. For this latter reason appendix A, B, C have been attached so as to give some information about the P.D.P.7, the 2701, and the cards and cost of the interface hardware. 1. Hardware 1.1 Logical Interface, General Discussion of Connecting Lines The P. D. P. 7/2701 interface logic was designed to handle transfers to and from both devices on a demand-response basis. This aspect is particularly important from the P.D.P.7 point of view, since the P.D.P.7 must be capable of handling transmissions to and from many remote consoles as swiftly as possible. The P.D.P.7 may be programmed to accept single word transfers on an interrupt basis and service consoles when not thus employed. It may also be dedicated to handling burst mode messages from the interface up to a maximum of 77g words. The interface entry to the P.D.P.7 is through a D.E.C. 173 data multiplexor which utilizes the P.D.P.7 data break facility. The demand-response feature of the interface makes multiplexing with other devices feasible assuming timeout conditions of the 2701 are met. The 2701 transmission rate may be controlled by the P.D.P.7 and the interface. (Subject to maximum transfer rate limitations of the 2701.) -2- TTT TT m n T t t J 00 i a < l> r SSr KQOV »« • a ^s 7V.H JMM 35 TT O 9 * r * * 3 TTTTTTT * s 3 TT J_L 1 £ TTT 5 o. -3- The P.D.P.7 device selector system is used to generate the various instructions needed. (iOT's) In order to cut system cost, a second level IOT instruction decoder was designed for the interface. In this way only two special purpose device selector hoards were re- quired to generate 18 control pulses and levels. The device selector hoards generate (l) and (3) pulses each. Nand/nor logic and two unused IOT instruction hits, hits 12 and 13, generate the additional pulses and levels. The P.D.P.T's attention is gained hy the interface by use of the interrupt bus. The interface designates its intention hy raising a skip flag. The P.D.P.7 will respond to the interrupt bus at the end of the current instruction. The P.D.P.7 then breaks to location (0) and executes a subroutine at location (l). Important registers and information are stored at this point. Location (l) is normally a jump to the flag handling subroutine in which the P.D.P.7 executes a series of IOT instructions, dealing with 10 devices. These IOT pulses go to nand gates of the various 10 devices. The gate outputs are tied to the skip bus and when a gate is "made" the processor "skips" the next instruction in the list and normally lands on a jump instruction to the particular 10 device handling subroutine. This method enables the processor to do other things when not handling 10. Input /output priority can be established in the skip list. Once the initial interrupt has been made and the necessary information has been transferred to the interface from the P.D.P.7, the interface communicates via the high speed data break. The interface will generate a break request to the P.D.P.7 which will be answered at the end of the current instruction. When the P.D.P.7 breaks, it uses only the memory address register and the memory buffer. -k- None of the other registers are disturbed. The interface memory address is incremented by (l) and the P.D.P.7 resumes processing, pending another break request. In the 2701 interface an interrupt is generated on a write select or a read select signal from the 2701. Interrupt is also generated when the interface address counter overflows indicating an end condition. Break request is generated by write ready or read ready from the 2701. The address counter overflowing in the interface also generates end of record (EOR) to the 2701 to terminate the transfer, If a parity error is detected on a transfer from the 2701, a flag is set and the check is made after the transfer is completed. The flag is checked by using the skip bus and an IOT instruction. -5- 2701 Parallel Data i Adapter (PDA) Output Data Lines (l6) Input Data Lines (l6) Write Select (l) Read Select (l) Write Ready (l) Read Ready (l) Demand End of Record (EOR) (l) Redundancy Error (l) Interrupt (l) Parity (l) Parity (l) P.D.P.T Interface OUTPUT DATA LINES INPUT DATA LINES. WRITE SELECT. READ SELECT. WRITE READY. READ READY. From the PDA to the interface buffer register. While the word is held in the buffer register, parity is generated in the interface and compared with PDA parity. From the interface buffer register to the PDA. Parity is generated in the interface and sent to the PDA. From the PDA to the interface to signal a write operation from the 2701. This line also generates an interrupt to the P.D.P.7 if the write enable flop is set. From the PDA to the interface to signal a read operation from the 2701. This line also generates an interrupt to the P.D.P.7 if the read enable flop is set. From the PDA to the interface. This line notifies the interface of a data word on the bus. The data is valid and settled before the line is raised. From the PDA to the interface. This line notifies the interface it is available and ready to accept a word from the bus. -6- WRITE COMMAND. READ COMMAND. REDUNDANCY ERROR. END OF RECORD (EOR). DEMAND . To the PDA from interface. Signifies the interface has accepted the word on the bus Signifies the data on the bus is valid. Read data must be valid for the duration of the demand signal. (interface Parity Error). Interface to PDA. Indicates the interface has detected a parity error on a write operation. Interface to PDA. This line signifies the interface has completed the operation and will not generate or accept any more data. This line also causes the PDA to present device end and channel end status to the 360 channel. INTERRUPT . Interface to PDA. Signals the PDA to interrupt the CPU through the channel. PARITY . PDA to interface. Parity is sent simultaneously with the data bus. The interface gates the data bus into the buffer register, and calculates parity to be compared with the PDA parity. PARITY- INTERFACE TO PDA . The interface buffer register is loaded from the P.D.P.7 and parity is calculated from the register contents. The data and parity is sent simultan- eously to the PDA. 1.2 Block Diagram General Information REF: Block Diagram P. D. P. T/2T01 Interface D-7-I+O-78 The blocks making up block diagram D-7-^0-78 contain the name and drawing number of each logical section. All signals used or generated by each logical section have been drawn in to facilitate discussion of the interface logic. A general discussion of the various blocks and their functions will be given for orientation purposes followed by a detailed discussion of the input and output lines and their relation to the interface. All material will be referenced to block diagram D-7-U0-78. For reference to actual logical assemblies the drawing number contained -7- in the block may be used. In the logical drawings, DEC (Digital Equipment Corporation) standard symbols are used. A discussion of DEC symbols and the circuit logic elements may be found in the DEC Logic Handbook. Each DEC card used in the logic has a dotted line drawn around that card's circuits. Inside the dotted line will be a letter, followed by three numbers to indicate the card type. The only nonstandard circuits used are the X006 and X007 boards built here for cable transmitters and receivers. A logic element and circuit drawing for these boards is contained in the interface drawings . 1. 3 Block Diagram Detailed Description 1.31 Instruction Decoder D-7-I1O-76 The instruction decoder logic is used to split the device selector signals from the P.D.P.7 into several more signals for control and gating of the interface. Two basic IOT commands from the device selector, IOT 50 and IOT 51, and their associated IOT pulses form one set of entries. The IOP pulses 1, 2, k from the P.D.P.7 input/out- put control logic and MBB12, 13 (memory buffer bits) are the other entries. The IOT pulses and levels are combined in nand gates with combinations of MBB12 , 13 to produce particular pulses and levels for interface control. MBB12 , 13 are actually two unused bits in the IOT instruction which are used in this case for sub device selection. The outputs of the instruction decoder respond to the IOT instruction bit configuration as follows : -8- READ IOT's 7050^7 - ICR (initiate channel read) micro instruction to generate ICR1, ICR2 in same instruction. 70501+1 - ICR1 70501+2 - ICR2 705021 - SRD1 (skip on read done) 705002 - ERI (enable read interrupt) 705001 - SRR (skip on read ready) 705001+ - DRI (disable read interrupt) 705021+ - CRD (clear read done) WRITE IOT's 7051^7 - ICW (initiate channel write) micro instruction to generate ICW1, ICW2 in same instruction. 7051U1 - ICW1 7051^2 - ICW2 705121 - SWD (skip on write done) 705101 - SWR (skip on write ready) 705102 - EW1 (enable write interrupt) 70510U - DW1 (disable write interrupt) 70512U - CWD (clear write done) 705l6l - SPE (skip on parity error) 70516H - CPE (clear parity error) The use of the various signals generated in the instruction decoder will be discussed further in conjunction with the logical areas in which they are used. 1.32 Multiplexor D-173-0-2, D-173-0-3 The data multiplexor, type 173, was devised primarily to extend the data break device handling capabilities of the PDP-7 from one channel to four channels. It is a convenient means also of designating priorities of high speed channels. The multiplexor essentially looks at the channel data request lines in order of descending priority. As a data request is set into the multiplexor priority flops , it clears the MPX flops of all lower priority channels. Only one MPX flop is allowed on at any one time. The PDP-7 timing pulse T5 is used to clear all MPX flops and pulse T6 sets the MPX flops according to channel -9- data request inputs. When the channel MPX flop is set, it conditions the channel address and data word gates to place channel information on the data and address "buses to the PDP-T. The channel MPX flop also conditions gates to allow address accepted, data accepted, and data ready to be gated to the specific channel. Transfer direction is also conditioned by the channel MPX flop to be sent to the PDP-7. At the same time the multiplexor gating setup and priority is being established, data request is sent to the PDP-7. This is done by an OR function on all channels. The purpose is to guarantee an answer to the break request at the end of the current cycle without waiting for the multiplexor setup. Waiting on the multiplexor could cause a one-cycle delay in transmission. 1.33 Data Address Register D-7-U0-71 This logic is used to furnish a current address to the PDP-7 on a break cycle. The content of the PDP-7 accumulator (bits 5 through 17) is transferred to the address flops before a break cycle is initiated. If a write sequence is to be performed, the accumulator bits are gated into the address register by the signal ICW from the instruction decoder. The signal ICR gates the bits for a read sequence. The data address register is cleared to "0" by a signal DA which originates in the data buffer logic. Address incrementing is accomplished only on bits 12 through 17 of the address register. The address is incremented by the signal, address accepted, from the multiplexor logic. The address is incremented to a maximum of 77o addresses. Address bits 12 through 17 are sent to the block end logic for overflow detection, and all bits, 5 through 17, are sent to the multiplexor for distribution to the PDP-7 -10- 1.3 1 * Block End Logic D 7-^0-71 The block end logic consists of a large nand gate with inputs made up of address bits 12 through 17 from the data address register. When all inputs are true (representing address overflow) a signal called 77 OCCURRED is generated which causes an end of record (EOR) to be sent to the 2701 PDA. This terminates the transfer. 1.35 Data Buffer D-7-^0-72 The data buffer is a double gated 16 bit register to buffer the data from the 2701-PDA and the PDP-7. Bits 2 through 17 from the PDP-7 memory buffer are gated into the register by CH"0" data ready from the multiplexor. The output of the register is driven to the 2701-PDA by X007 transmitter boards. The data from the 2701-PDA (DI bits) is received by the X006 receiver boards. The data is gated into the register by the signal, write gate. The output of the buffer register flops is tied into the multiplexor for entry to the PDP-7. The buffer is cleared by an ICW or an ICR which also generates the signal, CLR DA TO "0" (clear data address register). The buffer is also cleared by address accepted and read run (l), for the read case; and CH"0" DATA ACCEPTED, for the write case. 1.36 Parity D-7-^0-73 The parity logic is used to calculate parity to send with the data word to the 2701-PDA. It is also used to calculate parity to compare with the parity sent by the 2701-PDA. The parity circuits are exclusive OR's and the inputs are directly from the buffer register. -11- A parity error is looked- at by the PDP-7 only during the write in from the 2701-PDA. The signal, write demand, is used as a gate. If the parity sent by the 2701 PDA and the calculated parity disagree, the PE (parity error) flop, is set and the signal, redundancy error, is sent to the 2701-PDA. The parity error flop output is tied to the skip logic (D-7-^0-7^) and parity error check is normally made at the end of the transfer. The signal, CPE (clear parity error), is self- explanatory. 1.37 Skip & Interrupt Logic D-7-U0-.7U The skip and interrupt logic is the area of the interface which utilizes most of the instruction decoder outputs. The logic primarily consists of several flip-flops and gates which are set or conditioned by instructions from the instruction decoder and levels from the 2701-PDA. These flops and gates in turn condition gates on the skip and interrupt busses so conditions may be checked by instructions from the PDP-7. The interrupt to the 2701-PDA is generated in this logic to inform the 2701 that the PDP-7 requires attention. Likewise, the PDP-7 interrupt is generated to notify the PDP-7 that the 2701 requires attention. The skip bus to the PDP-7 is activated when one of several conditions prevails and the PDP-7 does the proper instruction to check the condition. The inputs from the instruction decoder are self-explanatcry from their names. EWI (enable write interrupt) does just that, and ETC. Read and write EOR (end of record) come from the read control logic and write control logic, respectively. Their function is to set the read done and write done flops so the transfer end can be detected by the P.D.P.7. This is accomplished via the skip bus. -12- The read run (0) and wr:" te run (0) are conditioning levels to determine a read or write interrupt to the PDP-?. Read select and write select from the 2701-PDA are used to generate an interrupt to the PDP-7 with proper conditions. These signals are also used to generate the transfer direction level to the multiplexor. 1.38 Write Control Logic D-T-^O-T^ The write control logic is used to control the data into the PDP-7 core memory, from the 2701-PDA. This logic contains the necessary- control elements to utilize the PDP-7 data break mode, and control the transfer timing. The write select signal from the 2701 PDA is used as a conditioning level. Absence of the write select signal terminates the transfer and clears the EOR (end of record) flop. The write ready line from the 2701 is used as a word transfer command, going on and off for each word transferred. Write ready coming on generates the write gate signal to gate the word from the 2701-PDA into the interface buffer. The write gate sets the DATA REQ flop to generate a DATA REQ to the multiplexor at write ready turn on time. All data requests in the write case are a result of write ready. ICW (initiate channel write) is used only to set the write run flop to allow transfers to begin. The signal 770C from the block end logic generates EOR (end of record) to the 2701-PDA. The signal, demand, to the 2701-PDA is generated, after a delay, by the write gate signal. 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I » 4 t I t * *r Y h hllliil jf-O ■80 K? r" III S-18 B f ii i u CO g-O 5 i j tl 1 c:j (D7-4o-7fc) n u z UJ u e I— , I H 2 -o u -E3 — ' -Qr~~~ -w*—\\> i > s » -VW-||| ©r 5? HO- 1 -W-«— W — r 1.39 Read Control Logic D-7-4Q-75 The read control logic is used to control the data from the PDP-7 core memory to the 2701-PDA. This logic contains the necessary control elements to utilize the PDP-7 data break mode, and control the transfer timing. The read select signal from the 2701-PDA is used in this logic as a conditioning level. Absence of the level causes transfers to stop and EOR (end of record) to be cleared. Read ready is used as a word transfer command, going on and off for each word transferred. Read ready causes DATA REQ to the multi- plexor to be set for all but the initial PDP-7 transfer to the inter- face buffer. The initial DATA REQ and buffer transfer is accomplished by the signal ICR (initiate channel read). The signal, demand, to the 2701-PDA is also set by read ready. CH"0" data ready from the multiplexor logic resets the DATA REQ and demand flops . The address accepted pulse from the multiplexor is used in conjunction with 7T0C from the block end logic to generate EOR to the 2701-PDA. 2. PDP-7 Programming of Channel 2.1 Channel Description from a Programming Viewpoint 2.11 General Description The PDP-7 is equipped with a communications channel to the 360. Since it is essentially half-duplex, data may be carried on this channel -Hi- in only one direction at a time. To assist in the programming of this channel, it has "been constructed to appear at the PDP-7 end as a full duplex channel when all instructions are used as recommended. From the 360 end, the channel appears as half-duplex. For this reason the 360 must be careful not to attempt to perform more than one input/ output operation at a time to the channel. 2.12 Data Transfer When the transfer is initiated by the PDP-7 ( as it must be) the starting address for the transfer is taken from the bottom 13 bits of the accumulator. The number of PDP-7 words to be transferred is determined solely by the starting address , and may vary from one work to sixty-four words. If YYYXX represents an octal thirteen bit address, a transfer started at this location will involve all words from this address to YYY77, inclusive. Thus if a transfer is started at 12037 octal, words 12037 to 12077 will be transferred (kl octal or 33 decimal words). All transfers involve the bottom 16 bits of the PDP-7 word. When sending to the 360 , the top 2 bits of the 18 bit PDP-7 word are ignored. In the opposite direction from the 360 , the top 2 bits are set to zero as data is entered into the PDP-7 memory. The sixteen bits that are transferred represent two 360 bytes of eight bits each. The bytes are transferred to and from the 360 serially, and a transfer need not involve an even number of bytes of information. Clearly, however, the number of 360 bytes sent to or received from PDP-7 memory must be even. This will be discussed more fully later. During a transfer, the first byte of information always comes from the top half of the 16 bit word segment. The next byte involved then -15- comes from the remaining eight -bits. 2.13 Attention The 360 is capable of informing the PDP-7 of its intention to perform a transfer in either direction. The PDP-7, however, has the ability to inform the 360 only about its intention to transmit a message. Each time the PDP-7 executes the ERI instruction, ATTENTION is set in the 2701. If the 360 enters the state where it may be in- terrupted, by its input/output channels, it will interrupt on this attention signal. As soon as the 360 interrupts on the attention condition or a TIO or SIO instruction is issued to the 2701, the attention cond- ition is cleared. More will be mentioned about ATTENTION in a later section. From the PDP-7 standpoint the use of the ERI instruction in this manner is quite fortunate, since this instruction is normally executed prior to the transmission of data (thereby informing the 360 program of this intention). For this reason it is possible in most programming environments to be unaware of the attention signal and its significance to the 360. 2.lU Parity Checking Feature Like the attention feature, the parity checking feature is provided for data transfers in only one direction. In this case, however, incoming data is involved. This data is checked to see if its actual parity agrees with that sent by the 360. Each disparity sets a one bit parity error register in the PDP-7. PE (parity error) is tied to the PDP-7 interrupt system and may be tested by an instruction. The interrupt may not be disabled, but the condition may be cleared -16- by the CPE instruction. Data going to the 360 is not checked for data errors. Data errors may he detected by the 360 on transmission from the 2701 to the 360, but no indication of this reaches the PDP-7. 360 A p 2701 C B^ D Figure 2 Figure 2 -The 360 is capable of detecting errors along data paths A and B, but not on C and D. The PDP-7 detects errors on Data path C, but cannot detect errors on data paths A, B, or D. The 2701 is a standard IBM interface device discussed elsewhere in this report, 2.15 Interrupts The PDP-7 may be interrupted by three separate sources from the communications channel: 1 - 360 issues a read command. 2 - 360 issues a write command. 3 - PDP-7 detects a parity error. If the 360 has actually started an input (to 360) data transfer, the PDP-7 will be interrupted continuously for the duration of the transfer if enabled previously by the ERI instruction. Interrupts from this source (officially termed "Read Select") may be disabled by the DRI instruction. An identical situation exists with respect to an initiated write command from the 360, "Write Select," and the EWI and DWI instructions After interrupting, the source of the interrupt may be identified by the SRR and SWR instructions. Since "Read Select" is on anytime -17- the 360 has issued a read command, it is wise to ignore "Read Select" if the program is not prepared for the transfer. The' same recommendation applies to "Write Select." Parity error interruptions may be identified by the SPE instruction, and cleared by the CPE instruction. The interrupt may not be disabled. Parity errors may show up before the transfer has completed, but they are always indicated no later than completion. When an input /output transfer is completed, the appropriate "Read Done" or "Write Done" switch is set in the PDP-7. Both of these are tied to the PDP-7 interrupt system, and neither may be disabled. Both may be cleared and tested by PDP-7 instructions. 2.l6 Instruction Set Following is a list of the instructions and their individual functions. Please note that "Read" and "Write" are from the standpoint of the 360, not the PDP-7- ERI 705002 DRI 70500U ICR 70501*3 Enable Read Ready Interrupt Sets attention in the 2701, thereby interrupting the 360, and signaling the intention of sending information. Also enables interrupt on "Read Select," which arrives when the 360 initiates a transfer, and remains on until the transfer is complete. Disable Read Ready Interrupt Undoes an ERI. Disallows interrupts on "Read Select." Has nothing to do with attention. Usually issued just before an ICR. Initiate Channel Read Issued when it is known that "Read Select" is on. Actually starts data transfer. Address for transfer is taken from the accumulator during execution of this instruction. Length of transfer is as follows : f( Address )/6U] *6k+6k- (Address ) Asterisk implies multiplication. Remainders are discarded. Address of last word trans- ferred is : [(Address )/6U] *6U+63 -18- where (Address) is the address of the first word. SRR 705001 SRD 705021 CRD 70502U Skip on Read Ready Used to test for readiness of 360 to transfer data. If "Read Select" is on, the next instruction in core will be skipped by incrementing the program counter. If the next instruction in sequence is a transfer, the effect is that of a conditional transfer. Whether interrupt on "Read Select" is enabled or not has no bearing on the effect of this instruction. Skip on Read Done This instruction causes a skip in the identical manner of the SRR instruction. The skip occurs in the presence of "Read Done," which is always on after the completion of a Read operation. "Read Done" is tied to the interrupt system. Clear Read Done Clears "Read Done," thereby handily preventing further interrupts on it. After execution of this instruction, SRD will not. The following instructions have functions identical to the above instructions, except that they apply to the write operation and, therefore, to "Write Select" and "Write Done," rather than their counterparts for the Read operation . EWI 705102 DWI 70 510 1+ ICW 7051^3 SWR 705101 SWD 705121 CWD 705121+ SPE 705161 CPE 705164 Enable Write Ready Interrupt Unlike ERI , this instruction has absolutely no connection with the 360 "Attention" cond- ition. Disable Write Ready Interrupt Initiate Channel Write Skip on Write Ready Skip on Write Done Clear Write Done Skip on Parity Error Skips the following instruction if the PDP-7 has detected a parity error. Clear Parity Error Clears the PDP-7 flag that a parity error has occurred, thereby preventing further interrupts on the parity error condition. -19- 2.2 Programming Example — Interrupt Feature not Employed Figure 3 shows an example of a program that sends information to the 360 from a buffer located at octal location 7000. The NOP instructions are to prevent difficulties that sometimes occur when two IOT instructions are placed right after each other. The ERI instruction is not included for its effect on interrupt, hut for its use in signaling the 360. Note the absence of the EWI and DWI instructions in the second program segment which receives data from the 360. 2. 3 Programming with Interrupt The program in Figure k accomplishes the same function as that in Figure 3, except that it is not necessary to wait until the transfers are completed. The interrupt processor will initiate the desired transfer when the 360 starts one of the input/output operations . Since the 360 can start only one such transfer at a time, both transfers may be requested simultaneously. Please note that this program does not make use of program flags and switches which are essential to determine whether a transfer is in process before issuing some sort of initiating sequence such as ERI and EWI. Also, it is possible that the 360 might not fully cooperate, so some checks should be made before going directly into an ICR or ICW after the appropriate skip instruction. -20- /PERFORM A "READ" . G0, ERI N0P SRR JMP .-1 DRI LAW BUF ICR N0P SRD JMP .-1 CRD 7000/ • BUF BSS 100 /PERF0RM A "WRITE" . SWR JMP .-1 LAW BUF ICW SWD JMP .-1 CWD /SIGNAL DESIRE T0 SEND. /SKIP IF 360 READY. /IF N0T TEST AGAIN. /DISABLE INTERRUPT. /ADDRESS 0F DATA. /INITIATE TRANSFER. /PREVENT I0P CLASH. /WAIT F0R END. /CLEAR D0NE FLAG. /DEF. PR0GRAM C0UNTER. /6k W0RDS F0R TRANSFER, /WAIT F0R 360 T0 SEND. /L00P UNTIL READY. /ADDRESS 0F BUFFER. /INITIATE TRANSFER. /L00P UNTIL C0MPLETE. /CLEAR "WRITE D0NE" . Figure 3 Program to send to the 360 , followed by a program to receive from the 360. -21- 0/ SPE JMP TESTRR CPE DZM ERR0R JMP RETURN TESTRR, SRR JMP TESTRD DRI LAW BUF ICR JMP RETURN TESTRD , SRD JMP TESTWR CRD JMP RETURN TESTWR , SWR JMP TESTWD DWI LAW BUF ICW JMP RETURN TESTWD, SWD JMP 0THERS CWD JMP RETURN START, • ERI EWI /TEST F0R PARITY ERR0R . /CLEAR ERR0R FLAG. /SET ERR0R FLAG IN PR0GRAM /G0 BACK T0 PR0GRAM. /SEE IF READY T0 SEND. /IF S0 DISABLE INTERRUPTS. /GET ADDRESS 0F BUFFER. /START TRANSFER. /G0 BACK T0 PR0GRAM. /SEE IF "READ" FINISHED. /CLEAR D0NE AND /EXIT. /SEE IF READY T0 RECEIVE. /DISABLE INTERRUPTS. /ADDRESS 0F BUFFER /INITIATE TRANSFER. /SEE IF "WRITE" IS D0NE. /G0 TEST 0THER INTERRUPTS. /CLEAR "D0NE" FLIP-FL0P. /PREPARE B0TH 0F /THE 1/0 0PERATI0NS. Figure k Read followed "by Write using interrupt -22- 3. 360 Programming of Channel (Please reread the section on PDP-7 programming, or all is lost.) Now that you have done that : The 360 has four channel commands that may be used with the PDP-7 — Read, Read with timeout, Write, and Write with timeout. The general philosophy for the channel states that when the channel is inactive, it is always feasible to issue a Write command to the channel. It is also feasible to issue a Read command at any time that is desired, however, it is usually more rational to wait for "Attention," which indicates that the PDP-7 has something to say. If your requirements are irrational, however, do not wait on attention, and remove the ERI and DRI instructions from the program in Figure 3 ; this combination will transfer data. After a Read or Write Command, the 360 will quietly wait while the PDP-7 decides to initiate its end by use of the ICR or ICW command. The 360 will wait forever or until a HIO instruction is issued unless Read with timeout and Write with timeout are used. The timeout period is fixed by the device which in this case is a 2701. Timeout for the 2701 is two seconds. Programming of 360 channels and the 2701 is completely standard and is described in the publication IBM System 360 Principles of Operation , form number A22-6821. Significance of all bits in the channel status word (CSW), channel address word (CAW), and the channel command word (CCW) is identical to that for any channel. For this reason only a cursory explanation of the chain of events will be given. The command codes which are supplied in the first byte of the CCW are given in Figure 5. -23- ccw F C0DE ADDRESS L A G C0UNT 7 8 31 32 to 36 U8 63 Command Code — bits to 7 = (in hexadecimal) 1 - Write command 11 - Write with timeout 2 - Read command 12 - Read with timeout Figure 5 Command codes for channel commands for PDP-7 channel. Since most programming of the 360 is not done in a stand-alone fashion, but is done in connection with the supplied IBM operating system, and because a special programmming problem exists in this connection, a special note on in-system programming will follow later. The important thing to remember in programming on the 360 is that it is completely different from the PDP-7 in its simplicity. To read, one invokes the Read command. The same applies to write. The only rule to observe is never start a transfer while a transfer is already taking place. 3.1 Basic Sequence of Operations In order to initiate a transfer, the 360 executes the SIO instruction. When this occurs, the channel specified by SIO fetches the -2k- address of the CCW from the channel address word (CAW) which is at location 72 decimal. The channel then executes the CCW, which contains the address and length for the data buffer in 360 storage. When the transfer terminates and the interrupt for the device occurs, the status for the device will he deposited into the CSW (channel status word) in location 6h decimal. Status contains such flags as channel end, device end, and unit check. Such indications as timeout are obtained through issuance of a sense command (a standard CCW). Timeout for the 2701 is the low order bit of the first sense byte. 3-2 Programming with IBM Operating System In order to execute a channel command (CCW), the programmer simply issues an ESCP macro-instruction (fully described in IBM System/ 360 Operating System System Programmers Guide , form C28-6550) which indirectly specifies the CCW to be executed. Upon termination of the operation, the system automatically gives the channel status word and the results of a sense command at this time. The only requirement that is not easily satisfied is detection of "Attention." The attention condition at one time was closely in- tegrated with the operation of an input/output device being used during individual operations. In the 360 , however, an attempt was made to restrict it to functions that do not concern executing programs, such as "request" on an on-line console typewriter or indications of a disk drive coming into "ready." For this reason, "Attention" has been made very difficult to access, and a modification of the operating system was necessary. It is interesting to note that IBM has produced a channel-to-channel adapter (CTC) which serves much the same purpose as the PDP-7 to 360 channel described herein, and utilizes "Attention" -25- in a very similar fashion. At the time of this writing, however, this device is not supported by IBM software. All programs using the CTC including ASP make use of the software change about to be described. When "Attention" causes an interrupt , the address of the in- terrupt handler is taken from the input/output new PSW. The trick is to provide the address of an interception routine and place in in this PSW. This routine should check the I/O old PSW at location 56 decimal to see if the channel and device causing the interruption are the ones of interest. If so, the CSW at location 6U may immediately be tested for "Attention." If it is on, a program flag may be set. When the routine is finished, it should transfer to the location of the IBM I/O interrupt handling routine originally specified in the I/O new PSW at location 120 decimal. -26- APPENDIX A PDP-T Computer Introduction The sequence of information is so chosen as to supply a logical progression from the PDP-7 processor to the interface of the 2701. The first section describes briefly the PDP-7, the second section points up the important feature break cycle , the third section explains the device selector and the fourth covers the multiplexor. This material is supplied for the reader who is not familiar with the DEC PDP-7. The Digital Equipment Corporation (DEC) Programmed Data Processor-7 ( PDP-7) is a general purpose, stored-program, solid-state digital computer. The PDP-7 is single-address, fixed l8-bit word-length, binary computer using l's complement arithmetic and 2's complement notation to facilitate multiprecision arithmetic. Our PDP-7 contains an 8192-word, random access, ferrite-core memory. The basic PDP-7 includes the processor (with operator console), 8192 word core memory, input/output control with a device selector that permits selection of up to 6U I/O devices, information collector and information distributor. The processor provides facilities for program interrupt, data interrupt (for use with high-speed I/O devices), I/O status check, I/O skip, and I/O trap. The input/output equipment supplied with a basic PDP-7 system consists of a high-speed perforated tape reader (300 char/sec); a high-speed paper tape punch (63-3 char/sec); and a Model 33 KSR Teletype unit (10 char/sec). The computer consists of a processor (with operator console), a core memory, interface equipment, and input/output equipment. Figure 6 -27- >H s o o E5 O Ph H w EH EH O CO & H ffi o Eh CO B a M TO — o K H E-J o H < hj < « s H CO o K CO W K EH O CO EH m <; o o W M K Q a H gj Q CO O H S K O PQ En CO > >H CO w « CO H W Eh W CO O -M Eh O H (2 CO o CO a o o o En Pm O a) O O tH PQ -® •« ®" H2> — •« — ®- *-® — AM — cgh hS> — «w — ®- -Cg> «H Cgr ^s> — •« — ®- ^® — •« — - ^® •« — CgH ^ •«— ®- L — •« — 0- I/OT DEVICE XX SELECT __ COOE ENABLE ^* (CAN 8£ USED FOR SLOW CTClE REQUEST) ® CLIPPING POINT _l Figure T Device Selector Logic Diagram -3k- FLIP CHIP module. These pulse amplifiers normally produce a -2.5v, UoO-nsec pulse , but by jumpering the appropriate terminals on the module , the pulse length can be extended to 1 usee if the nature of the I/O device requires it. Each module contains three pulse amplifiers. One of these, triggered by an I0P1 pulse, produces an IOT XX01 pulse (where XX is the device number) , which may be used to sense the status of a device flag. The second, triggered by an I0P2 pulse, produces an IOT XX02 pulse which may be used to clear the device flag and read the contents of the device buffer register into the accumulator register. The third pulse amplifier, triggered by an IOPU pulse, produces an IOT XXOU pulse which may be used to transfer data from the accumulator register through the information distributor into the device buffer. All three pulses may also be used to initiate control functions with the selected device. Data Interrupt Multiplexer Type 173 Data Interrupt Multiplexer Type 173 consists of 60 FLIP CHIP modules contained in two mounting panels. The Data Interrupt Multiplexer permits the direct transfer of information between the PDP-7 core memory and one of four high-speed I/O devices which can supply 15 address lines, 18 data lines, a request line, and a transfer direction line. The mul- tiplexer services the devices in a preset priority order and routes the address and data supplied by each device into the data interrupt channel of the standard PDP-7 system. The data interrupt channel has priority over all other interrupt requests. When a data break is granted by the central processor on completion of the current instruction, the transfer takes place during one computer cycle, under the control of the I/O device. The maximum combined transfer rate of four devices connected -35- CH ADDRESS (15 L • ADDRESS MIXER I A ADDRESS LINES CH 1 ADDRESS (15L DDRESS (15) FROM SPECIFIC CH 2 ADDRESS (15 L DEVICE CH 3 ADDRESS (15)_ CH DATA (18) < ► DATA MIXER DATA (18) DATA LINES CH 1 DATA (18) FROM SPECIFIC CH 2 DATA (18) -*■ DEVICE CH 3 DATA (18) -*- CH DATA RQ i - V 't A EPXB k) MULTIPLEXER CONTROL T^ t6 CONTROL LINES CH DATA IN/OUX OF DEVICE CH ADDR ACCEPT DATA IN/OUT (XFER DIRECTION) _ CH CH DATA ACCEPT DATA REQUEST _ CH DATA READY REQUEST SLOW CYCLE (IF REQUIRE^ CONTROL T5) ADDRESS ACCEPTED LINES OF (5) P.ATA ACCEPTED DEVICES CH 1-3 (5) DATA READY (SAME AS CH 0) s -CP Figure 8 Data Interrupt Multiplexer Type 173 Block Diagram -36- to the CP through the multiplexer is 570,000 l8-bit words per second. Logical Functions Figure 8 shows a block diagram of the logical elements of the data interrupt multiplexer and their relationship to the central processor. When one or more of the devices connected to the multiplexer generate a channel DATA RQ level (-3 volts), the multiplexer control transmits to the CP a DATA RQ level which causes the DATA SYNC flip-flop in the interrupt control to set at time T5 DLY (delayed) of the current cycle. At time T6 of the same cycle, the multiplexer control selects the device having the highest priority. When the central processor reaches an "instruction done" situation and grants a break cycle, the following events take place : a. At time Tl of the break cycle, the processor transfers the address supplied by the requesting device into the MA, and the multiplexer returns a negative ADDR ACC (address accepted) pulse to the requesting device. b. At time T3, if an in_ transfer has been specified, the processor transfers the data supplied by the device into the MB, and the multiplexer returns a DATA ACC (data accepted) pulse to the requesting device. ( c. At time T3, if an out transfer has been specified, the inform- ation that was stored in the addressed memory cell is held in the MB, and the multiplexer returns a DATA RDY (data ready) pulse to the requesting device, indicating that the requested data is ready for sampling. d. At time T5 the multiplexer priority chain is cleared and the processor interrogates the DATA RQ line. e. If the DATA RQ line is still at -3 volts, the processor grants -37- another break cycle, and the events described in a, through d_ are repeated until all requesting devices have been serviced in order of priority. If the DATA RQ line is at ground, indicating that there is no further data request, the processor fetches and executes the next programmed instruction. Data Interrupt Multiplexer Control Each of the four I/O devices which may be connected to the multi- plexer must supply a -3 volt CH X DATA RQ level when it is ready to receive or transmit data. The four request lines are OR combined in the multiplexer. A data request from any or all of the four I/O devices results in the transmission of a negative DATA RQ level to the break control of the central processor. This DATA RQ level is AND combined with timing pulse T5 DLY to set the DATA SYNC flip-flop. When the processor reaches an "instruction done" situation, the major state generator estab- lishes a break state. In the multiplexer, the CH X DATA RQ level conditions a gate which is triggered by timing pulse T6 of the current computer cycle to set the associated MPX flip-flop. There are four flip-flops, designated MPXO through MPX3. The inverted (l) level of each flip-flop holds all flip-flops of lower priority in the state by pull-over action. Thus, only one flip-flop at a time can be set, and if two or more I/O devices have generated a DATA RQ level concurrently, the MPX flip-flop which is set at time T6 will be that associated with the device of highest priority. The MPX (l) level performs five functions, as follows: a. It conditions the address mixer gates which connect the address lines of the requesting device to the MA. -38- b. It conditions the data mixer gates which connect the data lines of the requesting device to the MB. c. It is NAND combined with the CH RQ IN level to produce a DATA IN level for transmission to the break control of the processor. d. It is applied to one input of a two-input diode AND gate as a check for slow cycle. e. It is applied to the input of a bus driver, whose output con- itions three NAND gates. These are used to generate address accepted , data accepted , and data ready . At time T5 , timing pulse T5 (inverted) is applied to the direct clear inputs of all four MPX flip-flops and resets them to 0. If no other I/O device has generated at CH DATA RQ level in the meantime, the DATA RQ line is at ground and permits timing pulse T5 DLY to clear the DATA SYNC flip-flop in the break control. At the conclusion of the break cycle, the processor will then fetch and execute the next programmed instruction. If, however, a further CH DATA RQ level has been generated, the DATA SYNC flip-flop will remain set and the processor will grant further data break cycles until all requesting devices have been serviced in order of priority. Address Mixer and Data Mixer The address mixer consists of 15 Type Blkl Diode Gate modules and 3 Type B105 Inverter modules each containing 5 inverters. Each Type lUl module contains seven two-input diode AND gates whose outputs are NOR combined. Three of these diode AND gates are unused. In the remaining four gates, one input is conditioned by one of the MPXB levels; the other input is conditioned by an address line from the associated -39- device. The data mixer is similar in operation to the address mixer, except that the input gates are conditioned by the device data lines and that there are 18 bits instead of 15- -1+0- APPENDIX B 2701 Data Adapter Unit Introduction A very short description of the 2701 is given in order to in- dicate the relative position of the Parallel Data Adapter (PDA) to the IBM 360 processor. Most of the material is specifically about the PDA; its functional analysis; its functional sections; its operation. Functional Sections of the 2701 The three function sections of the 2701 are: Channel Interface (CHIP) Transmission Interface Converter (XIC) Transmission Adapter (XA) The XIC and XA operate as a couple, which in conjunction with the CHIF, provides a single complete path for the operation of the terminal devices with the I/O channel. A minimum 2701 configuration contains one CHIF and one XIC-XA couple. Channel Interface (CHIF) An I/O channel (either a multiplexer channel or a selector channel) is a facility that serves as a means of communication between the System/360 processor/main storage and one or more input /output (I/O) devices. It provides for and controls the interchange of data, control, and program information between the processor/main storage and the I/O devices. The channel-interface section of the 2701 provides the circuits to attach the 2701 to a System/ 36O 1/0 channel. It supplies the path for transferring the various control signals, addresses, commands, and data between the 1/0 channel and an XIC and also controls the -Ul- operation of the usage meter. The CHIF is capable of operating with up to four XIC's and will interface normally with one I/O channel, or two in the event the 2701 is equipped with the Second Channel Interface feature. Transmission Interface Converter (XIC) The transmission-interface- converter section of the 2701 controls information and/or controls signal transfers between the System/360 I/O channel (via the CHIF) and a transmission adapter. The XIC operates through the CHIF with either a selector or multiplexer channel. When the XIC is connected to a selector channel, information transfer is always in byte mode; when connected to a multiplexer channel, information transfer is normally in the data-interleave (multiplex) mode. However, in the latter case, an XA can force multiple-byte mode for any number of bytes. The XIC stores channel commands for the transmission adapter and handles byte transfer to or from main storage when requested by the XA. The XIC also responds to specific commands received from the I/O channel and/or specific requests from the XA, initiates operation- ending procedures when requested by the XA, relays an Interface Stop signal from the I/O channel to the XA, and stores the status byte and a sense byte for transfer to main storage. Transmission Adapter (XA) The transmission-adapter section of the 2701 contains circuits necessary for the connection of a remote terminal (station, remote processor, device) to the 2701 and the necessary controls to effect movement of data to or from the channel via the CHIF and XIC. The XA decodes the I/O channel commands presented by the XIC, initiates service requests for data-byte transfer, and provides buffering for each transmitted or received character. Terminal-control functions -1+2- 2 x J I i , i i I , i i J , r> i i i , u U u u U y . _¥ < y r^ r^ c C c c c c X o t— X X o X o X o X o »— 4) 5 c 3 ■ U o X p— a." a. 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" , n A A A A 3 § o cfi w> A A A A 8 s 3 « < e> o fT (J — A A „ s - - C .= — o o — _» O) u T> ** - ° O 1 z e; -^ Commond Bin 0-7 Srotus In Sample Command Accepted 1 Out Sompling Command Ope.ol.o'n Conlroll and Sylc Coonle. Incomplete Data Xle> PDD Unil Ch«ck Doto Check Channel End Device End Unil E«ception Attention Cmd Interrupt Incomplete Doto > XIC Ponly Check Parity Atiign Redundancy Check Data Read Bit P Data Read Bits 0-47 Doto Write Bin 0-47 > PDU FIGURE 11, UNIT DATA AND CONTROL DIAGRAM such as communication-interface control, character and character-sequence recognition, parity checking, sense and status byte generation, end- of-operation , and error detection are performed by the XA. Parallel Data Adapter Introduction The Parallel Data Adapter operates with and is partially controlled by the Transmission Interface Converter (XIC) section of the 2701 Data Adapter Unit. The Parallel Data Adapter presents the external device with a demand/response interface to allow for a half-duplexed exchange of data between the device and the System/360 processor. The IBM 2701 Parallel Data Adapter (PDA) is a Transmission Adapter (XA) of the Data Acquisition and Control type. The PDA serves as a high- speed, variable-word-length buffer between the XIC and the Parallel Data Device (PDD). Data from the processor is received from the XIC in 8-bit bytes, is formed into l6-bit words, and is transferred to the PDD paralle] -by-bit and serial -by -word over a demand/ response type inter- face. Conversely, data from the PDD is broken into 8-bit bytes and is transferred to the System/360 CPU via the XIC. The PDA interprets the I/O channel command presented by the XIC, initiates a Request Service for data byte transfers, performs the necessary operations to form the bytes into a word (or, during execution of a Read command, to break a word into bytes ), then transfers the data to the PDD or to the CPU. When an end-of-operation sequence is initiated by the XIC or the PDD, sense and/or status bits are set to indicate that the sequence has occurred. Functional Analysis of 2701 PDA Operations The XIC initiates any of the operations that the PDA is capable of performing by placing -k6- a valid command on the Command Register lines. The reception and decoding of any valid command causes the PDA to generate a' Command Accepted level and to return it to the XIC. If other than a valid command is placed on the Command Register lines, it is rejected, i.e., the Command Accepted signal is not produced and the XIC sends Command Rejected to the channel. The commands that a PDA can decode and execute are listed in Table 1 and are described below. TABLE 1 COMMAND BIT CONFIGURATIONS Command 1 2 Bit 3 s h 5 6 7 Read Read with Timeout* 1 l Write 1 Write With Timeout* 1 1 Diagnostic Read 1 1 Diagnostic Write 1 1 *Not recognized by the PDA if Timeout feature is not installed. (Read Command). This command controls circuit operations which allow data transfers from the PDD to the PDA and, subsequently, to the XIC and System/360 CPU. (Read with Timeout Command). This command operates the same as a Read command; however, if the PDD does not respond with data within 2 seconds, the Timeout sense bit is activated and the operation is terminated. -hi- (Write Command) . This command controls circuit operations which allow data transfers from the XIC to the PDA and, subsequently, to the PDD. (Write With Timeout Command). This command operates the same as the Write command; however, if the PDD does not accept the data within 2 seconds, the Timeout sense bit is set and the operation is terminated. (Diagnostic Read Command). The operation of this command is sim- ilar to that of a Read operation; the chief difference is that data transfer and control signals between the PDA and the PDD are inhibited. The command should be given following a Diagnostic Write Command. This causes the contents of the data register to be transferred to the XIC, thereby enabling a thorough check of data transfer from the XIC to the PDA and from the PDA to the XIC. (Diagnostic Write Command). The operation of this command is similar to that of a Write operation; the chief difference is that data transfer and control signals from the PDA to the PDD are inhibited. This command causes a series of data bytes to be supplied by the XIC. When the data word has been assembled in the data register, the PDA sets Device End and Channel End. This command is chained to a Diagnostic Read command so that the CPU can retrieve and examine the data transferred. Description of Functional Sections The PDA comprises seven functional sections: 1. Command decoder and byte counter 2. Device controls 3. Logic controls h. Sense and status register -U8- 5. Parity check and assignment 6 . Timeout 7- Data register and bus-in gating (Command Decoder, Operation Controls, and Byte Counter). This section decodes the commands presented by the System/360 CPU via the XIC, initiates execution of the decodes command, and controls the byte counter and transfer of data from the XIC (Bus Out lines) to the data register. Two of the PDA-PDD interface signals (Write Select and Read Select) are also controlled by this section. The byte counter is used to determine when the correct number of bytes has been received or transmitted. Jumper wires allow the byte counter to be extended from two to eight counts to accomodate the ex- tension features. (Device Controls). This section controls the PDA-PDD interface signals (with the exception of those mentioned above and those pertaining to the Parity bit). Control signals are exchanged with other sections of the unit to synchronize PDA operation with PDD operation. (Logic Controls). This section primarily utilizes signals from the command register and from the device controls to generate Service Request, Word Hold, and Stop signals and to reset the data register. (Sense and Status Register). This section contains flip-flops which store the Attention (bit 0), Channel End (bit k) , Device End (bit 5), Unit Check (bit 6), and Unit Exception (bit 7) status bits. The status information is transferred to the XIC when the Status In Early interface signal is down. The Command Interrupt (intervention Required) sense bit (l) and the Data Check sense bit (h) are also generated by this section. The Timeout sense bit (7) and the Incomplete -k9- Data Transfer sense bit (6) are produced by the timeout and command decoder circuits respectively. (Parity Check and Assignment). This section ascertains the validity of all data transfers between the PDD and XIC. During Write Operations, a parity bit is supplied with every byte transferred to the PDA from the XIC. The Parity circuits sample the status of the XIC Bus Out P line during the transfer of each byte from the XIC to the PDA data register. The parity of the word contained in the PDA data register is presented to the PDD. During Read operations, the PDA sends a data byte to the XIC, where a parity assignment is made for that byte. The parity of that byte is returned to the PDA, and byte transfers continue until the complete word has been transferred to the XIC. A check is then performed by the parity circuits to ascertain that the parity of the word transferred was correct. (Timeout). The 2-second timeout produced by this section provides time for the PDD to accept or supply data after a Write or Read command is decoded. If the PDD does not respond within this 2-second limit, device malfunction is assumed, and the Timeout signal is sent to the XIC. Special Read and Write commands are used when timeout is required and are operational only on those PDA's on which the timeout feature is installed. (Data Register). The data register provides a buffer between the XIC and PDD. Eight-bit bytes are received from the XIC and are assembled into a 16-, 2k- , 32-, 1+0- , or 1+8-bit word (a basic PDA has a l6-bit register; however, additional byte capacity can be ordered). The data register then transfers the word to the PDD under control -50- of the command decoder section and the byte counter. Data received from the PDD is broken into a series of 8-bit bytes, which are sent to the XIC one byte at a time under control of the device control section Status Indications The status bits inform the XIC and CPU when an operation is completed or when an abnormal condition of which the CPU should be aware has occurred. The five status bits utilized by the PDA are Attention, Unit Check, Device End, Channel End, and Unit Ex- ception. Sense Indications The sense bits inform the CPU when abnormal or unusual conditions occur within the PDA or the device and further define the indications presented by the status bits. -51- APPENDIX C Interface to 2701 located in PDP-7 NO. TYPE COST/EA. TOTAL 1 R-002 $5.00 $5.00 8 R-107 2U.00 192.00 7 R-lll 1U.00 98.00 11 R-113 20.00 220.00 Ik R-121 17.00 238.00 k R-131 35-00 ll+O.OO 1 R-lUl 13.00 13.00 11 R-202 25.00 275.00 7 R-201+ 28.00 196.00 3 R-302 UU.00 132.00 19 W-021 U.00 76.00 2 W-6U0 1+2.00 8U.00 1 B-171 18.00 18.00 $1687.00 12 W-99U U.1+0 52.80 2 19^3 WMP (RACK) 11+2.00 281+.00 3 100 ft. U918 (IND. PANEL) RIBBON CABLE 96.00 •30/ft. 288.00 30.00 12) Components (X006-X007) 20.00 2U0.00 $2581.80 *The W-99U cards were used for transmitter and receive cards. The receivers were called X-006 and the transmitters were called X-007. It takes six X-006 cards and six X-007 cards for the interface. I have estimated the cost of the various com- ponents that are required. -52- MULTIPLEXER - 173 NO. TYPE COST/EA. TOTAL 1 B-20U 32.70 32.70 h R-lll 1U.00 . 56.00 35 R-lUl 13.00 1*68.00 1 R-603 28.00 28.00 10 B-105 21.00 231.00 1 B-113 23.00 23.00 2 B-68U 52.00 10U.00 3 W-005 15.00 30.00 8 W-021 U.oo 32.00 _3 W-607 1+2. 00 126.00 6k $1111.70 1 1^93 WMP 1U2.00 1U2.00 50 ft. 19 Conductor Ribbon Cable .30/ft. 15.00 20 932 Bussing Strips .60/ea. 12.00 TOTAL $1280.70 A cost of one rack was saved by combining the multiplex circuits and 2701 interface circuits in the same area. -53- Form AEC-427 (6/68) AECM 3201 U.S. ATOMIC ENERGY COMMISSION UNIVERSITY-TYPE CONTRACTOR'S RECOMMENDATION FOR DISPOSITION OF SCIENTIFIC AND TECHNICAL DOCUMENT ( See Instructions on Rmnrm Side ) 1. AEC REPORT NO. COO-1U69-0116 Report No. 323 2. TITLE DEC PDP-7 Interface to IBM 2701-PDA 3. TYPE OF DOCUMENT (Check one): fyl a. Scientific and technical report I I b. Conference paper not to be published in a journal: Title of conference Date of conference Exact location of conference Sponsoring organization □ c. Other (Specify) 4. RECOMMENDED ANNOUNCEMENT AND DISTRIBUTION (Check one): [x] a. AEC's normal announcement and distribution procedures may be followed. I I b. Make available only within AEC and to AEC contractors and other U.S. Government agencies and their contractors. I I c. Make no announcement or distrubution. 5. REASON FOR RECOMMENDED RESTRICTIONS: 6. SUBMITTED BY: NAME AND POSITION (Please print or type) C. E. Carter, Research Engineer R. L. Miller, Elec Tech. II H. E. Lopeman, Electronics Engineer A. D. Whaley, Research Assistant Organization Department of Computer Science, University of Illinois, Urbana, Illinois FOR AEC USE ONLY 7. AEC CONTRACT ADMINISTRATOR'S COMMENTS, IF ANY, ON ABOVE ANNOUNCEMENT AND DISTRIBUTION RECOMMENDATION: 8. PATENT CLEARANCE: □ a. AEC patent clearance has been granted by responsible AEC patent group. □ b. Report has been sent to responsible AEC patent group for clearance. I I c. Patent clearance not required. NOV 2 8 W2 "-'•rn.lr.port/ ° ?n ° K3 'NO OME