LIBRARY OF THE 
 
 UNIVERSITY OF ILLINOIS 
 
 AT URBANA-CHAMPAIGN 
 
 XSHaY 
 C.oO.% 
 
/n^j^ 
 
 T HO^^ 
 
 >"^ Report No . 382 
 
 ^' PARALIxEL SIMULATION OF DIGITAL SYSTEMS 
 
 ■by 
 
 Chiyozi Tanaka 
 
 April 30, 1970 
 
 ILLIAC rV Document No. 211 
 
Report No. 382 
 
 PARALLEL SIMULATION OF DIGITAL SYSTMS* 
 
 Chiyozi Tanaka 
 
 April 30, 1970 
 
 Department of Computer Science 
 
 University of Illinois at Urb ana- Champaign 
 
 Urbana^ Illinois 618OI 
 
 -X- 
 
 This work was supported in part by the Advanced Research Projects 
 Agency as administered by the Rome Air Development Center under 
 Contract No. USAF 30(602)-Ul44 and submitted in partial fulfillment 
 of the requirements for the degree of Master of Science in Computer 
 Science^ January 1970- 
 
Digitized by the Internet Archive 
 in 2013 
 
 http://archive.org/details/parallelsimulati382tana 
 
11 
 
 ABSTRACT 
 
 The paper describes the method used to generate the parallel 
 simulator developed for the ILLIAC IV Project, University of Illinois. 
 The basic approach to achieve an efficient simulator system is parallel 
 logic simulation, package-level simulation, the use of a high level 
 language (ALGOL) and a flexible simulation control language (TESLA)- 
 This paper analyzes the problems associated with the ideas and gives 
 the algorithms used to generate the simulator. Emphasis is placed on 
 the algorithms and the implementation of the simulator generator system. 
 
Ill 
 ACKNOWIJ]D(MENT 
 
 The author would like to express his deep appreciation to 
 Professor Kenji Naemura for his guidance and many helpful suggestions in the 
 writing of this thesis. Also, many thanks to Mr. Arthur B. Carroll and to 
 Mr. Luther C. Abel for their advice and criticisms. The author is also indebted 
 to his co-worker, Prathima A. Agrawal, who wrote part of the programs of the 
 system. 
 
 Thanks are also extended to the Diagnostic Group personnel for their 
 helpful discussions. 
 
 Furthermore, many thanks go to Mrs. Kay Flessner, who did such a 
 fine job of typing this thesis. 
 
IV 
 
 TABLE OF CONTENTS 
 
 Page 
 
 1. INTRODUCTION 1 
 
 2. CONSIDEE^TION OF A SIMULATOR DESIGN 1+ 
 
 3. ORGANIZATION 10 
 
 3.1 Simulator Generator Group 10 
 
 3.2 Simulator 11 
 
 3-3 Result Display Group 12 
 
 3.^ Simulator Control Language 12 
 
 h. ALGORITHMS FOR THE SIMULATOR BODY GENERATOR I7 
 
 4.1 Definitions I7 
 
 k.2 Level Assignment I9 
 
 4.2.1 Level Assignment for a Link Graph I9 
 
 4.2.2 Determination of All Nodes Bounded by- 
 Maximal Strongly Connected Subgraphs 24 
 
 4.2.3 Level Assignment for Any Graph 24 
 
 4.3 Loop Detection 26 
 
 4.3-1 Determination of R Matrix 26 
 
 4. 3 '2 Determination of Maximal Strongly 
 
 Connected Subgraphs 28 
 
 4.4 Ordering 33 
 
 4.4.1 Determination of the Longest Paths in a Graph [6] . . .36 
 
 4.4.2 An Algorithm to Find the Longest Paths 39 
 
 4.5 Algorithm for Generating the Simulator Body 4l 
 
V 
 
 Page 
 
 5. SIMULATION CONTROL LANGUAGE (lESLA) ^8 
 
 5.1 Declaration kQ 
 
 5.1.1 Program kQ 
 
 5.1.2 Declarations kQ 
 
 5.2 Control Statement 50 
 
 5.2.1 Input Control Statements 50 
 
 5.2.2 Storage Element Control Statements 50 
 
 5.2.3 Output Control Statements 51 
 
 5.3 A Sample Program 52 
 
 6. SIMULATOR CONTROLLER 56 
 
 7. IMPLEMENTATION 58 
 
 7.1 TESLA Compiler 58 
 
 7.2 Simulator Generator Group 58 
 
 7.3 Simulator 62 
 
 7.4 Result Display Program 62 
 
 8. CONCLUSION 6k 
 
 APPENDIX 
 
 A A Sample Update Listing of CUBC/UPDATE 66 
 
 B A Sample Signal Sort Listing of CUBD/WEDTRl 67 
 
 C Listings of CUBD/WEDTR2 69 
 
 D Listings of CUBD/LEVELER 7!+ 
 
 E Listings of CUBD/REDUCE 78 
 
 F Listings of CUBD/HSKEEP 80 
 
 G Listings of CUBD/SIMGEN 81+ 
 
 H A Sample Output Listing of <BOARD NAME>/SIMULA ' . 86 
 
 LIST OF REFERENCES . . . .' 9I 
 
VI 
 
 LIST OF FIGURES 
 
 Figure Page 
 
 1. General Flow of Logic Simulator System ik 
 
 2. Flow of Simulator Generator System 1^ 
 
 3' The Fionction of Simulator l6 
 
 k. An Example of Ascending Level Assignment 22 
 
 5- Level Assignment of Any Directed Graph 25 
 
 6. An Example of the Determination of Maximal 
 
 Strongly Connected Graphs in G 29 
 
 7- An Example of Node Ordering and its Logical Connections .... 3!^ 
 
 8. The Modified Order and Its Logical Connections 35 
 
 9' An Example of the Determination of the Longest Paths 38 
 
 10. An Example of a Graph for the Simulator Body Generator i+3 
 
 11. Extracted Graph Bounded by Loops kk 
 
 12. Condensed Graph of the Example k6 
 
 13' An Example of TESLA Program 5^ 
 
 lU. A Sample Format of TESLA Object Command 57 
 
 15- Program System of Simulator 63 
 
1. INTRODUCTION 
 
 The introduction of integrated circuitry and large scale integration 
 is changing the trend in logical design and simulation of computers [4], Elec- 
 trical and mechanical limitations on semiconductor and packaging technology 
 place significant restrictions on logic design and the partitioning and logic 
 design must be an iterative process to arrive at a completed design. 
 
 Because of the nature of the fabrication, the logic of a machine must 
 be described in several levels such as a) the logic in an IC package, b) the 
 interconnection of IC's within a printed circuit board (on which 20 ~ 150 IC 
 packages can be mounted in general), c) the connection among printed circuit 
 boards within one section, d) the connection among sections. 
 
 From the view of the manufacturing processes, the logic in an IC 
 package or printed circuit wiring on a printed circuit board cannot be changed 
 as easily as the discreetly wired connection within a section; therefore, de- 
 bugging an original design before the design is committed to hardware is being 
 increasingly emphasized. Additionally, as the design of computers has become 
 more complicated and more sophisticated, it has become almost impossible for 
 a designer to design an error-free computer without the assistance of some tool 
 to examine his design. 
 
 One of the purposes of the logic simulator system is to provide the 
 designer with more inmiediate design help by which he can exercise ample test 
 programs on his logic and obtain detailed information to determine if his design 
 is correct. After the logic design is debugged, the machine will be constructed 
 and checkout of the machine follows. In this stage, failure detection or iso-^- 
 lation of faulty components is required. 
 
The simulator can be used not only for debugging the logic of a com- 
 puter, but also for the generation of diagnostic test patterns, i.e., if the 
 simulator is modified so that a description of failiires of each element is in- 
 corporated in the simulator, it can calculate the output pattern for a certain 
 failure (fault insertion) and certain input pattern; and if this output pattern 
 is different from the correct output pattern, which is calculated by the orig- 
 inal (correct) simulator, then the input pattern which produced these outputs, 
 can detect the above failure. Thus, if the simulator is modified so as to 
 simulate failures in the logic, the simulator can be used to generate fault 
 detection tests [9]. In order to generate fault test patterns, the simulator 
 must basically be executed for each failure by applying input patterns until 
 some input pattern detects a given failure. In general as the input patterns 
 are randomly chosen, the simulator must be executed many times to find the 
 patterns for all possible failures. For this purpose, the speed of execution 
 of the simulator is very important. 
 
 Many efforts in the field of logic simulation have already been 
 made. The most frequently used technique for a logical simulation is a so- 
 called gate -level simulation, which means that a set of logical equations is 
 compiled into a string of executable computer instructions and the simulation 
 is accomplished by executing the resulting program a given number of clock 
 times. However, the disadvantage of the gate level logic simulator is that 
 regardless of mechanical organization of the logic, the logical equations of 
 the whole machine to be simulated must be specified in one single description 
 to the simulator; therefore, if a machine is too big to be simulated at one 
 time, the logical designer must partition the whole system into several blocks 
 
by hand and write all the equations for each block, which in turn causes extra 
 work and less accuracy of logic debugging. In this paper, a simulator system 
 is presented which is generated from the interconnection list (wire list) and 
 preserves the mechanical organization of the logic. 
 
 Although it is necessary to have several simulators of various levels, 
 such as a printed circuit board simulator, a section simulator and a machine 
 simulator, only the printed circuit board simulator is described, which is used 
 extensively for ILLIAC IV printed circuit board debugging and test pattern 
 generation, because the other simulators are designed in the same way. 
 
2. CONSIDERATION OF A SIMQLATOR DESIGN 
 
 The requirements for a simulator should vary according to the organ- 
 ization and the fabrication of a computer. Desirable specifications for a 
 logic simulator including fault test generation can be described as follows: 
 
 l) The construction of the simulator should conform as closely 
 as possible to mechanical organization of the logic. 
 
 The logical description of a computer will be partitioned 
 to IC package^ printed circuit board, section and system, and 
 the only available information from the design process will 
 be the logic description of IC packages, the connection list 
 within a printed circuit board, the connection list within 
 one section and the connection list among sections within 
 a system. Therefore, the logic equations of a whole system 
 will not necessarily be produced for the production process. 
 
 From this point of view, it is desirable to design a 
 logic simulator which requires as input a description of 
 the IC packages used in the design and the wire-list. In 
 addition, once a basic simulator - a printed circuit board 
 simulator - is designed, it is desirable to construct the 
 other simulators using the same procedures as the basic 
 simulator by just collecting each printed circuit board 
 simulators. 
 
2) The simulator should be easily updated. 
 
 The logic internal to an IC package may not be changed 
 as easily as the connections on a board (during the design 
 phase) or the backplane connections among boards. The con- 
 struction of the logic simulator should have the same nature. 
 It is desirable that any change in design may be reflected 
 in different ways in the simulator; therefore, the simulator 
 can be much more easily updated if those different connections 
 can be distinguished one from the others. 
 
 3) The logic described in the simulator should be easily under- 
 standable to a designer. 
 
 In general logic debugging may be done by reviewing 
 logical equations and/or logic diagram. If the simulator 
 gives a designer a complete set of logical equations, the 
 designer can directly work with the simulator to find input 
 patterns for the simulator or to debug his logic and to change 
 the logic. 
 
 h) Failure insertion to the simulator should be achieved with 
 minimum effort. 
 
 After completion of logic debugging, the simulator will 
 be used for generation of failure detection tests. This is 
 achieved by inserting additional information for each element 
 which specifies the failure modes of the elements into the 
 simulator; therefore, this modification should be as easily 
 as possible. 
 
5) The speed of the simulator should be fast. 
 
 One of the most important points for a simulator is how 
 fast the simulator is. Since a computer performs Boolean 
 operations on full data words, it is possible to associate a 
 different test case with each bit in one word. Those test 
 cases in one word will then be calculated in parallel; there- 
 fore, the effective speed of the simulation will be increased 
 as many times as the number of usable bits of one word. 
 
 In order to accomplish those objectives, four major ideas are em- 
 ployed in the simulation system. They are parallel processing logic simula- 
 tion, package-level simulation, the use of a high level language (ALGOL) and 
 a flexible simulation control language called TESLA (TEst Simulator LAnguage). 
 
 Package level simulation is similar to gate-level simulation. How- 
 ever, input data to the simulator generator is a logic description of each IC 
 package and the connections between those IC packages in the case of a printed 
 circuit board simulator, therefore, the designer need not write all the Boo- 
 lean equations for input to the simulator. If the wirelist and the logic 
 description of the IC packages are correct, the simulator can be generated 
 automatically. The idea of package-level simulation is that the logic of each 
 IC package is described in one subroutine and the simulator body which means 
 the simulator program without its control program for controlling it or com- 
 municating with its user is a well-ordered sequence of subroutine call state- 
 
 *The computer used for this simulation system is Burroughs -5500. 
 One word consists of U8 bits and k'J bits are usable. Hence, ^7 different 
 test cases can be evaluated in parallel by this system. 
 
merits and the associated parameters correspond to the signals among those IC 
 packages. Hence, only the logic of a package is described by a set of Boolean 
 equations. 
 
 This technique can be easily utilized to a section simulator in which 
 one subroutine described the logic on one printed circuit board and the simu- 
 lator body is again a sequence of subroutine calls and the parameters correspond 
 to the interface signals between those printed circuit boards. Therefore, it 
 is advantageous to use a high level language so that a subroutine can define 
 the connection between packages. Besides, the logic of the simulator is more 
 easily understood when written as a single high-level language statement rather 
 than a series of assembly code statements. To modify the simulator to permit 
 failure insertion, it is then only necessary to modify the sets of logic equa- 
 tions which describe the logic of each IC package type. 
 
 This approach, however, gives rise to several problems to be solved 
 as follows : 
 
 1) How to order the packages involved in loops. 
 
 2) To which level to assign packages containing storage elements. 
 
 3) The requirements for parallel processing. 
 
 k) How to obtain better efficiency of the simulation. 
 
 The subroutine calls must be ordered properly so that the propaga- 
 tion of control and data signals can be followed. The order is defined by 
 
the assigned levels and the simulation of packages is executed in accordance 
 with the levels. However, as the assignment of levels is not originated from 
 the logic equations of packages but from the wiring between packages, there may 
 exist loops for which the level cannot be assigned. This loop means that the 
 input to some package is dependent on the outputs from a previous package whose 
 input is in turn dependent on the outputs of the package before that and so on 
 until the package whose inputs are dependent on the output of the original pack- 
 age, assuming that there is no logical loop but a physical loop. For the first 
 problem, since the level cannot be assigned to those packages, one level is 
 assigned to a set of looped packages and the simulation is performed iteratively 
 for these packages until all of the logical values within the loop have sta- 
 bilized. 
 
 The second problem can be solved by duplicating a storage package into 
 two nodes. Since this simulator evaluates logic at one clock time and the out- 
 put of a storage element does not change its value during the period and 
 its input value is transferred to its output only at the end of one 
 clock time simulation; hence it can be divided into two parts; the output part 
 having no incoming signal and the input part having no outgoing signal. If a 
 storage package is thus partitioned, the level of the output part is assigned 
 to the first level and the level of the input part to the last level. 
 
 For the third problem, each signal occupies one word whose bits 
 correspond to test cases. Binary Boolean operations are executed on full 
 word on the Burroughs -5500, but if the Boolean value of one word is interro- 
 gated, only the forty- seventh bit is evaluated; and if this bit is locial one, 
 its entire value is true and otherwise false. Therefore, if tests of entire 
 Boolean values are required, such as the stabilization test, comparison with 
 
each bit in a word should be made. The other case is when a signal is always 
 a constant value, such as a constant voltage connected to a pin. If logical 
 one is assigned to some signals, this corresponding signal should be filled 
 with all ones instead of being assigned with true, in which case only the forty- 
 seventh bit is set to one. Therefore, arithmetic expressions are used instead 
 of Boolean. 
 
 In order to obtain better efficiency, several improvements can be 
 considered. As already stated, the package level simulation is based on a 
 sequence of subroutine calls, however, the linkage of those subroutine will 
 take considerable time. Hence, instead of generating the subroutine calls, 
 it is more efficient to generate a sequence of sets of logical equations ex- 
 plicitly, in which case each pin of a package is replaced by a signal name. 
 
 The second point of the improvement is that if the loop consists of 
 many packages, the efficiency of the simulation - how fast the values of looped 
 packages will stabilize - depends on the order of the packages within a loop. 
 The efficient iterative order of simulation of the packages is along the 
 longest path within the loop which does not pass through any package twice. 
 
 The third improvement is that if there are more than one independent 
 loops within unassigned packages, more efficient simulation can be obtained 
 by assigning each loop to a different level although the original level assign- 
 ment program may assign those independent loops to the same level in order to 
 minimize the number of packages within a program loop. However, the second 
 and third improvements are not implemented in the current system because the 
 number of looped package is so few that significant advantages cannot be 
 achieved. The level assignment, loop detection and ordering algorithms are 
 described in the following section in detail. 
 
10 
 
 3. ORGANIZATION 
 
 The logic simulator system consists of four major groups of programs: 
 the simulator generator group, the simulator itself, the result display group 
 and simulator control language compiler. The general flow of this system is 
 shown in Figure 1. [l] 
 
 3.1 Simulator Generator Group 
 
 The input to this group is a wirelist which describes package inter- 
 connections and descriptions of each IC package used on printed circuit board. 
 First, the wirelist is edited so that it contains only logical signals for the 
 simulation and is updated if necessary, and each signal is classified to input, 
 output and internal signal with respect to the connector of a board so that 
 these signals may belong to proper corresponding arrays in the simulator. 
 Then a representation of the board in the form of a directed graph is produced; 
 in which a node of the graph corresponds to each IC package and an arc of the 
 graph to connections from a package's output to another package's input. Be- 
 fore generating the directed graph, a package of storage element is split into 
 two nodes, one corresponding to the package's output and the other to the pack- 
 age ' s input . 
 
 During these processes signal sort listing and pin sort listing are 
 generated; and if there are errors in the wirelist, error messages are printed 
 for reference to a designer. 
 
 The directed graph representation is used for input to the level 
 assignment program. Ascending and descending level assignment are carried out 
 as far as possible. The remaining nodes will be either members of loops or 
 
11 
 
 bounded by loops. For those remaining nodes, loop detection Is carried out 
 and each loop is replaced by a pseudo node. Once all loops are replaced by 
 pseudo node, no loop exists in this subgraph of the remaining nodes, therefore, 
 level assignment is again carried out for this subgraph so that all packages 
 and pseudo-nodes are assigned to proper level. Each loop is examined to be 
 ordered for efficient simulation and then the final determination of the order 
 of simulation is made. With this output in which each package is ordered 
 properly for the correct and efficient simulation and signal array list gen- 
 erated by the first part of this group, ALGOL codes are generated to simulate 
 the logical function of each IC package associated with the node. • 
 
 In case of looped packages, before generating sets of Boolean equa- 
 tions a program loop statements and stability test statements are added. The 
 variables used in these Boolean equations are the simulation variables asso- 
 ciated with the signals connected to those packages. 
 
 Those sets of logical equations in ALGOL coding called the simulator 
 body is merged with manually prepared simulator control program called "head 
 and tail, " and a complete simulator program will be produced automatically. 
 The flow of this group is shown in Flg-ure 2. 
 
 3.2 Simulator 
 
 The simulator consists of three major sections: the simulator head, 
 the simulator body, and the simulator tail. 
 
 The simulator body consists of properly ordered sets of logical 
 equations which describe the function of all packages within a printed circuit 
 board generated by the simulator body generator group whose function is that 
 given inputs to a board and the states of all storage elements on the board 
 
12 
 
 at any particular time, the simulator body will calculate the outputs from the 
 hoard and the next states of all storage elements. 
 
 The simulator head consists of control routines which pass interface 
 signal values and storage element states to the simulator body and translate 
 various control commands generated by the TESLA compiler to control the execu- 
 tion of the simulation with a given set of signal values. 
 
 The simulator tail governs the creation of an output file which con- 
 tains the simulation results and also controls the simulation such as the ter- 
 mination and, in conjunction with the simulator head, controls looping or 
 iteration through the simulator in simulation of sequential clock pulses. The 
 function of the simulator is shown in Figure 3- 
 
 3.3 Result Display Group 
 
 The result display program processes the simulation result file 
 and decompose this parallel simulation output to the output of each test case. 
 The outputs are then edited and printed in a desired form which is specified 
 by the print commands of the simulator control language. 
 
 3.^ Simulator Control Language 
 
 To permit a designer to utilize the full range of simulation capa- 
 bilities, a simple simulator control language ('TESLA) is used for various 
 control of the simulation. TESLA is fundamentally an assembler-like language. 
 Statements in the language consist of declarations and test steps. Declara- 
 tions are used to associate lists of interface and storage signal names with 
 single identifiers (internally array elements), and similarly to associate bit 
 patterns with identifiers. 
 
13 
 
 A Test Step is defined to be the simulation of one clock interval. 
 During a test step the following actions will occur in the order indicated, 
 a) Adjust the input values and storage element contents; h) Simulate the 
 action of the combinational logic during the interval; c) Store the output 
 values and next storage element states. For the control of these actions, a 
 test step with respect to TESLA consists of a step label followed by a series 
 of input, storage element and output control statements. One prominent feature 
 of this language is that a declaration or a statement can specify simultaneous 
 generation and control of many simulations. The further description of the 
 language is described in Section 5- 
 
Ik 
 
 / 
 
 INPUT 
 
 WIRELIST 
 a IC PACKAGE 
 DESCRIPTION 
 
 TESLA COMPILER 
 
 I 
 
 SIMULATOR 
 
 BODY 
 GENERATOR 
 
 SIMULATOR 
 
 I 
 
 RESULTS DISPLAY 
 
 I 
 
 SIMULATION 
 RESULTS 
 
 Figure 1. General Flow of Logic Simulator System. 
 
15 
 
 WIRELIST AND 
 SIGNAL ARRAYS 
 
 ORDER OF 
 SIMULATION 
 
 ORDER OF 
 SIMULATION 
 
 LOGIC PACKAGE 
 DESCRIPTION 
 
 SIMULATOR 
 
 BODY 
 GENERATOR 
 
 SIMULATOR 
 PARAMETERS 
 
 MERGE 
 
 (simulator j 
 
 SIMULATOR 
 HEAD a TAIL 
 
 Figure 2. Flow of Simulator Generator System. 
 
16 
 
 NO CHANGE 
 
 STORE 
 
 n 1 r 
 
 -DATA- 
 
 •ZERO 
 
 NO CHANGE 
 — PRESET — I 
 
 CLEAR 
 
 INPUT CONTROL 
 
 'IL 
 
 II II 
 
 TRANSFER 
 
 STORAGE CONTROL 
 
 INPUT ARRAY 
 
 INTERNAL ARRAY 
 
 STORAGE STATE 
 
 COMMENT LEVEL =0 A029 (DIL008) 
 
 c [092] •-NOT (c [093] "•— [1 e] ) ; 
 
 0q[i6] ■•— (C[095] AND c[o9l]) OR (c[090] OR q[i6]); 
 
 b[04o]*-NOT (b[04|] -•— q[|7]); 
 
 0q[|7] *— (C[095] AND c[09l])0R (c[o9o] OR o[l7]); 
 
 COMMENT LEVELS AI02 (DIL022) 
 
 c[026]*-N0T (C[025] <•— (a[033] AND a[03o] AND VTRUE)); 
 
 c[0l4]-«— NOT(0EMPTY ♦- (a[030] AND VTRUE AND VTRUE)); 
 
 COMMENT LEVEL = 100 A066 (DIL008) 
 0EMPTY «— NOT (b[085]— q[|0]); 
 
 Qq[|0] ••— (a[0I5] AND c[l65]) OR (c[l64] AND q[io]); 
 
 tr 
 o 
 
 ^^ 
 
 1 
 
 o 
 (?) 
 
 I 
 
 Figure 3* The Function of Simulator. 
 
17 
 
 h. ALGORITHMS FOR THE SMUMTOR BODY GENERATOR 
 
 The problems of level assignment, loop detection and the ordering 
 can be clearly defined in term of directed graph [3]^ [5]^ C?]^ [8]. In order 
 to convert from a wirelist to the graph, the wlrelist must be changed to a 
 directed branch list in which a node in the graph corresponds to a package and 
 a directed branch to a connection between packages so that there is no parallel 
 lines between any two nodes since parallel lines cannot be distinguished from 
 each other in a graph. 
 
 The following definitions are necessary to establish those algo- 
 rithms: 
 
 k.l Definitions 
 
 A directed graph is a set of nodes connected by directed branches. 
 A path is a sequence of directed branches connected in series between two nodes 
 without passing a node twice. A loop is a sequence of nodes such that a path 
 exists from a node to Itself. Node j is said to be reachable from node 1 if 
 there Is at least one directed path from node 1 to node j. A subgraph of a 
 given graph is defined as a subset of nodes with all branches between these 
 nodes retained. A graph consisting of a set of nodes and branches is said to 
 be strongly connected if and only if any nodes are reachable from any others. 
 The maximal strongly connected subgraph is a strongly connected subgraph which 
 includes all possible nodes which are strongly connected with each other. A 
 link graph is a graph which has no loops. Mathematical definition of a graph 
 can be stated as follows: 
 
18 
 
 A graph, which is denoted by G = (X, P) is the pair consisting of 
 the set X of nodes and the function P on X. If x and y are two nodes such that 
 Y e P X, they are joined by a branch pointing from x to y. The following oper- 
 ations of P are defined: 
 
 i) P^ X = P (P x) 
 
 p" X = P (P^""^ x) = P P P X 
 
 li) The transitive closure of P is a function P defined by 
 
 rx={x} U{Px} U{P^x} UfP^x} U 
 
 P "" X = { X } U {P X } U (P^ X ) U U [P"" X } 
 
 iii) The inverse of P is a function defined by 
 r'"'" y = { X I y G P X } 
 
 If B is a subset of X in a given graph G = (X, P) 
 r"''"B= [x|PxnB+(p) 
 
 A graph can also be represented by a square matrix of order n, 
 where n is the number of nodes 
 
 iv) An adjacency matrix A(G) of a graph G is defined by 
 
19 
 
 A(G) = [a ] 
 
 a. . = r 1 if X. G r X. 
 IJ / J 1 
 
 if X * r X. 
 ,1 ^ 1 
 
 v) A reachability matrix R(g) of a graph G which indicates 
 
 whether node x. is reachable from node x. is defined bv 
 3 X ■^ 
 
 R(G) = 
 
 = f^io-l 
 
 
 
 
 7 
 ij 
 
 r 
 
 if X. € r X. 
 
 J 1 
 
 
 
 lo 
 
 if X i r X. 
 3 ^ 1 
 
 I 
 
 L 
 
 4.2 Level Assignment 
 
 4.2.1 Level Assignment for a Link Graph 
 
 The level assignment is to assign integer values to the nodes of a 
 link graph G. The graph G has an ascending level assigranent, and the in- 
 tegers are levels if for each branch (a., a.)* (a- ^ T a.) in G the correspond- 
 
 ing integers satisfy n., <n .. Also the graph G has a descending level assign- 
 
 ■'- J 
 
 ment, if for each branch (a., a.), (a. e Pa.) inG the corresponding integers 
 
 J- J J •*• 
 
 satisfy n. > n. . 
 
 The assignment of levels to a given link graph is defined by the 
 following : 
 
 Let X be a set of all nodes in a link graph G. 
 Let a. (i = 1, 2, ... p) be the node of the graph G. 
 
20 
 
 a) Ascending level assignment 
 
 i) The set A(0) of level zero nodes is defined "by 
 
 A(0) = { a. I r"^ a. = cp ) 
 
 ii) The set A(n) of level n nodes is defined by 
 
 A(n) = { a. I r'"- a. c U A(j)} 
 
 j=o 
 
 b) Descending level assignment 
 
 i) The set D(0) of level zero nodes is defined by 
 
 D(0) = { a^ I r a^ = op} 
 
 ii) The set D(n) of level n nodes is defined by 
 
 n-1 
 D(n) = { a. I r a. ^ U D( j)} 
 
 From these definitions the following theorem results: 
 Theorem 1 . The following properties of a directed graph G are equivalent. 
 
 (1) G has no strongly connected subgraph, i.e., a link graph. 
 
 (2) It is possible to order the nodes of G so that its adjacency 
 matrix is upper triangular. 
 
 (3) It is possible to assign levels n. to the node a. in such a 
 
 way that if a. e P a. in G, then n. > n.. (This assignment 
 
 is of ascending order and the same argument is also true for 
 descending level assignment.) 
 
 Proof: 
 
 (1) - (2) 
 
 Since G has no strongly connected subgraph, there exists at least 
 one node which has no incoming branches. Let those nodes be A(0). 
 
21 
 
 If B is a subset of the nodes of G^ we define G-B as the subgraph obtained by 
 
 deleting the nodes of B and all branches of the graph originating in B. . Since G 
 
 has no strongly connected subgraph, G - A(0) also has no strongly connected 
 
 subgraph, therefore G - A(0) also has at least one node which has no incoming 
 
 branches. Let those nodes be A(l). By continuing the process, all nodes of G 
 
 can be partitioned to one of A(i). With the nodes of G ordered in this way, 
 
 let A(g) = [^. .] be its adjacency matrix. Since by the construction of this 
 
 matrix, there is no branch from a node of A(i) to a node of A(j) in G if i > j. 
 
 Hence the corresponding entry a. . =0. 
 
 -'-J 
 
 (2) - (3) 
 
 Suppose the nodes of A(G) have been ordered so that A(G) is upper 
 triangular. A(i) can be assigned to level i since a. . = o if i > j , i.e. , 
 there is no branch from a node of one level to one of a lower level. 
 
 (3) - (1) 
 
 If G satisfies (3)^ then all nodes in G must be assigned levels. 
 However, suppose there is a strongly connected subgraph in G and let the mem- 
 ber of the node be 
 
 ^2_' ^2' "' \' ^^ - ^^ 
 
 Then a. e T a, and a € r a. (i, k=l, 2, . . . n) 
 
 and n. > n^ and n. < n, which contradicts (3) 
 
 therefore G has no strongly connected subgraph. 
 This completes the proof of theorem 1. 
 
Example 1. Ascending level assignment of Figure k. 
 
 22 
 
 Figure h. An Example of Ascending Level Assignment 
 
23 
 
 A(g) = a. 
 
 h ^2 ^3 % S % ^ 
 
 10 10 
 
 110 
 
 
 
 10 1 
 
 10 
 
 10 1 
 
 
 
 Using above mentioned process, A(G) can be rearranged as the 
 
 following ; 
 
 A(G) = a 
 
 2 
 
 % 
 ^3 
 
 3-]_ ^■ir 3-2 ^g ^[|. ^O ^ 
 
 110 
 
 10 
 
 110 
 
 10 1 
 
 11 
 
 
 
 
 
21+ 
 
 From this matrix, 
 
 A(0) = C a^, a^ ) 
 
 A(l) = { a^, a^ ) 
 
 A(2) = { a^ ) 
 
 A(3) = { a^, a^ } 
 
 4.2.2 Determination of All Nodes Bounded by Maximal Strongly Connected 
 Subgraphs . 
 
 From the definition of ascending and descending level assignment, 
 
 the set L of nodes which are bounded by maximal strongly connected subgraph 
 
 is obtained by 
 
 n m 
 
 LC X - U A(i) U U D(i)) 
 i=o i=o 
 
 where n and m are the largest level in ascending and 
 descending level respectively. 
 
 4.2.3 Level Assignment for Any Graph 
 
 In general, a directed graph may have some strongly connected sub- 
 graphs and some nodes may be bounded by strongly connected subgraphs. In this 
 case, as stated in Section 4.2.2, the levels cannot be assigned to these nodes. 
 However, the idea of the level assignment can be generalized from link graph 
 to all directed graph. 
 Theorem 2 . Every node in any directed graph can be assigned a level if the nodes 
 
 of a maximal strongly connected subgraph are all assigned the 
 
 same level. 
 
25 
 
 Proof: If the nodes of maximal strongly connected subgraph are assigned 
 the same level^ these nodes can be treated as one node. When this is 
 done_, the resulting condensed graph has no loops; therefore all nodes 
 can be assigned to a level by the definition of the level assignment. 
 
 Example 2. 
 
 Level assignment of any Directed Graph. 
 
 (a) 
 
 Example of a directed graph 
 having maximal strongly con- 
 nected subgraph. 
 
 8 (18) 5 
 
 (b) 
 
 The condensed graph of the 
 example . 
 
 Figiire 5- Level Assignment of Any Directed Graph 
 
26 
 
 In Figure 5a, nodes 9, 10, 11 and nodes 1^^-, 15 constitute 
 maximal strongly connected subgraphs and nodes 12 and 13 are bounded by these 
 maximal strongly connected subgraphs. In the corresponding condensed graph, 
 the first maximal strongly connected subgraph is replaced by the node L and 
 the second by L . Those represented by double circles is shown in Figure 5b, 
 in which the integer next to a node represents level. Figure 5a shows the com- 
 plete ascending level assignment derived from Figure 5b. 
 
 k.3 Loop Detection 
 
 In order to assign the levels for any directed graph, it is necessary 
 to condense the graph to a link graph. The condensation can be achieved after 
 maximal strongly connected subgraphs are detected. Determination of these 
 subgraph can be made from using the reachability matrix. 
 
 ^.3.1 Determination of R matrix 
 
 Theorem 3 . The Reachability matrix is described by the following recursion 
 relationships: 
 
 R^(G) = A(G) 
 
 R^(G) = (A(G) X R^_^ (G)) U R^_^ (G) 
 
 R(G) = Rp(G) n = 2, 3, .... p. 
 
 where p is the number of nodes in a graph G. 
 
 Multiplication and inclusive or in Theorem 3 is defined by the fol- 
 lowing formula, where X and Y are matrices of order n. 
 
 X X Y = [X. .] X [y. .] = [y^^ x.^ . y^.] 
 XUY = [x,.]U[y,.] = [X,. uy ] 
 
27 
 
 Proof: The proof of Theorem 3 is divided into two parts. The first is to 
 show that the equation represents a process for obtaining the reach- 
 ability matrix. The second is that the number of repetitions, p, is a 
 sufficient condition for obtaining the reachability matrix. 
 
 Part 1. The recursion formula can also be represented by 
 
 R (G) = A U A U A^ U U A^ 
 
 P 
 
 Since A 
 
 2 
 
 [a.. ] = [Ua . a], element a . . =1 
 
 ij 
 
 _-, ik k j ■ 
 
 k=l 
 
 ij 
 
 if there is at least one path of length 2 from a. to a. i.e., 
 
 (2) 
 
 ij 
 
 if a. € r^ 
 
 ) : if a. G r a. 
 
 Therefore, A represents a matrix whose elements a. . indicate 
 whether or not there is at least one path of length n from a. to 
 
 a. depending upon whether a. . = 1 or a. . =0, respectively. 
 J -'-J -Q -"-J 
 
 Hence, the element of 7. . of R(G) = U A. is 1 if and only if 
 
 i=l 
 
 there exists at least one path of length equal to or less than p 
 
 from a . to a . . 
 1 J 
 
 Part 2. Whenever a. is reachable from a. in a given graph with p nodes, 
 
 J 
 
 there must be a path of length at most p from a. to a.. 
 
 1 J 
 
28 
 
 In other words, since there are only p nodes available, any path 
 cannot be of length greater than p, thus proving the theorem. 
 
 From the Theorem 3, the following corollary is obtained: 
 
 Corollary 1. Let k be the minim-um value of n such that 
 
 R (G) = R ^ (G) for n < p with p nodes graph. Then 
 n n-1 — 
 
 \ (G) = R(G). 
 
 ^^oof: If the length of all possible paths is less than or equal to 
 
 k in graph G, R^(G) includes all possible paths. 
 Hence A(G) X R^^ (G) = R^ (g) 
 
 \+l(G) - \ U (A(G) X R^(G)) = R^(G)U R^(G) = R^(G) = R(g) 
 
 4.3.2 Determination of Maximal Strongly Connected Subgraphs 
 
 By definition, a maximal strongly connected subgraph is a subgraph 
 with the maximal nodes which are mutually reachable. Hence the following 
 
 theorems follow: 
 
 T 
 Theorem k . If an element s. . of the elementwise product R(G) . R (G) is 1, 
 
 nodes a. and a. are members of a strongly connected subgraph. 
 J 
 
 T 
 Proof: The elementwise product of R(G) . R (G) is defined by: 
 
 S(G) = R(G) . R^(G) = [7..] • [7..] = [7.. • 7..1 
 
 -L J J -1- -L J J -L 
 
 This equation means that an element s. . of S(G) is 1, if a. is 
 
 -'-J J 
 
 reachable from a. and a. is reachable from a.. 
 11 J 
 
29 
 
 Theorem 3 . S(G ) is symmetric. 
 
 This is clear from the definition of S(G). 
 
 Theorem 6 « In the S matrix, if a diagonal element is non-zero, then the cor- 
 responding node is a member of a loop. The maximal loop, which is 
 equivalent to the set of nodes of a maximal strongly connected sub- 
 graph, can be obtained from all distinct non-zero elements in a row. 
 
 Proof: If a diagonal element s. . of the S matrix is 1, then the cor- 
 
 11 
 
 responding node is a member of a loop since there exists a path 
 from node a. to a.. The members of a maximal strongly connected 
 
 subgraph are those nodes whose corresponding elements in S(g) are 1. 
 
 th 
 If S. . =1, non-zero elements in the i row must have a path both 
 
 to and from node a., while no such path-pair exists for zero elements. 
 
 Hence, all distinct non-zero elements in a row constitute a maximal 
 
 strongly connected graph. 
 
 Example 3» Determination of a maximal strongly connected graph. 
 
 A(G) = 
 
 
 y 1 
 
 2 
 
 3 
 
 h 
 
 5 
 
 6 
 
 7 
 
 8. 
 
 1 
 
 
 
 1 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 2 
 
 
 
 
 
 1 
 
 
 
 1 
 
 
 
 
 
 
 
 3 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 1 
 
 k 
 
 
 
 1 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 5 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 1 
 
 
 
 6 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 1 
 
 7 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 1 
 
 8 
 
 ^ 
 
 
 
 
 
 
 
 
 
 
 
 
 
 0. 
 
 Figure 6. An Example of the Determination of 
 
 Maximal Strongly Connected Graphs in G 
 
30 
 
 A (g) = A(g) X A(g) = 
 
 R^Cg) = A(G) U A^(G) = 
 
 1 
 2 
 
 3 
 k 
 
 5 
 6 
 
 7 
 8 
 
 1 
 2 
 
 3 
 h 
 
 5 
 6 
 
 7 
 8 
 
 123^5678 
 00101110 
 
 00010110 
 01000100 
 00101011 
 00000111 
 00000101 
 00000011 
 00000000 
 
 123^+5678 
 01101110 
 00111110 
 01010101 
 01101111 
 00000111 
 00000111 
 00000111 
 00000000 
 
 / 
 
 a^(g) = A(G) X a(g) X a(g) = 
 
 1 
 
 2 
 
 3 
 h 
 
 5 
 6 
 7 
 8 
 
 123^5678 
 00010111 
 01000111 
 00101011 
 00010111 
 00000111 
 00000011 
 00000111 
 00000000 
 
31 
 
 R^Cg) = a3(G)UR2(G) = R^(G) = R(G) = 
 
 1 
 2 
 
 3 
 h 
 
 5 
 6 
 
 7 
 8 
 
 123^5678 
 01111111 
 01111111 
 01111111 
 01111111 
 00000111 
 00000111 
 00000111 
 00000000 
 
32 
 
 o o 
 
 Ci 
 
 EH 
 
 m 
 
 1 
 
 CO 
 
 o 
 
 o o o o 
 
 o 
 
 o 
 
 O 
 
 O 
 
 O 
 
 H 
 
 r-i 
 
 H 
 
 o 
 
 o 
 
 O 
 
 O 
 
 o 
 
 rH 
 
 rH 
 
 H 
 
 o 
 
 o 
 
 O 
 
 O 
 
 o 
 
 H 
 
 H 
 
 r-i 
 
 o 
 
 iH 
 
 r-\ 
 
 iH 
 
 H 
 
 rH 
 
 rH 
 
 r-i 
 
 o 
 
 H 
 
 H 
 
 rH 
 
 r-i 
 
 rH 
 
 r-i 
 
 r-i 
 
 o 
 
 H 
 
 rH 
 
 rH 
 
 r-i 
 
 rH 
 
 r-i 
 
 H 
 
 o 
 
 rH 
 
 rH 
 
 rH 
 
 rH 
 
 r-i 
 
 r-i 
 
 / 
 
 1 
 
 r^ 
 
 rH 
 
 rH 
 
 H 
 
 r-i 
 
 r-i 
 
 H 
 
 o 
 
 r-i 
 
 H 
 
 rH 
 
 rH 
 
 H 
 
 rH 
 
 H 
 
 o 
 
 r-i 
 
 H 
 
 H 
 
 r-i 
 
 rH 
 
 H 
 
 rH 
 
 o 
 
 r-i 
 
 rH 
 
 rH 
 
 r-\ 
 
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 o 
 
 rH 
 
 H 
 
 r-i 
 
 r-i 
 
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 rH 
 
 rH 
 
 r-i 
 
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 rH 
 
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 / 
 
 
 
 
 
 
 
 
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 CO 
 
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 rH 
 
 ,-i 
 
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 r-i 
 
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 u-\ 
 
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 J- 
 
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 r-i 
 
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 r-i 
 
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 ro 
 
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 r-i 
 
 rA 
 
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 OJ 
 
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 rH 
 
 r-i 
 
 rH 
 
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 rH O 
 \ 
 
 H 
 
 O O O O 
 
 O O 
 
 OJ en -d- Lpv vD IT— CO 
 OJ OO J- UA ^D [--CO 
 
 0) 
 
 
 -d 
 
 
 o 
 
 
 fl 
 
 
 V 
 
 
 si 
 
 
 -p 
 
 
 V) 
 
 
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 03 
 
 
 ■P 
 
 
 03 
 
 
 •H 
 
 
 W 
 
 
 c3 
 
 
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 a; 
 
 
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 <u 
 
 
 xi 
 
 
 -p 
 
 
 • • 
 
 
 
 
 w 
 
 
 ^ 
 
 t*^ 
 
 
 1 
 
 -§ 
 
 MD 
 
 03 
 
 03 
 
 -d 
 
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 ^ 
 ^ 
 fl 
 
 o 
 
 (U 
 
 +3 
 
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 Ch 
 
 >5 
 
 
 
 rH 
 
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 w 
 
 03 
 
 •P 
 03 
 •H 
 
 K 
 
 rH 
 
 
 
 S 
 
 IH 
 
 0) 
 
 
 
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 0) 
 
 -p 
 
 K) 
 
 nzi 
 
 CC 
 
 H 
 
 Xi 
 
 
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 4:5 
 
 1 
 
 w 
 
 00 
 
 <D 
 
 
 Xi 
 
 OJ 
 
 C5 
 U 
 
33 
 
 k.h Ordering 
 
 "When a loop is detected in a given graph, the logical equations of 
 the corresponding nodes (IC packages) are put in a program loop and executed 
 until the values of those nodes in the loop are all stabilized. The efficiency of 
 stabilizing the program loop of the simulation depends on the order of nodes 
 in a loop. If the graph is re-drawn so that its nodes, with the associated 
 branches, are ordered in sequence from top to bottom and if a branch whose 
 arrow points from top to bottom is called a normal branch and a branch whose 
 arrow points from bottom to top is called a reverse branch, then the following 
 property can be heuristically stated. 
 
 If nodes are ordered so that the number of reverse branches is mini- 
 mized, the number of iterations necessary to stabilize a program loop will be- 
 come minimized provided that the node in the top position has inputs from out- 
 side. 
 
 Since the evaluation of the nodes in a loop is made from top to bottom 
 in a program, only the nodes which have incoming normal branch can be defined in 
 the first iteration. Then in the following iteration, at least one node having 
 an incoming reverse branch will be defined since the nodes which have incoming 
 branches from defined nodes can produce the correct outputs. Therefore, if the 
 order of the nodes is such as to produce the minimum number of reverse branches, 
 the nimiber of iteration will be minimized. 
 
 The directed graph representation is not sufficient to calculate the 
 necessary number of iterations, but logical connections within a graph must also 
 be given. 
 
 For example, if a loop consists of four nodes as shown in Figure 7a 
 and its order is defined such as shown in Figure 7h, there are four reverse 
 
3h 
 
 branches in the order. If the logical connection of the graph is as shown in 
 Figure Tc, four iterations are necessary to stabilize the loop. That is, in 
 the first iteration, the values associated with nodes la and 2a are defined, 
 in the second, the value of 3a is defined, in the third, the value of h and 
 finally lb, 3b and 2b will be defined. 
 
 (a) 
 
 (b) 
 
 (c) 
 
 (d) 
 
 Figure 7. An Example of Node ordering and Its 
 Logical Connections 
 
35 
 
 However, if the logical connection is given as shown in Figure 7d, five itera- 
 tions are necessary, i.e., 3b is stabilized in the fifth iteration. Therefore, 
 it is not possible to determine the nianber of necessary iterations even though 
 the order of nodes and its branches are fixed. 
 
 Finding the ordering having the minimum number of reverse branches is 
 difficult in the general case unless all permutations are examined. However, 
 optimal solution for this problem can be heuristically stated as follows: 
 
 The most efficient order of nodes is along the longest path within 
 the loop which does not pass through any node twice. 
 
 Consider the previous example, in which the most efficient order is 
 that in which the nodes are ordered as shown in Figure 8a, which is along the 
 longest path. The logical connections of the example are shown in Figures 8b, 
 and 8c. In these cases only two iterations are necessary. 
 
 Figure 8. The Modified Order and Its Logical Connections. 
 
36 
 
 i^-.U.l. Determination of the Longest Paths in a Graph [6] . 
 
 A method of finding the longest path or paths in a graph can be ob- 
 tained by modifying a reachability matrix such that the matrix contains path in- 
 formation. The following definitions are necessary: 
 
 Definition 1 . 
 
 A path matrix of length n is defined as follows: 
 
 p^"\g) = [p^^h 
 
 P .. = ^sequence(s) of n+1 distinct node names starting 
 f from node i and ending at node j if there exists 
 C such path(s) of length n 
 
 
 if no such path exists 
 
 From this matrix, another matrix p^ (G) called initial 
 path matrix is deduced by removing the first node name in 
 each element from the matrix P (G) of length 1. 
 
 Definition 2. 
 
 Let A be P^"''(G) and let B be P^°'^(G). 
 
 Then product AB of multiplication over these path matrices is defined 
 
 as follows : 
 
 The operation is the same as the usual method of "line and column. " 
 Whenever p^"? of p'''^'^(G) is multiplied by p^°l of P^°'^(G), zero 
 
 * This matrix is called a Latin matrix in graph theory.. 
 
37 
 
 results in the (i,k) position of the resulting path matrix AB 
 if either or both of these element contains a zero. A zero is 
 also entered in the position if from all the products, it is 
 not possible to obtain a sequence in which no nodes are repeated 
 when a sequence of p .•/ of P (G) is placed after a sequence 
 of p . . of P (G)t If a sequence of p •■/ can be placed after 
 a sequence of p . . and one or more sequences are found in which 
 no node is repeated, the sequence (or sequences) is put into the 
 (i,k) position of the resulting matrix. 
 
 By this definition, the resulting matrix is obviously a path matrix 
 of length n+1. Hence, the path matrix of length n can be obtained by the 
 recursion formula: 
 
 P^^)(G) = P^'^-l^G) X P^°^(G) 
 
 where x denotes the above mentioned multiplication. 
 
 The method of finding the longest path(s) in a graph is then 
 described by 
 
 P^^-'l^G) = p(^^(G) XP^°^G) 
 
 n = 1,2,3. . . . 
 
 If P (G) = or n+1 - m, where m is the number of nodes of 
 a given graph, then P (g) contains the longest paths. 
 
38 
 
 Example k. The determination of the longest path(s) of Figure 9« 
 
 p(0)(G) 
 
 
 /I 
 
 2 
 
 3 
 
 h 
 
 5\ 
 
 1 
 
 
 
 
 
 3 
 
 h 
 
 
 
 2 
 
 1 
 
 
 
 3 
 
 h 
 
 
 
 3 
 
 1 
 
 
 
 
 
 
 
 5 
 
 k 
 
 
 
 2 
 
 3 
 
 
 
 5 
 
 5 
 
 
 
 
 
 
 
 k 
 
 
 
 Figure 9* An Example of 
 the Determination of the 
 Longest Paths. 
 
 P<1)(G) 
 
 
 ^1 
 
 2 
 
 3 
 
 k 
 
 5>. 
 
 1 
 
 
 
 
 
 13 
 
 Ik 
 
 
 
 2 
 
 21 
 
 
 
 23 
 
 2k 
 
 
 
 3 
 
 31 
 
 
 
 
 
 
 
 35 
 
 k 
 
 
 
 k2 
 
 43 
 
 
 
 45 
 
 5 
 
 
 
 
 
 
 
 54 
 
 
 
 / 
 
 P^^^(G) = P^^^(G) X P^°\'g) 
 
 
 1 
 
 2 
 
 3 
 
 4 
 
 5 
 
 
 y 
 
 
 
 
 135 N 
 
 1 
 
 
 
 l42 
 
 l43 
 
 
 
 145 
 
 2 
 
 231 
 
 
 
 213 
 243 
 
 2l4 
 
 ai4 
 
 235 
 245 
 
 3 
 
 
 421 
 
 
 
 
 
 354 
 
 
 
 4 
 
 Ml 
 
 
 
 423 
 
 
 
 435 
 
 5 
 
 
 
 542 
 
 5^3 
 
 
 
 
 / 
 
 P^3)(G) = p(2)(G) ^ p(0)(G) ^ 
 
 
 / 1 
 
 2 
 
 3 
 
 4 
 
 5 V 
 
 1 
 
 
 
 
 
 1423 
 
 1354 
 
 1435 
 
 2 
 
 2431 
 
 
 
 2143 
 
 231-^ 
 2354 
 
 a?^ 
 
 3 
 
 
 
 3142 
 3542 
 
 
 
 
 
 3145 
 
 4 
 
 4231 
 
 
 
 4213 
 
 
 
 4235 
 
 5 
 
 5421 
 5^31 
 
 
 
 5423 
 
 
 
 
 
39 
 
 p(^)(G) 
 
 P^3)(G) ^ p(°)(G) 
 
 1 
 
 
 
 2 
 135^2 
 
 3 
 
 
 k 
 
 
 5 
 
 1U235 
 
 
 
 
 
 
 
 2135^^ 
 
 21U35 
 231^5 
 
 35^21 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 U2135 
 
 5^231 
 
 
 
 !)U213 
 
 
 
 
 
 In this example^ nine longest paths can be obtained; they are 
 
 135^12, 1^235, 2135^, 2lif35, 231^5, 35^21, 
 1^2135, 5^231, 5^213. 
 
 Although this method is quite clear, it is not suitable for a com- 
 puter. From this idea, however, a suitable algorithm for a computer can be 
 obtained. 
 
 h.h.2. An Algorithm to Find the Longest Paths . 
 
 An algorithm suitable for a computer can be stated as follows, 
 assuming that each node is represented by a distinct integer: 
 
 Step 1. 
 Step 2. 
 
 Establish P*^°''(G) matrix. 
 
 Construct a table of paths of length 1 so that each path row 
 is in numerical order. 
 
 Step 3« Execute the following procedure for each row of the table. Examine 
 each element from the row of P (G) which corresponds to the right- 
 most integer of a path. For all non-zero elements in the P^°'^(G) 
 
1+0 
 
 matrix, compare the value of the element with each integer of the 
 path, and if the value does not agree with any of the elements of 
 the path, put it into the next colimm of the path. If another 
 path can he found, place the entire new path in the empty row of 
 the table. If, however, the matrix value already appears in the 
 path, then cross out that path. 
 
 Step k. Repeat Step 3 until all rows are crossed out or the number of 
 
 iterations becomes equal to the number of nodes in a given graph 
 minus one. 
 
 Step 5- If the termination is made by all rows crossed out, extract those 
 paths which were crossed out at the last iteration. If the ter- 
 mination is made without all rows crossed out, extract paths which 
 were not crossed out. These paths are the longest ones. 
 
 Using this algorithm, the previous example can be solved as follows 
 
 Example 5- 
 
 
 
 1 
 
 2 
 
 3 
 
 h 
 
 5 
 
 
 
 < 
 
 
 
 
 
 
 1 
 
 
 
 
 
 3 
 
 k 
 
 
 
 
 2 
 
 1 
 
 
 
 3 
 
 k 
 
 
 
 t'^U) = 
 
 3 
 
 1 
 
 
 
 
 
 
 
 5 
 
 
 k 
 
 
 
 2 
 
 3 
 
 
 
 5 
 
 
 5 
 
 
 
 
 
 
 
 k 
 
 
 
 
 PATH 
 
 TABLE 
 
 
 Paths 
 
 of 
 
 
 
 Leng 
 
 th 
 
 
 
 1 
 
 2 
 
 3 
 
 k 
 
 21 
 
 3 
 
 5 
 
 k 
 
 31 
 
 k 
 
 2 
 
 X 
 
 h2 ' 
 
 1 
 
 3 
 
 5 
 
 13 
 
 5 
 
 k 
 
 2 
 
 23 
 
 1 
 
 k 
 
 5 
 
 h3 
 
 1 
 
 X 
 
 
 Ik 
 
 2 
 
 3 
 
 5 
 
 2h 
 
 3 
 
 1 
 
 X 
 
 5^ 
 
 2 
 
 1 
 
 3 
 
 35 
 
 k 
 
 2 
 
 1 
 
 i^5 
 
 X 
 
 
 
 21 
 
 k 
 
 3 
 
 5 
 
 h2. 
 
 3 
 
 1 
 
 X 
 
 23 
 
 5 
 
 k 
 
 X 
 
 h-i 
 
 5 
 
 X 
 
 
 \h 
 
 3 
 
 5 
 
 X 
 
 \h 
 
 5 
 
 X 
 
 
 2k 
 
 5 
 
 X 
 
 
 ^k 
 
 3 
 
 1 
 
 X 
 
 31 
 
 k 
 
 5 
 
 X 
 
 2k 
 
 3 
 
 5 
 
 X 
 
 5k 
 
 2 
 
 3 
 
 1 
 
 21 
 
 k 
 
 5 
 
 X 
 
 k2 
 
 3 
 
 5 
 
 X 
 
i^l 
 
 From the table, the longest paths are: 
 
 2135^, ^2135, 135^2, 231^5, 1^235, 5^213, 35^21, 21^^35, 
 and 5^231. Those are the same as in Example h. 
 
 ^,5 Algorithm for Generating the Simulator Body 
 
 The algorithm for generating the simulator body, which consists 
 primarily of level assignment, loop detection and longest paths determination 
 is defined by the following steps. Before starting from Step 1, it is assimied 
 that the wirelist has been converted to a graph description, i.e., a branch 
 list is provided. 
 
 Step 1. Assign levels to packages in an ascending order as far as possible. 
 
 Step 2. Assign levels to packages in a descending order as far as possible. 
 
 Step 3. Extract the unassigned packages (these are bounded by loops). 
 
 Step h. Construct the adjacency matrix for the packages extracted above. 
 
 Step 5- Get the reachability matrix. 
 
 Step 6. Get S matrix and determine all maximal strongly connected subgraphs. 
 
 Step 7« Get the longest path in each maximal strongly connected subgraph and 
 get a sequence of packages so that the first package of the sequence 
 has inputs fron outside of the loop. 
 
 Step 8. Get the condensed graph, in which the packages of maximal strongly 
 connected subgraphs are represented by one pseudo -package so that 
 the modified graph has no loops. 
 
 Step 9* Assign a level to each package in the condensed graph in ascending 
 order. 
 
 Step 10. Expand the pseudo -packages to the original ones using the sequence 
 obtained in Step 7 and reassign a level to all packages in an as- 
 cending order such that 
 
 i) The level of packages which were assigned by Step 1 are 
 less than the levels of looped packages. 
 
k2 
 
 ii) The levels of loop packages are less than the level of 
 the packages which were assigned in Step 2. 
 
 Step 11 Using the sequence obtained above, generate a set of logical 
 equations for each package by the following rules: 
 
 i) Referring to the levels assigned to the packages and to the 
 connection list, generate sets of logic equations whose in- 
 dependent variables are elements corresponding to signals 
 in the connection list. 
 
 ii) For a storage package of the first level, generate only 
 equations which correspond to the output part. 
 
 iii) For a storage package of the last level, generate only 
 equations which correspond to the input part. 
 
 iv) For each loop, add program loop statements and statements 
 which test for stability by recognizing stabilized output 
 values from the equations. 
 
i^3 
 
 One example of these steps is shown in Example 6. 
 
 Example 6. 
 
 Step 1 . Ascending level 
 assignment. 
 
 level 
 
 nodes 
 
 
 
 1. 2, 3, h 
 
 1 
 
 5, 6 
 
 2 
 
 8 
 
 3 
 
 7 
 
 k 
 
 10 
 
 5 
 
 20 
 
 6 
 
 21 
 
 7 
 
 27 
 
 Step 2 . Descending level 
 assignment 
 
 level 
 
 nodes 
 
 
 
 27, 28, 29, 30 
 
 1 
 
 26 
 
 2 
 
 2l+, 25 
 
 3 
 
 21, 22, 23 
 
 k 
 
 20 
 
 Figure 10. An Example of a Graph for the 
 Simulator Body Generator. 
 
kk 
 
 step 3- Extracted nodes are shown in Figure 11. 
 
 A(G) 
 
 Step k . Adjacency Matrix A(G) 
 
 9 11 12 13 1^ 15 16 17 18 19 
 
 9 
 
 
 
 
 
 1 
 
 1 
 
 
 
 
 
 
 
 
 
 
 
 
 
 11 
 
 
 
 1 
 
 1 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 
 
 12 
 
 1 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 
 
 13 
 
 1 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 11+ 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 15 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 16 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 1 
 
 
 
 17 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 1 
 
 1 
 
 18 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 1 
 
 
 
 
 
 19 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 / 
 
 Figure 11. 
 
 Extracted Graph 
 Bounded by Loops 
 
 Step 5 . Reachability Matrix R(G) 
 
 R(G) = R^(G) = Rg(G) 
 
 9 
 11 
 12 
 13 
 14 
 
 15 
 16 
 
 17 
 18 
 
 19 
 
 9 11 12 13 Ik 15 16 17 18 19 
 
 1 
 
 
 
 1 
 
 1 
 
 1 
 
 1 
 
 1 
 
 1 
 
 1 
 
 1 
 
 1 
 
 1 
 
 1 
 
 1 
 
 1 
 
 1 
 
 1 
 
 1 
 
 1 
 
 
 
 1 
 
 1 
 
 1 
 
 1 
 
 1 
 
 1 
 
 1 
 
 1 
 
 
 
 1 
 
 1 
 
 1 
 
 1 
 
 1 
 
 1 
 
 1 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 1 
 
 1 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 1 
 
 1 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 1 
 
 1 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 1 
 
 1 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 1 
 
 1 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 1 
 
 1 
 
h^ 
 
 step 6. 
 
 S(G) = R(G) X R (G) = 
 
 9 
 11 
 12 
 
 13 
 Ik 
 
 15 
 16 
 
 1? 
 18 
 
 19 
 
 9 11 12 13 lU 15 16 17 18 19 
 
 1011000000 
 0100000000 
 1011000000 
 1011000000 
 0000000000 
 0000000000 
 0000001111 
 0000001111 
 0000001111 
 0000001111 
 
 / 
 
 By S(G), the graph has three loops: 
 
 loop 1 - (9, 12, 13} 
 
 loop 2 = {11} 
 
 loop 3 = {16, 17, 18, 19} 
 
 Step 7. 
 
 
 
 
 
 
 
 a) The longest path for loop 
 
 1. 
 
 
 
 
 
 9 
 
 12 
 12 
 
 13 
 13" 
 
 1 
 
 2 
 
 
 f^°\g) = 9 
 
 
 
 9,12 
 
 X 
 
 The longest 
 
 12 
 
 9 
 
 
 
 
 
 9,13 
 
 X 
 
 paths are 
 
 13 
 
 9 
 
 
 
 
 
 12,9 
 
 13,9 
 
 13 
 
 12 
 
 12, 9, 13 and 
 
 13, 9, 12. 
 
 b) The longest path for loop 2. 
 
 Since the loop is formed from only one node, there is no path. 
 
k6 
 
 c) The longest path for loop 3. 
 
 16 17 18 19 
 
 P^^^G) = 
 
 16 
 
 
 
 17 
 
 18 
 
 
 
 
 17 
 
 16 
 
 
 
 18 
 
 19 
 
 
 18 
 
 16 
 
 17 
 
 
 
 
 
 
 19 
 
 16 
 
 
 
 18 
 
 
 
 The longest paths are: 
 
 16, 18, 17, 19; 17, 19, 16, 18 
 
 18, 16, 17, 19; 19. 16, 17, 18 
 
 19, 18, 16, 17; 16, 17, 19, 18 
 
 17, 19, 18, 16; 18, 17, 19, 16 
 19, 16, 18, 17; 19, 18, 17, 16 
 
 1 
 
 2 
 
 3 
 
 16,17 
 
 18 
 
 X 
 
 16,18 
 
 17 
 
 19 
 
 17,16 
 
 18 
 
 X 
 
 17,18 
 
 16 
 
 X 
 
 17,19 
 
 16 
 
 18 
 
 18,16 
 
 17 
 
 19 
 
 18,17 
 
 16 
 
 X 
 
 19,16 
 
 17 
 
 18 
 
 19,18 
 
 16 
 
 17 
 
 16,17 
 
 19 
 
 18 
 
 17,19 
 
 18 
 
 16 
 
 18,17 
 
 19 
 
 16 
 
 19,16 
 
 18 
 
 17 
 
 19,18 
 
 17 
 
 16 
 
 The sequence of the nodes for loop 1 is thus 12, 9, I3. 
 
 The sequence of the nodes for loop 3 is I6, I8, I7, I9 (or I6, I7, I9, I8) 
 
 Step 8 . 
 
 The condensed graph is shown in Figure 12. 
 
 Step 9 . Ascending level assignment 
 Level = (LI) 
 Level 1 = {L2} 
 Level 2 = {1^,15} 
 Level 3 = {L3} 
 
 Figure 12. Condensed Graph 
 of the Example. 
 
hi 
 
 step 10 . 
 
 The total level assignment and the order of nodes within a 
 level can "be obtained as follows: 
 
 We assume that the nodes assigned by the ascending ordering 
 are leveled starting from level 0. The nodes bounded by 
 loops start from level 50, and the nodes from the last level 
 are assigned to level 100. 
 
 level 
 
 1, 2, 
 
 3, h 
 
 
 1 
 
 5, 6 
 
 
 
 2 
 
 8 
 
 
 
 3 
 
 7 
 
 
 
 k 
 
 10 
 
 
 
 5 
 
 20 
 
 
 
 6 
 
 21 
 
 
 
 7 
 
 27 
 
 
 
 50 
 
 11 
 
 
 
 51 
 
 12, 9, 
 
 13 
 
 
 52 
 
 Ih, 15, 
 
 
 
 53 
 
 16, 18, 
 
 17, 19 
 
 
 96 
 
 20 
 
 
 
 97 
 
 21, 22, 
 
 23 
 
 
 98 
 
 2k, 25 
 
 
 
 99 
 
 26 
 
 
 
 100 
 
 27, 28, 
 
 29, 30 
 
 
 Step 11. 
 
 The logical equations will be generated in the above order. 
 Program loops and test statements will be inserted in levels 50, 
 51 and 53. For the actual logic equations, see Appendix Gl. 
 
k8 
 
 5. SIMUIATION CONTROL LANGUAGE (TESLA) 
 
 lESLA - TEst Simulator LAnguage - is a fairly general logic simula- 
 tion input, output and control language. Language statements consist of two 
 categories: declarations, and test step commands. Statements are written in 
 free-field fonnat separated by semicolons. This section presents a short de- 
 scription of the language and a sample program to provide an introduction of the 
 language. The complete syntax and semantics of this language are described in 
 [2]. 
 
 5.1 Declaration 
 
 5.1.1 Program 
 
 A TESLA program starts with the word BEGIN. The first declaration 
 must be a case limit declaration, which specifies the range of test cases. 
 The other declarations may be freely written in a program, provided that all 
 quantities are declared before they are used. Redeclarations are permissible. 
 
 A step label followed by a series of statements assigns values to 
 signals and controls the simulation in one clock interval. 
 
 A program must end with the word END. 
 
 5.1.2 Declarations 
 
 a) Case limit declaration 
 
 CASK [n:m] - this specifies the number of test cases to be executed 
 in parallel, m and n are integers and < m - n < 46. 
 
k3 
 
 b) Group declarations 
 
 SIGNAL GROUP - used to associate an identifier with a group of 
 signals. Any signal name may "be used in the list. 
 STORAGE GROUP - used to associate an identifier with a group of 
 storage signals. In this case, the next state of storage element 
 is assigned to the signal. 
 A mult i -signal identifier, which is written by using *'s as "don't cares" 
 in place of characters, specifies a group of signals whose names match the 
 non-asterisked portions of the multi-signal identifier. 
 Group declarations may be nested to any depth. 
 
 c) Data declarations 
 
 DATA - associates bit patterns with an identifier. Bit patterns 
 may be expressed either in octal or binary form. If bit patterns 
 are case dependent, case dependent digits (A ~ Z) may be used in 
 the bit pattern, provided they have been declared. 
 
 d) Digit Declaration 
 
 DIGIT - associates digit patterns with an identifier which must 
 be single letter of the alphabet. The digit is called a case 
 dependent digit. This declaration is used to declare digits whose 
 value varies with the test case. The first digit of the digit .list 
 is associated with the lower limit of the simulation cases declara- 
 tion, the next digit is associated with the next case, etc. This 
 case dependent digit may be declared in octal or binary fonii. 
 
50 
 
 5.2 Control Statement 
 
 There are three categories: input control statements, storage con- 
 trol statements and output control statements. A step label followed by any 
 control statement and/or declarations specifies values of signals and control 
 of the simulator and its output. 
 
 5.2.1 Input Control Statements 
 
 Three simulation input control commands may be used. These commands 
 
 may adjust input variables of specified test cases among those being generated 
 
 in parallel by specifying case limit. 
 
 INSET - causes each of the input variables associated with the 
 list of input signals following the command to be set 
 to a logical "one". 
 
 INCLR - causes each of the input variables associated with the 
 list of input signals following the command to be set 
 to a logical "zero". 
 
 INPUT - causes the input variables associated with the list of 
 input signals to be modified by a specified data 
 pattern. 
 
 INOUT - permits input signal values to be set to the values of 
 the values of signals calculated during the previous 
 test step. 
 
 The identifier ALL and the (default) empty word both cause the 
 
 specified action to be applied to all input variables. 
 
 5.2.2 Storage Element Control Statements 
 
 Three commands can be used to control simulated storage elements. 
 Case limits can be used to restrict storage element control statements to 
 apply to speicified test cases. 
 
51 
 
 FFX - causes the storage elements to be set their next states 
 in accordance with values calculated during the previous 
 test step. This corresponds to the actual operation of 
 the physical storage element. Therefore, unless other- 
 wise specified by an explicit storage element control 
 statement, the transfer (FFX) condition is assumed to 
 apply to all storage elements. 
 
 FFIN - similar to the INPUT command. It causes sets of storage 
 elements to assume the states given by an associated 
 bit pattern. This bit pattern is used instead of the 
 normal next storage element states. 
 
 FFOLD - this inhibits the transfer of calculated next storage 
 element states into the present states and causes the 
 storage element states to remain unchanged from those 
 held during the previous test step. 
 
 It is assumed that at the start of simulation_, all storage elements 
 
 will be initially cleared to logical zero. 
 
 5.2.3 Output Control Statements 
 
 These statements are used to print the simulation results with 
 various formats. These commands may include case limits to selectively print- 
 out the results of only some of the many test case results which have been 
 generated in parallel. 
 
 PRINT2 or PRINTS - causes printing of the simulation output 
 
 in binary or octal form for the list of output signals 
 and/or storage elements following the command. 
 
 PRAC2 or PRAC8 (PRint And Compare) - causes the printing (in 
 binary of octal) of ' not only the simulation output 
 for each member of the list following the command, 
 "but also an expected output pattern which has been 
 associated with each of these lists. If differences 
 exist between this expected output and the actual out- 
 put, a marker is printed which directs the observer's 
 attention to the location of the differences. 
 
 PRID2 or PRID8 (PRint If Different) - has the same statement 
 format as PRAC and causes the same type of output but 
 only if there are differences between the actual and 
 expected outputs. If the simulation output is as 
 expected, no printout occurs. 
 
52 
 
 5.3 A Sample Program 
 
 An example of a TESLA program is given in Figure 13 which simulates 
 the logic of one of Control Unit boards. The following descriptions will hope- 
 fully clear up some of the confusion of the previous sections. 
 
 line 
 
 2 The first declaration must be the number of test 
 cases which are generated in parallel. 
 
 3-6 The group identifier TOM is associated with sixteen 
 input connector signal names which are written with- 
 in a pair of parenthesis. 
 
 7-8 These group declarations associate multi-signal 
 
 identifiers with TGM, ABT, AGT, and AGO respectively. 
 The group identifier TOM could also have been de- 
 clared using a multi-signal identifier as follows: 
 
 SIGNAL GROUP T0M(T0M-**--G1) ; 
 
 9 This declaration is for storage element group FF. 
 
 IO-I3 These are the same as in line 3-8 except they 
 
 associate output connector signal names with the 
 identifiers which are used for print statements. 
 
 1^-17 These digit declarations associate the given letters 
 with the case dependent digit patterns. The letter 
 D, for example, is associated with a case dependent 
 digit whose value is zero in the odd ninnbered test 
 cases and one in the even numbered ones. 
 
 18 PAT 1 is a sixteen-bit pattern. The first four pins 
 are set to different values for the different par- 
 allel test cases according to the digit declaration A. 
 The second four pins are set according to the digit 
 declaration B, the third four to C and the last four 
 to D. For example, the first pin is set to zero for 
 test cases 1 through 8 and one for test cases 9 through 
 16. 
 
 19-20 PAT2 and PAT3 are eighteen bit patterns and declared 
 using octal notation. 
 
 21-22 PAT4 and PAT5 are declared using binary notation. 
 
53 
 
 23 The first test step of this simulation is called STEPl. 
 The values of the group of storage elements identified 
 with FF are all set to zero for test cases 1 through k^ 
 all ones for test cases 5 through 8 and first eight 
 signal values are set to ones and second eight signal 
 values are set to zeroes for test cases 9 through 12 
 according to PAT3 and so on. 
 
 2k Since there are no case limits, for all cases the sig- 
 nals CLK CO is set to one and CLK CI is set to 
 
 zero. 
 
 25 The first statement prints the values of the members 
 of FF in binary form and the second statement prints 
 the values of all output connector signals. 
 
 28 The members of TOM and T(M are set according to the 
 pattern PATl. 
 
 29 The values of the members of TRO, COMP, TGC and FF are 
 printed in binary form. 
 
 35 "NOT PATl" means the Boolean complement of the values 
 of PATl. Therefore, the members of ACT are set to the 
 inverses of the values of PATl. 
 
 36 The third statement is a print-if-different in binary 
 form. If the expected values of FF for all cases are 
 one, no printout occurs. However, if there is difference, 
 the expected and actual values and the points of differ- 
 ence are printed out. 
 
 37 The first statement prints all output connector signal 
 values. This is equivalent to PRINT2 ALL. The second 
 is a print -and-compare in binary form. The values of 
 the members of COMP for test case sixteen are compared 
 with ones and the expected (in this case all ones) and 
 actual values and the points of difference (which are 
 indicated by X's under the differences) are printed 
 out. 
 
 ^1 By this statement STEPIO is repeated twice. 
 
 k'J END. terminates the program. 
 
5i+ 
 
 IILIAC IV TPAMSLATO* WRITING SYSTEM 
 Tf^LA CnrPlLFR - VFRSinN 1 DECFMBTP 2?> 1969 AT Ol ?l'»«,9 
 
 PPPGPAM OTOritND/TFSLA 
 
 PEGI^ 1 
 
 CASE sr 1 I1^]^ 2 
 
 SIGNAL r^'fc'^ T( > ( Tri'-1 ?--(;i .THK'-l 3--f.l ,TnM-M"-r.1 »Tn^-i 5--G1 » 3 
 
 Tn"-?p--r, i»TnM-?9--r. i,TPM-3o--Gi»TnM-3i--Gi» « 
 
 •rr( -4i-.f>, ^,jnM-as--r-i#Trn-'tf--Gi.TnM-a7--ni, 5 
 
 Tf'-ftc--r-i*Tnk'-^i--M»Trw-t.?--f, i,Tn»'-(<,3--Gn. 6 
 
 Tf ( TCI -**--Gr ), A«Tf APT-**--r.Ol# 7 
 
 Ar T(A(-T-«*--GO), AGn(/lf.r-**--GO)i 6 
 
 STPPAGF rfTliP r h ( TPf'-**--! O » 9 
 
 Sir.MAL f PPi-P IPC ( TP('-**--l 0) » 10 
 
 ri't P(T-r( Mr**pf»TC'^f'PCH>'-7»TfnN'PrHK-p,T-rnMPn-Gn» 1 1 
 
 Trc (Tf.(-?f--r-l>Tr,r-?9--ri»Tr.r-30--r, i,TGr-3l--Gl» 12 
 
 7rf-/,/j--f, J ,T'-,r-/j5--ri»Tfr-'»6--f, 1 .Tr.r-a7--Gn) 13 
 
 f'TGTT fir?f pprrrxM ni ". 11 m n» 1** 
 
 f-z?( r^'rv^ 1 1 1 n(( ui i 1 M • 15 
 
 r = ? ( f^ 1 J P L n ( 1 1 r (i 1 n » 1 fc 
 
 psPfpinrioioKMrion: 17 
 
 rAlAt-ATlsPfAAAiJtPPffCrCT'Pr"*, 18 
 
 F/sT;- = pf roor(ipi, 19 
 
 HAT3ePf 777777)/ 20 
 
 ^'AT«r?f1lnn11(.;ufo^n^^^, 2i 
 
 F A T b = ? C '' C P H! P P ' 1 11 1 1 1 1 n J 22 
 
 STFPIJ FFl^ FT fitit] PAT?,r^|Pi PAT3#r<;«1?] PATit, r 131 1 •*] FATbl 23 
 
 U«FT riK-----(;p) I ► P | fi flK-----ci; 24 
 
 HPI^ TP r F : ( py* T? al i : 25 
 
 Figure 13 • An Example of TESLA Program 
 
55 
 
 STFP?! USrr T-TPOE -Kr,j ,T-TPnf^i-Kr,l ,T-rLIN--Rl »rLK-----ri,T-TRn«-i'Gl» 26 
 
 T-Cr»>f^C-r,i HNTl P rLK-----rO) 27 
 
 IMPUT TTM KAT1»T0K' PATlJ 28 
 
 PRINT? TKr*CnMF,Tr,r»FF; 29 
 
 STFPfll USFT TGITFOFN-U 30 
 
 INPUT AtiT fATi; Uri P TPMJ 31 
 
 HPUT? Tf,r,CfHP.Tf.C»FF » 32 
 
 STTP^i UFUT *f'T MTi: UClP A ■" y ! 33 
 
 PRitT? TPr.( nMf,Tr,C 'FF > 3ft 
 
 ^TFP*i UFUT flr.T ^r,T PtTi: pf.TM? rf , rOMP; 35 
 
 STFP7: U'MiT API ^l.T Poll; T'Tir ahtj PRI^? f^ 2 f 11 M 11 1 1 11 1 U 1 1 M J 36 
 
 PPT NT?? yftC? ff-Mp ri^8161 9(1111111111111111111)1 37 
 
 «TrPff UFUT Tf,M h|!T P/M1; ^^^lR ART! 38 
 
 PPTM? rPfP; PkaC? rrr^'^^ [ISslSl ?M 1 1 H 1 1 1 1 1 11 OOOr 1 rO ) t 39 
 
 PP/>(? rpMr (16:1^1 ? r 11 1 11 n 1 OOfO 1 1 1 1 oto ) } 40 
 
 prpfAl :? 41 
 
 STFPin iNFt'T Af^f' t- ATI : 42 
 
 U «F T Ar[}TRPr -! ; 43 
 
 PPU7? rfi».'f .FF .TPC^Tcf ; 44 
 
 STFPl 1 I UF UT ACL ' ( T ";T1 : 45 
 
 PPTN'T? rrrf ,rf * I^<r , Tf,r : 4b 
 
 FNn. 47 
 
 cnMppATi I A r TFN^, Mf c,nrprF ppprpM- erpfpc i.r(,F rrTFriFD TN Pass 1 
 TMF TrTn TTk/F I At; r ►tmutf? 1 «> . tt SFf"nNnS. 
 
 TI^F row TMTIAi 17^11^ ; r mtmitF« 3,? SFrpK'nS, 
 
 TTfF rnr t;t«^^I^(;. f.'TMHTF.t ?.fl ^FCPNnS. 
 
 TT^-F rPt- ^AK,«;T^^: f MTMiTF*^ 5.3 SFCPNrS. 
 
 nvt rnc crf.A^Tir ArTTrnss r mtmitf^ a.? SFcpNnS. 
 
 Tl>-F rfu ThhPP (.FcP^FPV, p MyriiTF^ 0.0 fiFcrNnS. 
 
 TT>F fPF rr.i'r, ^PT-.TUG. p MMiTF? 0.0 SFCOMpS. 
 
 /i7 rAPfc KTAf' AT lf3 fAH'\S PFR MTMiTF, 
 
 Figure 13 . An Example of TESLA Program - Cont. 
 
56 
 
 6. SIMULATOR CONTROLLER 
 
 The function of the simulation controller is to translate TESLA. object 
 code and to pass input and storage element values to the simulator body, to con- 
 trol the simulation execution, such as program termination and to place the out- 
 puts on an output file without editing for the purpose of obtaining fast simu- 
 lation. 
 
 In order to obtain high speed and efficient execution of the simula- 
 tor, TESLA source statements are decomposed into several simple commands so that 
 any tasks which can be performed within the compiler are performed there, rather 
 than in the controller. 
 
 The controller accepts four input commands, three storage element com- 
 mands and two miscellaneous commands. Obviously output commands do not affect 
 the controller, so another file having only output commands is generated by the 
 compiler. This is not used for the controller but rather by the separate re- 
 sults display program. 
 
 The basic function of input commands is to set the specified array 
 elements to be set to a logical one, logical zero or to specified patterns. 
 These input patterns are masked by bits which are generated from the case limits 
 at the beginning of each one-clock simulation. 
 
 Storage element commands cause the storage elements to assume their 
 normal next state, to retain their present states, or to set the states given 
 by associated bit patterns. 
 
 Miscellaneous commands consist of End of Input and End of TESLA 
 Program. The End of Input is used at the end of each test step to initiate 
 simulation, i.e., whenever the controller recognizes the End of Input command. 
 
57 
 
 it jumps to the simulator body to execute one clock time of the simulation. 
 The simulated data is placed on an output file for printing. The End of TESIA 
 Program command is used to indicate the end of the simulation. When controller 
 recognizes this, it stops the execution and terminates the program in an orderly 
 manner. A typical format of TESLA's object comman is shown in Figure l4, in 
 which INI means the command name, n is the ni;imber of pairs of words where SYMBi 
 presents input interface and signal array subscript and Datai presents the data 
 which is put to the subscript. The detailed description of those commands is 
 also described in [2]. 
 
 26 3^ ^7 
 
 Data 1 
 
 '/, 
 
 71 SYMB 2 
 
 Data 2 
 
 y///////////A^-^ i 
 
 Data 3 
 
 Figure \h. 
 A Sample Format of TESLA Object Command 
 
58 
 
 7 . IMPLEMENTATION 
 
 The set of programs for this system is divided into three major 
 groups: the TESLA compiler, the simulator generator group and the results 
 display program. The whole program sequence is shown in Figure 15. 
 
 7.1 TESLA Compiler 
 
 In order to compile a TESLA program, two programs must be executed; 
 TESLA/MERGE and TESLA/DISK. 
 
 a) TESLA/MERGE reads a list of all signal names and their associated array 
 
 subscripts which has been generated by the simulator generator 
 programs and fonns a table of signal names and array subscripts 
 including storage element subscripts. 
 
 b) TESLA/DISK is the compiler itself. Referring to the output of TESLA/ 
 
 MERGE, each signal name in a source program is verified and if all 
 signals in the program are valid, the source code is compiled and 
 two object files are created; one contains the simulator control 
 code which specifies all control information and signal values 
 used in the simulator and the other contains the print control 
 object code which specifies the format of printout of the results 
 display program. 
 
 7'2 Simulator Generator Group 
 
 This group of programs consists of seven subprograms and generates 
 a simulator for each CU or PE printed circuit board automatically. Each sub- 
 program has the facility to call the next program without manual intervention 
 
59 
 
 so that all of these programs are executed automatically in correct order. 
 Each subprogram also generates a history file for tracing the history of the 
 simulator. The ordering program is not currently incorporated in this group 
 because the number of looped packages in the printed circuit boards is small 
 enough to not affect the execution time of the simulation. Each subprogram 
 of this group has the following functions: 
 
 a) CUBD/UPDATE accepts an original netlist file and, if necessary, the net- 
 
 list is updated with correction cards. A reformatted, updated net- 
 list is produced. A sample of update listing is shown in Appendix 
 A. On the left hand side of the listing, four records are shown 
 as inserted and on the right, four records are deleted. 
 
 b) CUBD/WEDTRI - the main job of this program is a signal name sort and 
 
 assignment of an array element to each signal name. This program 
 also checks for simple wirelist errors, such as signals having no 
 source or having no destination, or having more than eight fan-outs. 
 A part of this signal sort listing is shown in Appendix B. The 
 Symbol names in the listing correspond to the array subscripts 
 which are used in the simulator. The A array contains all input 
 interface signals, B contains the output interface signals and 
 C and D are for internal signals. Each array has up to 512 elements. 
 
 c) CIJBD/WEDTR2 accepts the signal sorted file and sorts by package location 
 
 and pin. In the process of sorting, an arc-list which describes the 
 directed graph of the board is also generated. In this program, 
 storage elements and connectors are divided into two nodes and each 
 package location is converted to a unique niuneric value for effi- 
 cient execution of the level assignment. Appendix C-1 shows a 
 
60 
 
 part of the listing of a package and pin sort. In it, the four 
 characters at the extreme left show a package location, with the 
 associated package type in parentheses. The three n-umeric charac- 
 ters to the right of each signal name show the pin to which that 
 signal is connected. A source package and pin is shown in parenthe- 
 ses if a pin of the package is a load, otherwise blanks are put in 
 this position. Appendix C-2 shows the arc-list corresponding to 
 Appendix C-1. Appendix C-3 shows numeric value for each package 
 location and its package type. Note that each flip-flop (type DILOO8) 
 has been split in two. 
 
 d) CUBD/LKVELER - the arc-list is converted to a source-destination list 
 
 as shown in Appendix D-1. In this, the integer in parentheses 
 right to the package location is the symbolic name of a package 
 and integers in the source or destination row correspond to other 
 package locations. Using this list, the level assignment procedure 
 assigns a level to each package in ascending and descending order 
 until no more packages can be assigned. The output listing of 
 this procedure is shown in Appendix D-2. The flag bit is set if 
 a package has been assigned a level. Therefore, if both the FWD 
 and BKWD flag bits are zero, the corresponding package is a member 
 of a loop or bounded by loops. In this example, A0l4, AOI5, etc. 
 as unassigned. 
 
 e) CUBD/REDUCE - the first part of this program prints a listing of assigned 
 
 packages and unassigned packages and generates the arc-list of only 
 the unassigned packages as shown in Appendix E-1. A loop detection 
 procedure separates each loop and converts each loop to one pseudo 
 package. Finally, a source-destination list using pseudo packages 
 
61 
 
 is produced. In Appendix E-2, the meiribers of each loop are listed. 
 For example, a loop called CHNOl consists of AOlU and A015. In this 
 example, there are six loops and one non -looped package (AI39) which 
 is bounded by loops. Using these pseudo packages (CHNOl through 
 CHN06 and A139)^ "the source -destination list is printed. 
 
 f) CUBD/HSKEEP - using the previous source-destination file, an ascending 
 
 level assignment is done by the same procedure as in CUBD/LEVELER. 
 This is shown in Appendix F-1. Finally, all packages are reassigned 
 so that the levels of the looped packages starts from level fifty 
 and the last level becomes one hundred, as shown in Appendix F-2. 
 
 g) CUBD/SIMGEN - referring to the levels just assigned to the packages and 
 
 to the package-pin sorted netlist generated by CUBD/WEDTR2, this pro- 
 gram generates sets of logic equations whose variables are array 
 elements corresponding to signals in the netlist. For looped pack- 
 ages, a iterative statement and test statement for the stabilization 
 are inserted so that if the outputs of the packages have not stabil- 
 ized after thirty repetitions, a message is printed out to indicate 
 a. possible race condition. Because of the nature of the B-5500 
 ALGOL compiler, some redundant words such as BEGIN, DEFIKE, and 
 END are inserted to force program segmentation since no more than 
 1022 words of object code may be in any segment. In addition to 
 generating the simulator body, this program creates a small para- 
 meter file which contains the mmiber of input, output, internal 
 and storage signals and the name of a board to be simulated, etc. 
 Also, all signal names are printed, partitioned into their respective 
 input, output, and internal arrays signal as shown in Appendix G-2. 
 
62 
 
 In Appendix G-1, a part of simulator 130(3^ is shovm. In this, 
 VTRUE stands for logical one, FALSE for logical zero and OEMPIY 
 for any empty output pin. For looped packages (for example, 
 level 53^ -^137)^ a WHILE statement is used for the iteration. The 
 Y array stores the current values of outputs and Z array stores 
 the previous output values. After the evaluation of each set of 
 logic equations, the elements of the Y and Z arrays are compared. 
 If the comparison disagrees, STABLE will be set to false and the 
 evaluation will be repeated, 
 h) CUBD/MERGE - reads the parameter and simulator body file and the head 
 and tail (which were written manually) and combines them into a 
 complete simulator program. The head and tail program is common 
 to all boards. 
 
 7- 3 Simulator 
 
 <BOARD NAME>/SIMULA is generated by the above simulator generator 
 group. The simulator accepts the simulation input file which is created by 
 the TESLA compiler and generates a file which contains necessary information 
 for the results display, including the simulator history. During a simulation, 
 if there are no errors, only step numbers and the time used is printed 
 (Appendix H). The print-out of the simulation results is done by the Results 
 Display program. 
 
 7* ^ Result Display Program 
 
 CUBD/PRINTER reads a print control file generated by TESLA compiler 
 and makes a listing of each test case in the requested format. A sample list- 
 ing is shown in Appendix I. 
 
63 
 
 Q« 30ARO>/OUPDT «» (11 
 
 (1) 
 
 CUBD/WEDTRl 
 
 Q <B0ARD>/1SSRT«« (21 
 Q <B0AR0>/1IARY«« (6| 
 Q <B0ARD>/10ARYiJ i (6| 
 Q <BOARD>/ ITARYh (6) 
 Q <BOARD>/ ISGNLo (8) 
 
 (2) 
 
 CUB0/WE0TR2 
 
 Q <B0ARD>/2PSRT.i (6| 
 Q <B0ARD>/2PSYBi. (3] 
 Q <B0ARDV2PARCiui (3) 
 
 (3) 
 
 CUBD/LEVELER 
 
 Q <BOAR0>/3SARC«« (4) 
 Q <B0ARD>/3FLVL»» (4) 
 
 (4) 
 
 CUBO/ REDUCE 
 
 Q <B0ARD>/4MLVm (5) 
 Q <B0ARD>/4CHIN «i (5) 
 Q <B0ARDy4LARC«i (5) 
 
 (5) 
 
 CUBO/HSKEEP 
 
 1. <BOARD> MEANS BOARD NAME tg. TOFUNA 
 
 2. >i MEANS RUN NUMBER 
 
 3. INTEGER TO THE LEFT OF THE PROGRAM NAME GIVES THE PROGAM NUMBER 
 
 4. INTEGER TO THE RIGHT OF A FILE NAME GIVES THE PROGRAM NUMBER WHICH 
 
 USES THE FILE. 
 
 (61 
 
 CUBO/SIMGEN 
 
 Q< B0ARD>/6 PARAxi (7| 
 0< B0ARD>/6 BODYk i (71 
 Q< BOAR0>/6 STOS« « (8) 
 
 (71 
 
 CUB0/MER6E 
 
 Q< B0ARD>/1 SGNLn (8) 
 0<B0ARD>/6ST0S«« (8 1 
 
 TESLA/MERGE 
 
 Q< a0ARD>/ SYMBOL (9) 
 
 TESLA COMPILER 
 
 TESLA/SINPUT (101 
 TESLA/PRINTC (111 
 
 SIMULATOR 
 
 Q<B0ARD>/0UTPT«» (II) 
 
 (111 
 
 CUBO/PRINTEfl 
 
 SIMULATOR 
 RESULTS 
 
 Q <60ARDV5TLVL«i (6) 
 
 Figure I5. Program System of Simulator. 
 
8. CONCLUSION 
 
 The description of this paper focused on what was originally to 
 have been the ILLIAC IV Control Unit printed circuit board simulator system. 
 This system is quite general, however, and was quickly and easily modified 
 to also produce Processing Element printed circuit board simulators and the 
 fault test pattern generation system for both CU and PE printed circuit boards. 
 Both CU section simulators and PE simulators are being developed based on most 
 of those programs described here. This simulator system is extensively used 
 for test pattern generation, in which the simulator body generator (CUBD/SIMGEN) 
 is modified so that it can generate sets of failure inserted logical equations, 
 as well as correct logical equations. The detailed method of test pattern 
 generation is described in [9]- 
 
 The differences between PE printed circuit boards and CU printed 
 circuit boards are as follows: 
 
 PE CU 
 
 Number of IC packages (max) 20 I65 
 
 Number of interface pins (max) 100 500 
 
 Logical value representation Positive voltage Negative voltage 
 
 = Logic "1" = Logic "1" 
 
 From a programmatic point of view, the CU board simulator system can treat PE 
 boards since the size of a PE board is much smaller than that of a CU board. 
 However, because the logical value representations are different (even though 
 the same IC's are used), there are two different simulator body generators. 
 In the case of PE generator, AND and OR elements in the CU representation are 
 changed to OR and AND elements and logical zeroes and ones in CU representation 
 
65 
 
 are changed to logical ones and zeroes. The PE board simulator body generator 
 is called CUBD/PESIM and has been operational for almost a year. 
 
 The simulator has been used for two purposes; first, for understanding 
 and debugging the logic of boards and second, for verifying manually prepared 
 test patterns written in TESLA for the boards. Both of these uses have been 
 applied to CU boards, particularly the latter since it is sometimes difficult 
 to find test patterns within a reasonable time for some types of logic using 
 the test pattern generation system. The FE board simulator system has not been 
 used extensively for the first purpose since the logic of the PE boards is so 
 simple that there is no difficulty in understanding and to debugging them. It 
 has, however, proven quite useful for correct simple, but basic errors in 
 manually written netlists by simply looking at the error listings which are 
 produced while generating the simulator. The PE board test generation system 
 has been very successively used to quickly produce diagnostics for all 35 PE 
 board types. 
 
 Although the CU board simulator has been used for debugging, more 
 extensive use of a simulator will be made when a section simulator is con- 
 structed. 
 
 Execution time for the generation of a typical CU board simulator 
 is less than ten minutes; for a typical PE board simulator, it is less than 
 five minutes. The execution time for a typical CU board simulator itself is 
 about fifty miliseconds per clock per set of up to h'J test patterns. 
 
 It has also been proven that this method of generating simulators 
 is quite general, since almost all of the programs can be used for various 
 simulators, such as, PE and CU boards, CU sections, and the whole PE, and 
 test pattern generation for each of them. 
 
66 
 
 APPENDIX A 
 
 A SAMPLE UPDATE LISTING OF CUBD/UPDATE 
 
 IIIIIC IV B0« D lg« E.T FUNL llf Lt TEI). TAH It-UK 
 
 TlCLKOnrND BUFf 008 CLtiCKS S TOrUKt- "tMUP 
 
 IKLKOirNO iliFF 007 CLOCKS S TOFIINC DFLFTfD 
 
 TICLkOiFND *n7» 013 nILOZZ I TOFUND OfLUfD 
 
 Trie H «0B? no? 1,11013 S TliriiNP ^^SFRTE'^ 
 
 1-C.IN---H PtFt nU ClKfliF L TCFpNO I^SFRTEn 
 
 lULtOCFSU PUFF ('06 CLkHIiF S Tl'fliNn I^SFHTfP 
 
 lUll-OlFM; NLiff 007 ClKbUf S InFimri iKSFRTf" 
 
 rmriuai MiMHfR nF PFrnpps" 972 
 
 MiMiFP ii( ntcnonn u THE iiPn»Tfr file* »7? 
 
 M.^i fu iiF I^S£B^ c»POs • ? 
 
 M'MlfP rr PFLETF f«PUS« 1 
 MiMIFP OF fH«Nr,F CApDS" 2 
 
 TIME liStn It t'BT»IN THIS PF SUl T 1 
 
 H-lifFSSlh TH'Fl MM'TFS ?9 SFCP'TS. 
 
 1/(1 TIMFI I U'UTtS 79 SFCONPS, 
 
 \^ 1 3?3 I IM TIS ?2 SFfO^PS, 
 
 PJTI I MPMjtY. 1/ ''/7(. Ifil 3 PM. 
 
67 
 
 APPENDIX B 
 
 A SPiMFLE SIGML SORT LISTING OF CUBD/WEDTRI 
 
 RFM*RK <;iG K/*MF PKGE ID PJK Fff-E TYPF S/L SYMBHL NAME SFO 
 
 riK----bC1 PUFF 016 fLKPUr I r[ pj 1 1 
 
 ClK----fiCl A?00 OP? riL013 S <■[ p] 1 2 
 
 f I K-----f A200 016 rlL^13 I Af r] 2 3 
 
 ClK-----rO P-02 A03 PIN S *[ f] 2 1 
 
 C|K-----ri A?CO OM rlL013 I Af ll 3 ^ 
 
 flR-----Cl P-0? A07 PIN S A[ n 3 6 
 
 Gf^PUhn-'io AO?ft 003 runiY i r[ n a 7 
 
 f.pnu^n--lO ao?« 001 riintv s rr n 4 b 
 
 f.PGiiKr--ii AO?s 006 runiY L rt ?i 5 9 
 
 Gi:(iUKn--ii AO?s 007 runiY s r[ p] 5 10 
 
 r,KoiiNn--i2 A0?b 003 runiY 1 rr ^] 6 11 
 
 f.P[a)Nn--i2 A0?5 ooj riinLY s ri o 6 12 
 
 r-p^u^^-•lJ ao?7 oc6 runiY i r[ /, ] 7 13 
 
 GFc.UK.n--i3 A027 007 riiPiY s rr ill 7 14 
 
 GByuNn--lA Ap?7 P03 nHniY I (■[ "^l B 15 
 
 GPCl)^p--l« A0?7 opi rilniY s ft ^^1 e 16 
 
 r•fiUll^n•-lb AC?fl op6 riiniY i Pr ^] 9 i7 
 
 Gf'OllK'P--lb AC26 007 PIIPIY S P[ 6] 9 1« 
 
 rpniiKn--i6 ao?« 003 riLniy l Pt 71 10 19 
 
 PPLUK'n--16 A0?8 001 rllPLY S P[ 7] 10 20 
 
 GJ;Lll^n•-17 A036 OOh TTIPLy L P[ P] 11 21 
 
 P''fll^^--l7 A036 00^ runiY s rr «] Ij H 
 
 GP[iUKr--lf< A036 003 PILOlY I P[ ol 12 23 
 
 Gf>liUMr--ld A036 0(^1 rlinLY S Pf o] 1? 24 
 
 GF{>U^n--1S' A046 006 niLnLY L P[ Ir) 13 ?b 
 
 Gf<nUKn--19 AOflft 007 riL'^IY S P[ IP] 13 26 
 
 GFnUMn--?0 A0fl6 003 riLPI Y I P[ 11] 14 27 
 
 GF-CUhP'-PO A046 OPI flLPLY S Ct 111 14 28 
 
 GUillKn--?! A056 0P6 PILPLY L P[ 1?1 15 29 
 
 GPt)Ll^n--?l A056 007 PIIPIY S C[ l9] 15 30 
 
68 
 
 xrR-5D--po 
 TrR-««n--PO 
 
 P-0? 
 AU37 
 
 B?8 
 005 
 
 PIN 
 
 riL0?7 
 
 L 
 S 
 
 PI 
 PI 
 
 ?Bl 
 ?Al 
 
 75 
 75 
 
 158 
 159 
 
 TFR-fiP"Pl 
 TFR-5b--pl 
 
 A037 
 
 B?0 
 00« 
 
 PTN 
 DIL027 
 
 Si 
 
 ^1 
 
 293 
 293 
 
 H 
 
 160 
 61 
 
 T-ALT--*PO 
 
 t-aCt---po 
 
 T-ALT — PO 
 T-ALT---PO 
 T-Al T---PO 
 
 A139 
 A139 
 
 A014 
 
 AOlA 
 
 A015 
 
 OH 
 009 
 
 OH 
 
 009 
 
 OOfl 
 
 nlLOll 
 
 niton 
 riLoii 
 riLOii 
 
 rlL0?2 
 
 L 
 L 
 
 L 
 
 L 
 
 S 
 
 
 3<^:i 
 
 3ft] 
 3ft] 
 3ft] 
 
 Vr 
 
 77 
 77 
 77 
 
 162 
 163 
 164 
 16b 
 
 166 
 
 T-ALT---PI 
 
 AOI ft 
 A015 
 
 811 
 
 002 
 
 Fits 1 
 
 riLO?? 
 
 s 
 
 f[ 1?) 
 
 rt 371 
 
 n 
 
 78 
 
 167 
 
 6b 
 
 169 
 
 T-ALT---PO 
 T-ALT---PO 
 T-ALT---PO 
 T-ALT---PO 
 T-ALT---PO 
 T-Al T---PO 
 T-AIT---PO 
 
 Al?o 
 Al?9 
 Al?6 
 Al?6 
 Al?l 
 A121 
 Al?? 
 
 013 
 
 012 
 013 
 012 
 013 
 012 
 OOfl 
 
 riLonr 
 
 DILOUr 
 
 riLOiir 
 riLOuc 
 niiorc 
 rlLOir 
 
 niiorr 
 
 L 
 L 
 1 
 
 L 
 L 
 L 
 S 
 
 re 
 r[ 
 
 3P] 
 3P] 
 3P] 
 3l?3 
 3fl] 
 3P1 
 3f] 
 
 79 
 79 
 79 
 79 
 79 
 79 
 79 
 
 170 
 171 
 172 
 173 
 174 
 175 
 176 
 
 T-Al T---R1 
 T-ALT---PI 
 
 T-ALT---PI 
 T-ALT---P1 
 T-ALT---P1 
 T-ALT---P1 
 T-ALT---P1 
 T-Al T---P1 
 
 A1?H 
 Al?8 
 
 Al?S 
 Al?5 
 A117 
 A117 
 AOl«j 
 AJ?2 
 
 013 
 
 012 
 
 013 
 012 
 013 
 012 
 001 
 002 
 
 rlLOlT 
 
 rii onr 
 
 riLonr 
 niLOhr 
 riLorc 
 riLCnr 
 
 f IL022 
 
 nlLonc 
 
 L 
 
 L 
 
 L 
 
 L 
 L 
 I 
 L 
 S 
 
 <"[ 
 
 01 
 01 
 01 
 
 rt 
 ^t 
 
 0[ 
 
 30] 
 3o] 
 
 3o1 
 30] 
 
 39] 
 3o] 
 39] 
 3Q] 
 
 80 
 60 
 
 80 
 80 
 80 
 80 
 60 
 80 
 
 177 
 176 
 
 179 
 180 
 161 
 18? 
 183 
 184 
 
 T-Al T---S1 
 T-ALT---51 
 
 Al?2 
 P-Cl 
 
 OH 
 P32 
 
 r iLonr 
 
 PIN 
 
 L 
 S 
 
 A[ 
 
 «I 
 
 ir] 
 IPl 
 
 SI 
 81 
 
 185 
 166 
 
 T-HIKDATAI 
 T-PIKPAT/Sl 
 
 AOPl 
 AG76 
 
 013 
 002 
 
 r u 4 
 
 rlL02? 
 
 L 
 S 
 
 rr 
 r[ 
 
 HO) 
 40] 
 
 82 
 b? 
 
 167 
 186 
 
 T-bTT35-f,l 
 T-fIT3"i-r.l 
 T-HIT35-r,l 
 T-HlT35-f.l 
 
 A130 
 A130 
 A076 
 A13? 
 
 012 
 013 
 
 ooe 
 
 007 
 
 riiooh 
 r iLora 
 run?? 
 rii02? 
 
 L 
 
 L 
 I 
 
 rt 
 
 01 
 
 rt 
 ot 
 
 41 ] 
 41 ] 
 
 «1 ] 
 41 1 
 
 83 
 83 
 
 83 
 83 
 
 189 
 190 
 191 
 192 
 
 T-MITFO-Gl 
 T-FITFO-f-l 
 
 A091 
 A090 
 
 Oil 
 
 00b 
 
 riLPLv 
 
 rlLOOT 
 
 L 
 S 
 
 rt 
 '■t 
 
 4?] 
 421 
 
 84 
 84 
 
 193 
 194 
 
 T-HITFO-l 
 T-HITFO-LO 
 
 A13? 
 A0P5 
 
 013 
 006 
 
 r 11.022 
 
 r IL008 
 
 L 
 S 
 
 rt 
 rt 
 
 "31 
 tt.-^l 
 
 65 
 85 
 
 195 
 196 
 
APPENDIX C. LISTINGS OF CUBD/WEDTR2 
 C-1 
 A SAMPLE PACKAGE NAME AM) PIN SORT LISTING OF CUBD/WEDTR2 
 
 69 
 
 CU »0*RD«TPI$P 
 
 «OCl 
 
 <riLr22) 
 
 1 
 
 
 001 
 
 T-HVOLT — J 
 
 (PI 
 
 00* ) 
 
 005 
 
 T-irC — K63 
 
 ( 
 
 ) 
 
 00« 
 
 T-mVOLT — I 
 
 COI 
 
 C0«) 
 
 on 
 
 T-CLK0J--1 
 
 (BUFF 
 
 003) 
 
 002 T-TFC"K6t ( ) 
 
 007 T«TrC"KG? ( ) 
 
 on T-NVOLT — J (DI 00«) 
 
 01« T-luSFTtfil (»09i» 005) 
 
 00* T-TFC--KGO ( ) 
 
 COe T-INSFTEGl (A09b 00b) 
 
 012 T-CLK02"! (PUFF 003) 
 
 016 1-KVCLT--1 (DI C0«> 
 
 AOC? (PILOOS) 2 
 
 007 T-TFC0«-L1 ( ) 
 
 01? T-TO — -Gl («01« 00?) 
 
 007 T-TrC05-Lt ( ) 
 
 Pt3 T-TFC--K01 (AOOl 002) 
 
 on 
 
 014 
 
 T-TFC--K60 
 TTFC05-D1 
 
 (*001 
 (*007 
 
 00«) 
 013) 
 
 *003 (riLOOR) 3 
 
 0P2 T-TFC02-L1 ( ) 
 
 012 T-TFC0«-01 (»0P7 01*) 
 
 007 T-TrC03-Ll ( ) 
 
 013 T-TFC--KG1 (*001 002) 
 
 on 1-TFC--HG0 (AOOl 
 01* T-TfC03-01 (A006 
 
 00«) 
 U13) 
 
 »0C« (r>U00») • 
 
 00? T-TFCOO-Ll ( ) 
 
 C|? T-TFC02-01 (AOOe 016) 
 
 007 T-TreOt-Ll ( ? 
 
 013 T-TrC--KG3 (AOOl 005) 
 
 on 
 
 014 
 
 T1FC--KG2 (AOOl 
 T-TFC01»0> (AOlO 
 
 007) 
 013) 
 
 AOCb (rUOOB) 5 
 
 00? T-TPR06-LI < ) 
 
 01? T-TFCOO-01 (AOlO P16) 
 
 PP7 T-TDB07-L1 
 013 T-TFC — KG3 
 
 ( ) 
 
 (AOOl 005) 
 
 on 
 
 014 
 
 T-tf C--K62 
 T-TDh07-Dl 
 
 (AOOl 
 (AOll 
 
 007) 
 013) 
 
 A0C6 (riL007) (, 
 
 001 T-TFC0?-61 ( ) 
 
 008 T-TFC05-C1 ( ) 
 
 013 7-TFC03-LI (A0P3 r07) 
 
 004 T-TFCOJ-Gl ( ) 
 
 009 T-TFC05-L1 (AOO? 007) 
 
 014 T-NVOLT"! (PI 004) 
 
 005 
 
 TTFC04-G1 
 
 ( 
 
 )■ 
 
 012 
 
 TTfC04-Ll 
 
 (A002 
 
 00?) 
 
 016 
 
 T-TFC02-L1 
 
 (A003 
 
 002) 
 
 At07 {riLPLV) 7 
 
 Oil T-TFC05-G1 (A006 rn«) 
 
 OU T-TFC04-D1 ( ) 
 
 fiPOllKD SIGNALS APE rELFTFI). 
 
 T-TfC05-Dl 
 
 014 
 
 TTFC04-G1 (A006 005) 
 
 "»• on "1t9^)'33.Gl (i!006 004) 
 
 Cit T-TFC02-D1 ( ) 
 
 fiPOUNO Slr.NALS ARE PFLFTFl). 
 
 AtOO (riLn07) 9 
 
 001 1-TDP0*-Gt ( ) 
 
 OOP T-TFCOI-Gl ( ) 
 
 tl3 1-TPR07-L1 (A005 O07) 
 
 013 
 
 T-TFC03-01 
 
 004 
 
 T-TPROT-Gl 
 
 ( 
 
 ) 
 
 009 
 
 T-TFC01-L1 
 
 (Aoo;r 
 
 007) 
 
 014 
 
 T-NV0LT--1 
 
 (DI 
 
 004] 
 
 014 
 
 T-TFC02-GJ (A006 001) 
 
 005 
 
 T-IFCOO-Gl 
 
 ( 
 
 ) 
 
 012 
 
 T-Tf tOO-Ll 
 
 (A004 
 
 002) 
 
 016 
 
 T-TUK06-L1 
 
 (A005 
 
 002) 
 
70 
 
 o o 
 o o 
 
 o o 
 o o 
 
 l/t <x « 
 
 o o o 
 o o o 
 
 (NJ tA 
 
 m — 
 
 » u. 
 o o — 
 « X c 
 
 o o 
 
 O 
 
 a. 0. 
 
 l/> lA 
 
 1 I 
 
 oi 1/1 I 
 
 J. a. t- 
 
 OO -I 
 
 a. a. o 
 
 i/i i/> » 
 
 a o ^ 
 
 • • • 
 
 o •• •« >• 
 
 ^ I I 
 X W I • 
 
 t >- •• t- 
 
 1 u o ^ 
 
 X M X O 
 
 O 2 -1 » 
 
 »« « 
 
 -• « 
 
 K. *« « 
 
 • • '^ 
 
 •* ♦ 
 
 lA X « 
 
 « a M « 
 
 
 
 O •• '• 
 
 o o •< 
 
 
 O •• M 
 
 o o •• - 
 
 o o 
 
 o o 
 
 o o o 
 
 o o o 
 
 o o 
 
 o o o 
 
 o o o a 
 
 o o 
 
 • — o — 
 
 «- ^ «- *M 
 
 ^ ^ 
 
 — -- c 
 
 ^ C\. *- *« 
 
 1 O S IT 
 
 CL (9 ■ t 
 
 -1 U 
 
 O I i 
 
 O O 1 l£ 
 
 ■ III 
 
 ■ III 
 
 1 H. 
 
 1 I 1 
 
 X ^ 1 U: 
 
 • 1 i 1 
 
 1 1 »- »- 
 
 a. a. 
 
 
 • 1 >- »- 
 
 1 1 • CVJ 
 
 1 1 _l -I 
 
 o c 
 
 O J _1 
 
 1 1 -J u. 
 
 i i t- 1 
 
 >- 1 c o 
 
 0. a 
 
 o c o 
 
 (r a o to 
 
 — C. _1 c 
 
 _ Cr =. > 
 
 */. ^/ 
 
 a > > 
 
 C C > 2 
 
 1 I- •« a 
 
 « K 2 2 
 
 c c 
 
 ►- 2 Q. 
 
 >->-*»- 
 
 »^ « 
 
 K « 
 
 ir\ » '^ 
 
 rv. o <\> 'C 
 
 K »*» 
 
 « o- m 
 
 <\. ►. -> • 
 
 o - 
 
 o — 
 
 o o — 
 
 c o — — 
 
 O w 
 
 o o — 
 
 o c. — ^ 
 
 o c 
 
 o o 
 
 o o c 
 
 c c c o 
 
 o c 
 
 Oct 
 
 o o o o 
 
 « cv. « 
 o o o 
 c. o & 
 
 O O 
 
 o c 
 
 (\ 9 <C 
 
 o o — 
 
 CN* irv *n 
 o o o 
 
 -*w w < 
 
 ^ *4 
 
 < 
 
 •« »« 
 
 < 
 
 — I 
 
 «« 
 
 
 V4 .M ..« •-• 
 
 -. ^ o 
 
 ^ 
 
 <^ ^ 
 
 c — — <^ 
 
 ^ r^ *« ^ 
 
 J o 
 
 2 
 
 o a 
 
 z 
 
 <r 1 
 
 a 
 
 
 J X a. o: 
 
 X o _; 
 
 1 
 
 _1 O 
 
 C O 1 o 
 
 1 >3 1 1 
 
 ■ 1 
 
 *s 
 
 • 1 
 
 o 
 
 1 I 
 
 I 
 
 
 III! 
 
 a «/) 1 
 
 1 
 
 1 tA 
 
 lull 
 
 1 Jk 1 1 
 
 — c. 
 
 ^- 
 
 ^. « 
 
 ^- 
 
 1 I 
 
 ■ 
 
 
 ■ Ill 
 
 • (LI 
 
 ^ 
 
 O. O. 
 
 — a. 1- — 
 
 •- 1 »- ^ 
 
 '»0 o 
 
 m 
 
 «o o 
 
 w. 
 
 ^—1 
 
 '> «« 
 
 
 '"I - 1 — 
 
 '« 1 O 1 
 
 ^ 
 
 ^sO o 
 
 '^O O _( o 
 
 '^-i 1 _. o 
 
 >-c» *- 
 
 
 >-ir a 
 
 
 u 1 1 
 
 c: ■ 
 
 
 i>-l I ■- I 
 
 Cu •> a. ■ 
 
 c; 
 
 oo. a. 
 
 — 13 a. c o 
 
 c\.o a C le 
 
 _tU. kfc 
 
 o 
 
 _IO o 
 
 a 
 
 o ^ rsi 
 
 c: a 
 
 (V 
 
 -*a o ^ o 
 
 (Ni _) tn « 
 
 
 C»/) */■• 
 
 — oc tA > a 
 
 C\i^ o » ^ 
 
 c.»- »- 
 
 ^ 
 
 o*- *- 
 
 2 
 
 O ¥- t 
 
 o a. 
 
 1 
 
 OCT >- « a. 
 
 o « c a. 
 
 2 
 
 oc c 
 
 ct- C 2 «- 
 
 02 ^ 2 W 
 
 -Jl 1 
 
 :^ 
 
 _JI ■ 
 
 3 
 
 -1 I O 
 
 -1 1 
 
 o 
 
 _<• 1 1 1 
 
 -1 1 1 1 
 
 1 
 
 -.1 1 
 
 
 -11 1 1 1 
 
 ■"■*" *~ 
 
 o 
 
 ►-•^- ^ 
 
 o 
 
 •-• ►- ^ 
 
 •-• ^ 
 
 (T 
 
 •-•- »— ►- ^- 
 
 •-I ►- »- ►- 
 
 ►- 
 
 
 
 
 9 rs. 
 
 c — 
 
 O w 
 
 « a. cv o 
 c o *- — 
 o o o o 
 
 — iT — « 
 O O — — 
 
 o o o o 
 
 o -* 
 ^ o 
 
 Ou ^ <\. <C 
 
 o o — — 
 
 o o o o 
 
 — lA o 'n 
 o o o -^ 
 o w o o 
 
71 
 
 APPEm)IX C. LISTINGS OF CUBD/WEDTR2 
 
 C-2 
 
 A SAMPLE ARC LISTING OF CUBD/WEDTR2 
 CU P0AR0«TDISP ARC LIST 
 
 AOOJ 
 
 4- 
 
 ni 
 
 AOOl 
 
 * 
 
 A09e 
 
 AOOl 
 
 
 PUFF 
 
 
 
 
 A002 
 
 4- 
 
 AOOl 
 
 A002 
 
 4 
 
 A014 
 
 AOO? 
 
 
 4007 
 
 
 
 
 «003 
 
 * 
 
 AOOl 
 
 A003 
 
 4- 
 
 A007 
 
 A003 
 
 
 4008 
 
 
 
 
 A004 
 
 «■ 
 
 AOOl 
 
 A004 
 
 ♦ 
 
 A00« 
 
 A004 
 
 
 4010 
 
 
 
 
 AOOb 
 
 ♦ 
 
 AOOl 
 
 A005 
 
 4- 
 
 AOIC 
 
 A005 
 
 
 4011 
 
 
 
 
 A006 
 
 ♦ 
 
 A002 
 
 A006 
 
 4- 
 
 A003 
 
 AOO^ 
 
 
 PI 
 
 
 
 
 A007 
 
 4- 
 
 A006 
 
 
 
 
 
 
 
 
 
 
 toot 
 
 ♦• 
 
 A006 
 
 
 
 
 
 
 
 
 
 
 acov 
 
 4- 
 
 A0U4 
 
 A0U9 
 
 4- 
 
 A005 
 
 A009 
 
 4 
 
 rl 
 
 
 
 
 AOIC 
 
 4- 
 
 AC09 
 
 
 
 
 
 
 
 
 
 
 AOll 
 
 4- 
 
 A009 
 
 
 
 
 
 
 
 
 
 
 AOl? 
 
 4- 
 
 ri 
 
 AOl? 
 
 4 
 
 P-03 
 
 
 
 
 
 
 
 A013 
 
 4- 
 
 DI 
 
 A013 
 
 4- 
 
 H-o:< 
 
 
 
 
 
 
 
 *014 
 
 4- 
 
 AOl? 
 
 A014 
 
 4- 
 
 A015 
 
 A014 
 
 4- 
 
 4013 
 
 
 
 
 AOlb 
 
 4- 
 
 A122 
 
 AOl 5 
 
 4- 
 
 A014 
 
 ACIS 
 
 4 
 
 4120 
 
 4015 4- 
 
 4116 
 
 A01«; «• 01 
 
 a016 
 
 4- 
 
 Alb2 
 
 A016 
 
 4 
 
 A015 
 
 
 
 
 
 
 
 A017 
 
 4- 
 
 A137 
 
 AC17 
 
 4- 
 
 DI 
 
 A017 
 
 4 
 
 4015 
 
 4017 4. 
 
 4094 
 
 
 A016 
 
 4 
 
 ni 
 
 AOIS 
 
 4 
 
 A09P 
 
 AOIP 
 
 4 
 
 PUFF 
 
 
 
 
 A019 
 
 ♦ 
 
 ACIR 
 
 A019 
 
 4 
 
 ACl 1 
 
 A019 
 
 4 
 
 4024 
 
 
 
 
 *020 
 
 4- 
 
 AOie 
 
 4020 
 
 4 
 
 A024 
 
 A020 
 
 4- 
 
 4025 
 
 
 
 
 4021 
 
 4- 
 
 4018 
 
 4021 
 
 4 
 
 AOi**! 
 
 A021 
 
 4 
 
 4027 
 
 
 
 
 fiOPi; 
 
 4- 
 
 AOl a 
 
 A022 
 
 4- 
 
 4C?7 
 
 A02? 
 
 4 
 
 4026 
 
 
 
 
 fiC23 
 
 4 
 
 AC20 
 
 40i?3 
 
 4- 
 
 401<? 
 
 A023 
 
 4 
 
 PI 
 
 
 
 
 /^G?A 
 
 4 
 
 A023 
 
 
 
 
 
 
 
 
 
 
 402b 
 
 4 
 
 A023 
 
 
 
 
 
 
 
 
 
 
 4026 
 
 4 
 
 A021 
 
 4026 
 
 4- 
 
 4C2? 
 
 A026 
 
 4 
 
 rl 
 
 
 
 
 /C?7 
 
 4- 
 
 A0?6 
 
 
 
 
 
 
 
 
 
 
 AOPe. 
 
 ♦ 
 
 4026 
 
 
 
 
 
 
 
 
 
 
 A029 
 
 4- 
 
 DT 
 
 4029 
 
 4- 
 
 A09P 
 
 4020 
 
 4- 
 
 f-UFF 
 
 
 
 
 4030 
 
 4 
 
 A019 
 
 A030 
 
 4 
 
 AC05 
 
 A030 
 
 4 
 
 n 
 
 
 
 
 A031 
 
 4- 
 
 Af^20 
 
 4031 
 
 4- 
 
 A021 
 
 A031 
 
 4 
 
 I' I. 
 
 
 
 
 403^ 
 
 4- 
 
 4029 
 
 4032 
 
 4 
 
 Ar?'» 
 
 A0 3? 
 
 4 
 
 rl 
 
 
 
 
 4(33 
 
 4' 
 
 A1 1ft 
 
 A033 
 
 4- 
 
 A139 
 
 4033 
 
 4 
 
 4103 
 
 4O33 4. 
 
 4131 
 
 
 aC3<» 
 
 4- 
 
 4002 
 
 4034 
 
 4 
 
 A033 
 
 A034 
 
 4 
 
 f 041 
 
 
 
 
 4035 
 
 4 
 
 4039 
 
 A035 
 
 4 
 
 AC 34 
 
 
 
 
 
 
 
 4036 
 
 4 
 
 AC35 
 
 4036 
 
 4- 
 
 A 04 
 
 
 
 
 
 
 
 A037 
 
 4- 
 
 A035 
 
 4037 
 
 4- 
 
 PI 
 
 
 
 
 
 
 
 403b 
 
 4- 
 
 ri 
 
 40 JP 
 
 4 
 
 40^3 
 
 403P 
 
 4- 
 
 4041 
 
 
 
 
 403V 
 
 4- 
 
 ni 
 
 4039 
 
 4- 
 
 A03fl 
 
 A039 
 
 *■ 
 
 tUFF 
 
 
 
 
 4 04C 
 
 4- 
 
 AC39 
 
 4040 
 
 4- 
 
 4034 
 
 
 
 
 
 
 
 4041 
 
 4 
 
 DI 
 
 4041 
 
 4 
 
 403^ 
 
 
 
 
 
 
 
 ton? 
 
 4- 
 
 A040 
 
 A042 
 
 4- 
 
 P! 
 
 
 
 
 
 
 
 4043 
 
 4 
 
 ri 
 
 4043 
 
 4 
 
 A041 
 
 4 04 3 
 
 4 
 
 A051 
 
 
 
 
 (.om* 
 
 4 
 
 4003 
 
 4 04 4 
 
 4- 
 
 A033 
 
 40«i 
 
 4 
 
 4051 
 
 
 
 
 404b 
 
 4 
 
 A049 
 
 4045 
 
 4 
 
 AC44 
 
 
 
 
 
 
 
 4046 
 
 4- 
 
 A045 
 
 4046 
 
 4- 
 
 4050 
 
 
 
 
 
 
 
 4047 
 
 4- 
 
 A045 
 
 4047 
 
 4 
 
 ni 
 
 
 
 
 
 
 
 4046 
 
 4- 
 
 n 
 
 4048 
 
 4- 
 
 A033 
 
 A04« 
 
 4- 
 
 4043 
 
 
 
 
 4049 
 
 4 
 
 ni 
 
 4049 
 
 4- 
 
 AC48 
 
 4049 
 
 4 
 
 t'UfF 
 
 
 
 
 405C 
 
 4 
 
 A049 
 
 4050 
 
 4 
 
 A04A 
 
 
 
 
 
 
 
 40bl 
 
 4- 
 
 A046 
 
 A051 
 
 4- 
 
 ni 
 
 
 
 
 
 
 
 4052 
 
 4 
 
 4045 
 
 A052 
 
 4- 
 
 4040 
 
 4052 
 
 4 
 
 4035 
 
 4O52 4. 
 
 nl 
 
 A05? ♦ A135 
 
 4053 
 
 4- 
 
 ni 
 
 A053 
 
 4 
 
 A041 
 
 405.^ 
 
 4 
 
 4051 
 
 4O53 4. 
 
 4053 
 
 4053 * A057 
 
 4054 
 
 4- 
 
 4004 
 
 A054 
 
 4- 
 
 A033 
 
 4054 
 
 4- 
 
 4057 
 
 
 
 
 405b 
 
 4 
 
 A059 
 
 A055 
 
 4 
 
 A 05 4 
 
 
 
 
 
 
 
 4f56 
 
 4 
 
 A0b5 
 
 A0b6 
 
 4 
 
 A&60 
 
 
 
 
 
 
 
 A057 
 
 4- 
 
 ni 
 
 4057 
 
 4- 
 
 A05^ 
 
 
 
 
 
 
 
 4056 
 
 4 
 
 01 
 
 AObe 
 
 4 
 
 A033 
 
 AObP 
 
 4 
 
 4053 
 
 
 
 
 4059 
 
 4- 
 
 PI 
 
 A0b9 
 
 4- 
 
 A05f 
 
 A059 
 
 4 
 
 f'Vff 
 
 
 
 
72 
 
 APPENDIX C. LISTINGS OF CUBD/WEDTR2 
 
 C-3 
 
 A SAMPLE PACKAGE NAME LISTING OF CUBD/WEDTR2 
 CD PnARD»TDlSP PACkaGF LIST 
 
 
 
 AOOl 
 
 ruo2? 
 
 1 
 
 AOO?I 
 
 DIL008 
 
 2 
 
 A0020 
 
 oiLOoe 
 
 3 
 
 A003I 
 
 DIL008 
 
 b 
 
 A003n 
 
 Oil OOP 
 
 5 
 
 A004I 
 
 DUone 
 
 ft 
 
 A004n 
 
 OIL 008 
 
 7 
 
 A005I 
 
 OIL 008 
 
 H 
 
 Acosn 
 
 niLOOh 
 
 9 
 
 A006 
 
 I,'IL007 
 
 10 
 
 A007 
 
 MIDI Y 
 
 n 
 
 A008 
 
 Oil 01 Y 
 
 12 
 
 A009 
 
 [)Il 007 
 
 13 
 
 AOlO 
 
 Oil UL Y 
 
 M 
 
 AOll 
 
 on 01 Y 
 
 15 
 
 AOl? 
 
 DIl OOC 
 
 1ft 
 
 A013 
 
 oiioor 
 
 17 
 
 A014 
 
 t) I L n 
 
 IP 
 
 A015 
 
 LILO?? 
 
 19 
 
 A016I 
 
 fjlLorw 
 
 20 
 
 AOlftO 
 
 f II OOtt 
 
 2\ 
 
 A017 
 
 I L 11 
 
 2? 
 
 AOie 
 
 1 II 022 
 
 23 
 
 A019T 
 
 I II 00ft 
 
 ?« 
 
 A019n 
 
 r iLOf ft 
 
 ?5 
 
 A020I 
 
 (;li oofi 
 
 2ft 
 
 AOpon 
 
 nliooft 
 
 27 
 
 A0?1I 
 
 iMl 00ft 
 
 28 
 
 AO?in 
 
 OiLOOft 
 
 29 
 
 A022T 
 
 oil Ot'ft 
 
 30 
 
 A0??n 
 
 T'llorM 
 
 31 
 
 A023 
 
 nil 00 7 
 
 3? 
 
 A024 
 
 OILOL V 
 
 3 3 
 
 A025 
 
 OILOI V 
 
 34 
 
 A0?ft 
 
 oil 007 
 
 35 
 
 A0?7 
 
 DIL 01 Y 
 
 3ft 
 
 A02« 
 
 on 01 Y 
 
 37 
 
 A029 
 
 riLo?? 
 
 3« 
 
 A030 
 
 [ IL007 
 
 39 
 
 A0 31 
 
 ( IL007 
 
 «0 
 
 A032I 
 
 on 008 
 
 *1 
 
 A032C 
 
 [ II 00ft 
 
 UP 
 
 A033 
 
 I.IL027 
 
 43 
 
 A034 
 
 on on 
 
 UU 
 
 A0351 
 
 nil OOP 
 
 45 
 
 A0350 
 
 1 n 00ft 
 
 4ft 
 
 A03ft 
 
 on (u V 
 
 47 
 
 A037 
 
 L IL027 
 
 4« 
 
 A03P 
 
 riLoii 
 
 4Q 
 
 A039 
 
 1 11.022 
 
 50 
 
 A040T 
 
 [ II 00ft 
 
 51 
 
 A040n 
 
 ill 008 
 
 b? 
 
 A041 
 
 ( II 022 
 
 53 
 
 A042 
 
 1 II 027 
 
 54 
 
 A043 
 
 1 11022 
 
 55 
 
 A044 
 
 III Oil 
 
 5ft 
 
 A045I 
 
 on 008 
 
 57 
 
 A045n 
 
 OiLOOft 
 
 56 
 
 A04ft 
 
 on 01 Y 
 
APPENDIX D. LISTINGS OF CUBD/LEVELER 
 D-1 
 
 73 
 
 A SAMPIiE SOURCE DESTINATION LISTING OF CUBD/LEVELER 
 SOUPfF DE^'TnATION list CU B0AR0«T0ISP 
 
 PACKAGEbAOOI 
 SOURCE 
 OESTINAt'-ON 
 
 PACKAGE«A002T 
 SOURCE 
 DESTINATION 
 
 PACKAGE«AOO?n 
 SOURCE 
 DESTINAt on 
 
 PACKAGEbA003I 
 SOURCE 
 DESTINATION 
 
 PACKAGE>A0030 
 SOURCE 
 DESTINATION 
 
 PACKAGE*A304T 
 SOURCE 
 
 DESTINAt ON 
 
 PACKAGE«A0O<(n 
 SOURCE 
 DESTINAt ON 
 
 PACKAGE«A005I 
 SOURCE 
 DESTINAt'-ON 
 
 PACKAGE«A0050 
 SOURCE 
 DESTINAT ON 
 
 PACKAGE>A306 
 SOURCE 
 DESTINATION 
 
 PACKA6E»A0O7 
 SOURCE 
 DESTINAt on 
 
 PACKAGE'AOOA 
 SOURCE 
 DESTINATION 
 
 ( 0) NO OF SOURCE" 3 NO OF DFSTlNATIONi 
 176 Itr 175 
 
 13 5 7 
 
 r 1) NO OF SOURCE* 3 Np Or DrSTlNATlON* 
 17 10 
 
 f ?) NO nr SOURCE" o Nn nr otstinationb a 
 
 9 43 95 98 
 
 ( 3) Nn nr source* 3 no nr nrsTiNATlON. o 
 
 IP 11 
 
 r A) Nn nr source* o Nn nr prsTINATlON* i 
 
 5"S 
 
 95 
 
 f 5) Nn nr souRcr* 3 Nn or nrsTiNATinN« o 
 
 11 13 
 
 f f) Nn nr snuRcr* o Nn nr nrsTiNATlON* a 
 
 12 ^7 90 95 
 
 ( 7) Nn nr source* 3 Nn nr nrSTlNATiON« o 
 
 13 lA 
 
 r P) Nn nr source* o Nn nr nrsTiNATiON* a 
 
 1? 
 
 3« 
 
 fl(S 
 
 90 
 
 9) Nn nr snuRCE* 3 Nn nr nrsTiNATiON* ? 
 
 ? A 176 
 10 11 
 
 f IP) Nn nr snURcr* j Nn nr nrSTlNATlONi 
 
 9 
 
 1 3 
 
 f 11) Nn nr source* i Nn nr nrsTiNATlON* 2 
 
 9 
 
 3 5 
 
7h 
 
 APPEKDIX D. LISTINGS OF CUBD/LEVELER 
 D-2 
 
 A SAMPLE LEVEL ASSIGNMENT LISTING OF CUBD/LEVELER 
 
 LFVri' ASSI^.►'^E^T I 1ST 
 
 rii bdaRObTDISP 
 
 oKCKAfif 
 *002n 
 A003n 
 AOO«n 
 AOObn 
 A01 6n 
 A019n 
 AO?On 
 AO?ln 
 A0?2n 
 A03?n 
 A03!>n 
 AOaOn 
 A0a5n 
 AOSOn 
 AOSbn 
 AO^On 
 AOPbn 
 A0f6n 
 AOP/'n 
 A fl 9 n 
 AlOlr 
 A man 
 A 1 nfln 
 « 1 1 ?n 
 All 6p 
 Al ?0n 
 Al ?«n 
 Al Ibn 
 
 purr 
 
 F - n 1 n 
 F-n?n 
 
 F-OJn 
 F-nin 
 r-Obn 
 
 ftooft 
 
 f (lOV 
 A 1? 
 API 3 
 AC?? 
 AO?ft 
 A (' 3 U 
 A031 
 «()3ft 
 A03'' 
 A04<? 
 A 8 6 
 A()4 ^ 
 ACS? 
 A0S6 
 AOf 1 
 A0'.3 
 AOftb 
 A06^ 
 A 1 03 
 Al 09 
 Alio 
 Al ?2 
 
 FWn Lvl FLAG 
 
 rwn 
 
 NO OF PACKAfiFS* l«r 
 
 I. VI. 
 
 n 
 
 
 
 ft 
 
 
 
 
 ft 
 n 
 ft 
 ft 
 ft 
 ft 
 ft 
 ft 
 ft 
 ft 
 ft 
 ft 
 ft 
 
 ft 
 ft 
 n 
 ft 
 ft 
 ft 
 ft 
 ft 
 n 
 ft 
 ft 
 ft 
 ft 
 ft 
 ft 
 ft 
 
 RKWD 
 
 LVL 
 
 ft 
 
 
 
 
 
 
 
 n 
 1 
 
 
 
 
 
 
 
 ft 
 ft 
 ft 
 ft 
 ft 
 ft 
 ft 
 ft 
 ft 
 1 
 ft 
 ft 
 1 
 ft 
 ft 
 n 
 ft 
 ft 
 
 ft 
 n 
 ft 
 1 
 1 
 
 ft 
 1 
 1 
 1 
 1 
 ft 
 1 
 1 
 ft 
 
 1 
 
 ft 
 
 ft 
 1 
 n 
 1 
 
 n 
 ft 
 ft 
 ft 
 
 
 Fl AG 
 
 RKWO LVL 
 
75 
 
 A132 
 
 A13A 
 «U1 
 «142 
 
 M53 
 
 »15b 
 
 A200 
 
 4007 
 
 »008 
 
 «010 
 
 AOll 
 
 *0?« 
 
 »0?5 
 
 A0?7 
 
 «0?8 
 
 A041 
 
 «0S1 
 
 A057 
 
 A062 
 
 *064 
 
 A0A6 
 
 A066 
 
 A076 
 
 All/ 
 
 Al?l 
 
 A12S 
 
 A176 
 
 Al?7 
 
 A140 
 
 P-05t 
 
 AOli 
 
 A069 
 
 A070 
 
 A 73 
 
 A07« 
 
 A077 
 
 A07fl 
 
 A079 
 
 AOR? 
 
 #1?6 
 
 A129 
 
 P-0?T 
 
 P-04T 
 
 A071 
 
 A075 
 
 AOflO 
 
 A0B3 
 
 A090 
 
 P-03T 
 
 A072 
 
 A091 
 
 A09? 
 
 AOl** 
 
 AOl^ 
 
 A053 
 
 AOfll 
 
 A096 
 
 A097 
 
 A09b 
 
 A102 
 
 AMI 
 
76 
 
 AUS 
 A11S 
 M19 
 
 M30 
 «131 
 
 *1 33 
 A134 
 «1 36 
 Al 37 
 A139 
 AlOb 
 A093 
 A09<l 
 AOl 7 
 A033 
 «03B 
 AOAB 
 «OSS 
 40fi6 
 4099 
 A106 
 AOOl 
 AOia 
 4029 
 ADS'* 
 A039 
 40^4 
 4069 
 l'O'3'i 
 40S9 
 40fl'» 
 A095 
 AlOO 
 4in7 
 41 1 3 
 Al?i 
 41 S2 
 Albtt 
 4002 
 4003 
 400« 
 4 005 
 401 6 
 401 9 
 A020 
 A021 
 A022 
 A032 
 4035 
 4040 
 4015 
 4050 
 A055 
 A060 
 A0B5 
 A0P6 
 40«7 
 40B9 
 4101 
 AlOU 
 
77 
 
 O O O O O O Ci 
 
 
 
 
 
 
 « 
 
 • • 
 
 
 c — 
 
 
 
 cv 
 
 
 C 
 Z 
 
 c 
 o 
 
 Ui 
 
 (/) 
 
 (/> 
 
 UJ 
 
 H- 
 3 
 Z 
 
 Z 
 
 V4 
 
 c c 
 z z 
 
 c c 
 o o 
 
 UI UI 
 
 (/> «/] 
 cv. o 
 
 «/} t/) 
 
 UJ Ui 
 
 ►- »- 
 
 3 3 
 Z Z 
 ^■^ ^t 
 Z 2 
 
 O CV 
 
 • 
 
 z 
 
 CL 
 
 in 
 
 < 
 
 c c 
 
 o c 
 
 c o 
 
 c 
 
 UJ 
 
 ir 
 
 •-« 
 I 
 
 UJ 
 
 Z 
 
 
 V 
 CD 
 
 » 
 >- 
 
 
 
 
 
 >- 
 
 
 u< 
 
 cr 
 
 
 
 
 
 z 
 
 «/) 
 
 Z 
 
 3 
 
 
 
 
 
 »i^ 
 
 Ui 
 
 »-« 
 
 I 
 
 
 
 
 
 « 
 
 u 
 
 ►- 
 
 ►- 
 
 
 
 
 
 ►- 
 
 u 
 
 
 
 ^x ^ 
 
 ^- »» 
 
 ^- ^• 
 
 ^- 
 
 or 
 
 c 
 
 c 
 
 
 «CM 
 
 >oo 
 
 « tn 
 
 m* 
 
 o 
 
 (T 
 
 >k z 
 
 
 o ^ 
 
 ^ CM 
 
 CVi f»» 
 
 o 
 
 ■ 
 
 a. 
 
 o 
 
 ►- 
 
 c 
 
 Uj 
 
 a. 
 
 ^i* ^- 
 
 
 Ui 
 
 Ui 
 
APPENDIX E. LISTINGS OF CUBD/REDUCE 
 
 E-1 
 
 A SAMPLE LEVEL ASSIGNMENT EXCLUDING LOOPED PACKAGES AND 
 ARC LISTINGS OF LOOPED PACKAGES OF CUBD/REDUCE 
 
 IMTIAt LEVEL ASSIr^i^fM ITST fU PrAPOsTTISP 
 
 78 
 
 t FVf I 
 
 I EVrLx 1 
 
 *oo?n 
 
 A03SC^ 
 AlOlP 
 P-0?ti 
 A006 
 
 A109 
 
 A003r 
 
 AO'iOr 
 A 1 r « r 
 p-c3r 
 * r, (, V 
 
 « (i 4 6 
 Alio 
 
 Ai/fl'-n 
 
 A1 OfO 
 (■-000 
 ACI? 
 A047 
 A 1??* 
 
 AOOSr 
 AO^fir 
 Ai i?n 
 
 AOl ^ 
 AO^? 
 A13? 
 
 AOl^n A0l9r 
 
 »055r aOi^OO 
 
 Aii6r Ai?on 
 
 «r?3 ao?6 
 
 a05* AOfl 
 
 A1 3fl Alai 
 
 AOPon 
 
 AOPe^n 
 
 Ai?Ar 
 
 AO?in 
 AoetP 
 
 A1350 
 
 A02PO 
 A0H7n 
 DI 
 
 A032U 
 AObVU 
 P-OIO 
 
 A03r 
 
 A Of 3 
 AI "? 
 
 A031 
 A065 
 A153 
 
 A036 
 A067 
 A155 
 
 A037 
 A103 
 A2C0 
 
 I f VFl.s 
 
 I f V F I r 
 
 L E \ F L = 
 I E Vf I = 
 
 I E V r I = 
 1 F vri « 
 I E V r I s 
 I EVf I = 
 I f \/M = 
 I t V f L = 
 
 It 
 
 9b 
 
 I E \ K = K ' 
 
 A007 
 A057 
 A1?7 
 Ari)3 
 A120 
 A071 
 A07? 
 A10«5 
 Af'93 
 A09fi 
 A017 
 
 Ar3f 
 
 tOOl 
 A09S 
 P-0^ ] 
 
 A c ? r, I 
 
 A 1 ?i I 
 
 ACt^ 
 
 Alio 
 ACIDS' 
 
 AU7"> 
 A 9 1 
 
 A C 3 3 
 
 A^<i^ 
 A( 1 »-. 
 
 AU c 
 F-1.2I 
 
 f( ?n 
 
 Arh6T 
 A 1 J M 
 
 AOIf 
 
 A 0^1 
 
 n f r 
 
 A(l7( 
 
 A ( p r 
 A (' 9 y 
 
 A r 7 <■■ 
 
 A1 07 
 
 A n ? ? I 
 ArP7T 
 r-01 I 
 
 A01 1 
 
 A07' 
 A on 
 
 f (U P 
 
 An3i 
 A n ■» 
 
 >--( 31 
 A03?T 
 A OJ^PT 
 
 Ar?« A095 A0?7 
 
 Af.68 a07iS A117 
 
 A0?0 A0«1 A05l 
 Al?l A12S A126 
 
 AC7« 
 
 A09C 
 
 «(i99 
 if 39 
 A1?3 
 A CO? I 
 Af 35T 
 
 fl077 A07H 
 
 A 1 nft 
 A <i ': 
 Al^V 
 
 A /' I 
 
 A019 
 AI Si 
 AO(<t I 
 AOt?! 
 
 A07V 
 
 A0Ot>I 
 AC be I 
 
 AOP? 
 
 i0b9 
 
 AOl 6 T 
 A05M 
 
 Al?b 
 
 A 1 1 I A U' 1 I A 1 P I A 1 1 «^ I A 1 1 M 
 
 AUP" 
 
 A0191 
 AOfcOI 
 AUOI 
 
 I [ f f F r I- « c . A c, F = 
 
 ATI <4 
 Allb 
 
 A 1 '1 
 A lit 
 
 ^f S3 
 M 19 
 
 A'lPl 
 AI 3(1 
 
 AI 31 
 
 A('97 
 A 133 
 
 i( 98 
 f 1 3" 
 
 AlO? 
 A136 
 
 AI 1 1 
 A137 
 
 k\ l<i 
 A13V 
 
 I lit 'to f t-f I I &T C h l-l 4|. i.tl Ol St-- 
 
 f CI'- 
 r U ? 
 iOl 'I 
 (. 1 3 'y 
 Kib 3 
 ' f. Vf 
 
 i ov/ 
 
 f 13^ 
 Mil 
 
 f. (JVC 
 ; C^ ' 
 M U 
 M 33 
 M j'l 
 
 AHS 
 
 All 'J 
 Alio 
 Al 37 
 Al IM 
 M 31 
 
 /■ 01 i 
 n 1 'J 
 f (M "^ 
 A01S 
 
 tPPi 
 
 I (I*' 7 
 -.008 
 
 .. ir? 
 
 Mil 
 Mil 
 Mil 
 Mil 
 AIM 
 MIS 
 A 11 M 
 
 »n« 
 
 A119 
 
 Al 30 
 
79 
 
 APPENDIX E. LISTINGS OF CUBD/REDUCE 
 
 E-2 
 
 A SAMPLE LISTING OF THE MEMBER OF LOOPED PACKAGES 
 AND ITS SOURCE DESTINATION LISTING OF CUBD/REDUCE 
 
 rH«u PACK*r,f ICHK01 *ui« *ois ch^o? #o«>3 fH^03 «oei *o«6 *ov7 aovb 
 
 »10? All! AnC Am An3 An" Al3ft CHkO* All* Allb 
 
 fHKOS Allfl A119 CHrOf A137 
 
 IOI'PfD packagFi 7 rt-ff1 CHrr? chnos ruMOi r^NOb rUNOft ai3v 
 
 PACK/>r,K.r^ Noi ( r) mi rr s(it.rr« c mp of nrsTt ? 
 
 rt ST I 7 6 
 
 PAf^ ACf »f t-^^? f 1) ^( f.f «f||^ff1 ( Kn nr ntsTr P 
 
 S('i kr f I 
 rt ST I 
 
 FAf k /(,f rf t.f.C.^ f ?) li( p( Sni'CCr= ? KH OF ''EsTr ? 
 
 Sl'i'kr r I c fr 
 
 ni ST I 3 b 
 
 PACK/.(,f tr^.^rll r 3) tt a sfnccF* 3 kh nf rfsie o 
 
 SUlil-f II ? b ^ 
 
 'M ST I 
 
 nisT I ^ 
 
 PACMof «f I'NOf ( s) ^'l' fF Sfi'frfi 3 ^ f rr rfsTr i 
 
 SfMlpf f t 7 U I- 
 
 nfST » 3 
 
 p*fM(,E»A) J9 r ^) K' n sfl'^^r« i >t pf tfsTc « 
 
 SUl'KFl f 
 
 rfST I ? 3 a •• 
 
 TI^'F iSfO Tn CPTAIN THTS KFSlilTt 
 
 FhOfFSSPP TTFFI ( tiM'TFS 3« «FCni-rS, 
 
 1/P TIMfi tlMiTfS i'O tFrniTS, 
 
 !►' ? I IM.,TF t M SF ( fTS. 
 
80 
 
 APPENDIX F. LISTINGS OF CUBD/HSKEEP 
 F-1 
 A SAMPLE LEVEL ASSIGMENT LISTING FOR LOOPED PACKAGES OF CUBD/HSKEEP 
 
 SCURrF 
 
 CHN 
 
 N«RC 
 
 S« 0. N«Rf(i« 0»LVO»l»LVL« 
 
 OtSTUATIr^ N*f<CS« 2. fJAWrPr ?.LVO»l»LVl 
 
 P»CHAf,{ 
 
 SCMIhrE 
 
 fhtgO? 
 
 NARCSb 0» KAl^rpr 0»LVD«1»LVL» 
 
 rtSTlKAMCf" K'AfCS* 0. NAKrn« 0»H'0«1»LVL« 
 
 N*RfSc ?. MHrr= 2»Lvn»i»LVL = 
 
 PATKAOE 
 
 srnHrF 
 
 r ^ 
 
 Pf ST U AT TP'^ NABfS« 2, NARrps ?.LV0e1.LVI« 
 
 PACKAGE fHNC« , ... 
 
 siui-rf MAPrs= 3, N«Krn= 3.H'D«i kLvi « * 
 
 ? 5 6 
 
 rt 5^TI^ AT I(iN N»firS= 0. KARrpa O.LVpe1»LVl» C 
 
 ?fff>fl"^ '"*"lsi?SrSc 1, NARfUs I.IVO.I.LVI' ? 
 
 PtSTUAITfN KARfSr t. NARCn= 1 . 1. vQs 1 , t V I a ? 
 
 ^fiCtsff 
 
 '"^(!l86cS« 3. NAwrr= 3.LV[le1 .I.Vl « 3 
 
 ? 'I ^ 
 
 P^STl^ATTf^ H«RfS= 1. NfwfPs 1 » L>'n= 1 > I VI e 1 
 
 rE?.iUAntN NABcs= t 
 ? 
 
 PACK«GK 
 
 , ^ARrpx 
 
 i»n.p=i 
 
 .1 VL = 
 
 1 
 
 , N A k r P s 
 3 
 
 f l^ 1 1 V 1 
 
 f I AG 
 
 ,LVL = 
 
 3 
 
 FkP LvI 
 
 Ct-f 01 
 
 A139 
 Ct'K03 
 
 c^•^ OS 
 
 ChKOA 
 
 C^^l/<t 
 
 
 
 
 
 
 
 1 
 ? 
 
 2 
 3 
 
 « 
 
 BKWL. LVL FLAG 
 
 bKWL IVL 
 
 4t 
 C 
 3 
 2 
 i 
 
 y 
 c 
 
81 
 
 APPENDIX F. LISTINGS OF CUBD/HSKEEP 
 
 F-2 
 
 A SAMPLE FINAL LEVEL ASSIGNMENT LISTING OF CUBD/HSKEEP 
 
 FU*1 IFVFl «SSI&NMFKT LIST fll Bn»Rn»TniSP 
 
 IFVtl- 
 
 
 
 AOu;n 
 
 A003r> 
 
 AOO«n 
 
 »0l 5p 
 
 *oi«n 
 
 «oi9n 
 
 AOZon 
 
 AbZlp 
 
 Ab220 
 
 A03?n 
 
 
 
 *03bn 
 
 »o«or 
 
 A0«5P 
 
 A050P 
 
 *055fi 
 
 AC60n 
 
 AOeMi 
 
 Aoe6r 
 
 A0A70 
 
 A0*9P 
 
 
 
 Aioin 
 
 Aio«n 
 
 A10«P 
 
 AllJr 
 
 «ii6n 
 
 »J20p 
 
 A124n 
 
 AU&O 
 
 UI 
 
 P-OIO 
 
 
 
 M-ozn 
 
 F-03M 
 
 p-o«n 
 
 p-05r 
 
 
 
 
 
 
 
 IFVFl. 
 
 J 
 
 »P06 
 
 AOfiS 
 
 API? 
 
 A013 
 
 A023 
 
 An?6 
 
 A030 
 
 Abil 
 
 tvit 
 
 AU37 
 
 
 
 *C«2 
 
 A0«* 
 
 A0A7 
 
 A0S7 
 
 A05H 
 
 A061 
 
 A063 
 
 AC6!i 
 
 *o«r 
 
 AlOJ 
 
 
 
 AIOV 
 
 AlUl 
 
 Al?? 
 
 A 13? 
 
 A13e 
 
 A141 
 
 Al4? 
 
 Alb3 
 
 Al^!> 
 
 A^OO 
 
 l(VFI« 
 
 ? 
 
 *oo^ 
 
 AOCfl 
 
 API () 
 
 Aon 
 
 A0?4 
 
 A02S 
 
 A027 
 
 AO<!tl 
 
 AU4t 
 
 AOSl 
 
 
 
 *Pi/ 
 
 AOf^ 
 
 AOAA 
 
 A06* 
 
 AOA« 
 
 A076 
 
 An7 
 
 A121 
 
 Al?b 
 
 A176 
 
 
 
 »i?^ 
 
 Alio 
 
 fdf F 
 
 
 
 
 
 
 
 
 I » VFl» 
 
 3 
 
 »P«3 
 «t29 
 
 A060 
 
 AP70 
 
 A073 
 
 A074 
 
 A077 
 
 AU78 
 
 A07V 
 
 AUA2 
 
 At?e 
 
 1 FVFl I 
 
 « 
 
 »on 
 
 «07b 
 
 AOftC 
 
 A0»3 
 
 A090 
 
 
 
 
 
 
 If vri < 
 
 •3 
 
 A072 
 
 A0«1 
 
 AP9? 
 
 
 
 
 
 
 
 
 If VFl « 
 
 bo 
 
 «C14 
 
 A015 
 
 APb3 
 
 
 
 
 
 
 
 
 1 (vri ■ 
 
 51 
 
 *13« 
 
 
 
 
 
 
 
 
 
 
 1 (VF| • 
 
 f>J 
 
 *t36 
 
 AOVft 
 AllH 
 
 AP97 
 AllV 
 
 A09*> 
 
 Ain? 
 
 Atn 
 
 A130 
 
 A131 
 
 A133 
 
 A134 
 
 1 (^Fl ■ 
 
 ^3 
 
 *137 
 
 
 
 
 
 
 
 
 
 
 If \ri* 
 
 Sll 
 
 Al 14 
 
 AllS 
 
 
 
 
 
 
 
 
 
 IE vri « 
 
 ^« 
 
 A105 
 
 
 
 
 
 
 
 
 
 
 1 IVFl ■ 
 
 <;b 
 
 Arv3 
 
 
 
 
 
 
 
 
 
 
 1 EVFL« 
 
 «6 
 
 A0«4 
 
 
 
 
 
 
 
 
 
 
 If VFl ■ 
 
 97 
 
 AOW 
 
 A (-3 3 
 
 
 
 
 
 
 
 
 
 If VFl « 
 
 ?h 
 
 A0 3e 
 
 A (1 '1 X 
 
 A()«>B 
 
 AO»e 
 
 A099 
 
 AlOA 
 
 
 
 
 
 lEVFlt. 
 
 ev 
 
 AOOl 
 
 AOIH 
 
 AP?» 
 
 A03« 
 
 A039 
 
 A0«4 
 
 A049 
 
 AOi« 
 
 4U5V 
 
 r.OHU 
 
 
 
 AOVb 
 
 Alf 
 
 A107 
 
 AM} 
 
 A123 
 
 A15? 
 
 Al5« 
 
 
 
 
 ItVFt.tf 
 
 P-Ob) 
 
 ^•r>?^ 
 
 F-04I 
 
 F»03t 
 
 AOP?I 
 
 A003t^ 
 
 A004I 
 
 (0051 
 
 Abl61 
 
 oOlVl 
 
 
 
 AP^'OI 
 
 r()?n 
 
 AP??I 
 
 A03JI 
 
 A035I 
 
 AP«OI 
 
 aO«5I 
 
 ACbOI 
 
 AUSbl 
 
 AO^OI 
 
 
 
 Arfcbl 
 
 Allt**! 
 
 ArH7I 
 
 A0fi9l 
 
 AlPlI 
 
 AlbAT 
 
 AlOPI 
 
 Allii 
 
 Aiiei 
 
 Al?OI 
 
 
 
 A1<>41 
 
 AISSI 
 
 H-01 t 
 
 
 
 
 
 
 
 
 Tl^-t liSlr T(l rpTAlN Thl« hf SUI Tl 
 
 FKOCFSSPti II>'tt P I lUiTFS 4 ^fCPKPS, 
 
 I/n TIMFl r I^liTFJ 1? SFfP»>'rS» 
 
 IN ■■ il^llTFS 41 ^FlPKTSi 
 
 P*Tfi UPMlAYi 1/ S/7P» M?« P).i, 
 
82 
 
 APPEKDIX G. LISTINGS OF CUBD/SIMGEN 
 G-1 
 A SAMPLE SIMULATOR BODY LISTING OF CUBD/SIMGEN 
 
 OEMPTV ♦ NnT(Ctl89J *■ (C[099J ANO Ct063] AND Cn69] AND CtlB31))J 00567300 
 
 Ctl92l ♦ NOT(C[195J ♦ {Ctl901 AnD Ctuej AND CtlSn AND Cf$551))l 00567400 
 
 V[000]*Cll931)Yr00l]»C[19?]»Yt0021«-Ctl«?JI 00567500 
 
 FOR J*P SirP 1 UNTIL ? DO BEGIN 00567600 
 
 TFHP*REAL(NOT Z[l3#Jl FOV YtJJ)l 00567700 
 
 IF TFMP K'EO OR TFHP.tllB] MEO THEN BEGIN 00567600 
 
 STABLE*FALSE| Z[ 1 3# J]«-Yr J) JFNDiENpi 00567900 
 
 t 00566000 
 
 % COMMENT LFVFL« 52 Al 36( P IL022 ) i 00566100 
 
 C[122] «• NnT(Ctl23] ♦ (AC0151 AND WTRUF AND VTRllE AND VTPUE))! 00568200 
 
 OEP'PTY 4- NrT(Ctl7n ♦ (CtC67] AMD Cri73] AND VTRuE AND VTRUE))j 00566300 
 
 Yt0001*Ctl7njYt00n«-Ct 123] «Yt0021«-Ctl221J 00566400 
 
 FOR J*0 STEP 1 LiNTIL ? DO PFGIN 0056^500 
 
 TFMP4-REAL(N0T Ztl«»J] FOV Y[J])i 00568600 
 
 ir TEMP KEO OR TEMp.rilP] NEC THEM HEr.JN 00566700 
 
 STABLF«-FALSE> Z r 1 1 » J)«-Y t J ) I END) F NT J 00568600 
 
 f 00568900 
 
 t COMMENT LEVEL* 52 AHPCDUOU)) 00569000 
 
 OEMPTY «• MPT(f[199] «• (CC203] AkO Cmi]) HP (fr204l AKP VTRUf));^ O0569J00 
 
 PEMPTY ♦ NPT(fr346] *■ ( VTRI'E AkP A[014]) PR (Crll61 AWP Cr219]))| 005a9?00 
 
 YtOOO]«-Ct 346])Y[00l3*Ct 199] > 0056V300 
 
 FIR J«-0 STEP 1 UNTIL 1 PO PFGIK 00569400 
 
 TFMH«-fiEAt (^'0T Z[lb#J] FOV Y[J])I 00569500 
 
 IF TFf'P NFO OR TEMp.rliS] MEO THEN BFGJN 00569600 
 
 STABLF«-EALSEJ Z [ 1 5* J ]<-Yt J Ji ENP; E^P) 00569700 
 
 » 00569800 
 
 % CIMMEkT LFVFLs 5? AJ 19(PTlO??)) 00569900 
 
 C[?00] ♦• KPT(fr20n *■ (r[199] AMD CfOCT] ANP VTRuE ANP VTRUE))| 00570000 
 
 OEKPTY ♦ NPT(Cr?04] «. (CtP99] AK'D Cr?20] ANP cr?0?] ANP Crl30])); 0057010C 
 
 Yl0C0]«-C[?041)Yf00l]«-Cr201 ] I Y [ Op? ] ♦ C [ 2P0 ] I 00570200 
 
 FOR J«-0 STFP 1 UNTIL 2 PO PF6TN 00570300 
 
 TFMP«.PtAI (NOT Z[16*Jl FOV Y[J]H 00570400 
 
 IF TF^-P NFO PR TFMp.CltSl Nf THFM HFGTN 0057G500 
 
 STaBLF^FALSEJ Zrlf »J]«-Yt J];FNn;FMn> 00570600 
 
 FNP» IF I f,FO 30 THfN wR I TF ( PR I K'TER. T I Mf PVFP # 52 ) I 00570700 
 
 FNPj PEGIK Off INF NPNEeTRuktl 00570800 
 
 I«-0) K><ILF (I*I*n ISS 30 A^P MPT <;7ARIE PR I LEO ? PP 00570900 
 
 Bfr,lN <TAPLE IbTRUF) 00571000 
 
 » 00571100 
 
 > COMMtKT IFVFL. 53 A 1 37 ( P 1 1 OPi" ) J 00571200 
 
 C[1t<7] «• NPKPFMPTY ♦■ (C[19?] AND Cr09«1 ANP A[P2n ANP VTKUE))! 00571300 
 
 CCP94] » KnT(frP95] ♦■ (r[131] A^D Cr220l AND VTRuE ANP Cr3fl03))l 00571400 
 
 Y[roo]«-cro95]rYropi)*rro94i;Y[oo2i«-rrie7]i oo57i5oo 
 
 Ftp J*r STEP 1 OMTIl 2 Pn HFGTN 00571600 
 
 TFKP«-fEAl (^OT ?{17,J] FOV V[J1)) 00571700 
 
 IF TFMP MFC OR TFMp.ritPl M.O THEM HFGlN 00571B00 
 
 STaBi F»F»LSEJ 7f 1 7* J]«-V[ ji)F Nr)>F^PI 00571900 
 
 FNPJ TF I GfO 30 THEN wP T TF r PP I ^TER . T I MFPVF b»53 ) ; 00572000 
 
 ENP; PEGU OFF INF NPNEeTPliE** 00572100 
 
 I«-0| VH'ILF (Ul + 1) I SS 30 AfP NfiT «TAF.IF OP I IFO 2 op 00572200 
 
 Btr.IN flAPl F leTRlF) 00572300 
 
 » 00572400 
 
 i CPMKFM IFVFL* 54 Al 14((!ll 01 n; 00572500 
 
 PFK'PTV «• KrT{rrl2l) «■ (rt35''l A^P ''TPI^F ) Vh (Ar0l3l ANO VTRUE))j 00572fc00 
 
 Ptt-FTY «■ NPT(ffl65] «■ ( VtRI'F A^P tri70]) np ( WTHUF AK'O CCP95]))| 00572700 
 
 Y[P(0]«-C[Ub)iYrOPn«-rfl2ni 0057?600 
 
 FCJP J«-r STFP 1 bNTll 1 pn OFf.lM 00572900 
 
 lFNP»PtAI (^OT 2rie#Jl FOV Y[J])I 00573000 
 
 IF TF^'P t^FP PR TLMp.rilPl NF THEN' PEGTN 00573100 
 
 STAbl F*EAl SE) Z t 1 P » J ] * Y r J 1 J END > E ►T ; 00573200 
 
 f 00573300 
 
83 
 
 COMMENT LFVrL* 54 AU5(DllO?2)J . , , . 
 
 OtMPTY «• NPT(Ctl70) ♦ (CI099) A^O Cfl2n AND Ctl3l] ANn 
 Ctl66] «• NnT(Crl67] <• (Ctl65) A^D VTRUE ANP Ct09l] ANP 
 Y(OOO)*Ctl67)JYtO0l)«-cri66]IYr00?3<-C[iron 
 FOP J*0 STFP 1 UNTIL 2 DO BFGIN 
 TFMP^fJEAKNOT Ztl9*J] FOV YtJl); 
 IF TFMP NFO OR TEMp.rii«l NEO THEN BF6TN 
 STABLF*FAISE) 7 t 19* Jl^Yf JllFNOIENDl 
 ENDl IF T GEO 30 THEN WR ITFf PPINTFP#TIME0VFP#54 )l 
 ND) PEGU DFFINE NnNE»TRUF«l 
 
 COMMENT LFVEL« 94 Al 05(DIl 022) I 
 CtlftS) * NPT(crH6J ♦ {Ct099) AkD Cr202] ANP Cn68] ANP 
 OEMPTY «• NPT(crl5Pl ♦ (CtOftSl AkO Cfl30] ANP Ct2l9] ANP 
 
 C[2l9J))) 
 VTRllF))j 
 
 VTRUE))! 
 VTRUE))! 
 
 COMMENT LFVFLi 
 CtP5fl] «■ 
 rro62) * 
 CtC66] «. 
 C[2in ♦ 
 
 COMMENT 
 f(070] 4. 
 Ct210] «■ 
 
 LFVFLs 
 Ct06f 
 
 cr2ii 
 
 Ct'MMENT LFVFL« 
 OEt"PTY ♦ NrT(f[096 
 CC2C8] *■ ^rT(Cf?09 
 
 CtiMMthT LFVFL« 
 
 OtMPTY «• NrT(rro33 
 Pf^-PTY «• NOKrrair 
 
 COMMENT LFV'FLe 
 PEMPTY <■ NrT(C[345 
 
 PEMFTY «■ ^nT(rr344 
 
 CCMKENT LFVFLs 
 PEMFTY ♦ KPT(rr34? 
 PEf'PTY ♦ KPT(r[34r 
 
 CIMMEnT LFVELx 
 PFKFTY «• NPT(rr339 
 PEKPTY «• NPTfCr337 
 
 CPMMENT LFVFLr 
 OEMPTY *■ NrTfrr04S 
 
 PE.^pTY «. NrT(rro7fl 
 CL'M^t^^ lmtl* 
 
 PE^PTY *■ Nf 1 (r r5P5 
 
 PE^'PTY «• NnT(rr?i/i 
 
 Cl'MMM |.FVFL« 
 
 PF^pTy ♦ KfTccrib? 
 
 COMMEM LfVFL« 
 
 rc?753 «• hrT(fr?7(^ 
 
 f.C?73) 4. NPT(fr?74 
 
 95 
 
 96 
 
 ; 
 
 ! 
 
 A093(PI| 0P7)! 
 CC06P) And Ctl45] 
 
 ccob") And cri45] 
 
 C(068] ArD C[145] 
 Ct2l3) AkD C[145) 
 
 A090(PI| Dl Y)! 
 
 97 A017(PT|0in! 
 
 *■ {C[09'>] A^P VTMiF ) 
 *■ ( VTRIT AKD FAl ?F) 
 
 97 AP33(P1I 0?7)i 
 
 «• C[0341 «■ rro35] 
 *■ Cr34P) ♦ CC3491 
 
 96 AC3PCPllOini 
 
 ♦ ( VTRl'F AfP C[033n 
 «■ (r[3a7] A^D Cr329]) 
 
 98 AP«8(PI| 01 1 )) 
 
 *■ ( VTHUF AKP Cr034]) 
 *■ (C[3aP] A^P C(343l) 
 
 (IF- 
 PR 
 
 (f rioi ] 
 
 f \/TRUF 
 
 AMP 
 ANP 
 
 VTRUE))J 
 CC2101))! 
 
 rr i6p] 
 
 Cr2l9) 
 
 ANP 
 ANP 
 
 Crl31 D! 
 
 criP4]); 
 
 Of 
 PR 
 
 OR 
 OR 
 
 { VTPUF 
 {Cr033l 
 
 (rr34i 1 
 (rt034i 
 
 AMP 
 AND 
 
 Ct^«7]))t 
 VtRUF)) 
 
 AMP rr.i'*8i)) 
 
 ANH VtNUF)) 
 
 98 AObP(PI| 0115! 
 
 «■ ( VTRDF AkD Cr035l) np (rr3361 A*.D rt?*9])) 
 
 ♦ (f(340) AK'P C[33«)) PR (Cr035l ANP VtRUF)) 
 
 96 APftftCPTl Oil)! 
 
 ♦ (CtC7P1 A^P VTRl'F) OR (rrl46l ANP VtRUF)) 
 «■ { VTHi F A^^ cri?4)) PF (rr220i ANP rtfi72))) 
 
 Vfl Af9O(pli0in) 
 
 ♦ (cf??n akp rr?09i) oR (rr2??i 
 
 ♦ (rtpopi AhP f,r?iP]) OR (fr209i 
 
 AMP rt?08))) 
 AMP Ct217l)) 
 
 96 AlOf f Pll 0P«1! 
 
 «• (ctiais] AKD \'TRiir) OR (("risoi anp vtruf) or 
 
 f([i?'n A»n cr25ai) or (Cf07?i amp rti7i]))*7 
 
 9 9 ACOHPll 0??)! 
 
 *■ (C[l?fl1 A^P VTFHF A^P VTRllE ANP fr0f7)))! 
 
 «■ (C[0671 AfP Cri?<il AMP VTRUF ANP VTRUE))! 
 
 00573400 
 00573500 
 00573600 
 00573700 
 00573800 
 00573900 
 00574000 
 00574100 
 00574200 
 00574300 
 00574400 
 00574b00 
 00574600 
 00574700 
 00574600 
 00574900 
 00575000 
 00575100 
 00575200 
 00575300 
 00575400 
 00575500 
 00575600 
 00575700 
 00575600 
 00575900 
 00576COO 
 00576100 
 00576^00 
 00576300 
 00576400 
 00576500 
 00576600 
 00576^00 
 00576600 
 00576900 
 00577000 
 00577100 
 00577^00 
 00577300 
 UO577400 
 0057^500 
 00577600 
 00577700 
 00577600 
 00577900 
 00576000 
 00576100 
 00576200 
 00576300 
 00576ii00 
 00576500 
 00576600 
 00578700 
 00576600 
 00576900 
 00579000 
 0057"100 
 P0579200 
 00579300 
 00579400 
 
APPENDIX G. LISTINGS OF CUBD/SIMGEN 
 G-2 
 A SAMPLE TOTAL SIGNAL NAME LISTING OF CUBD/SIMGEN 
 
 8i+ 
 
 ISM'T <IOPJ«l N»*>[ list (:!■ l(Ukr«TlI<.( 
 
 Af'fttV HAffmUfX*} 
 
 31 
 
 CLi.-----fO 
 T-«| I...<1 
 
 T-TPIH3-I 3 
 
 I 
 
 CI ►- ri 
 
 T-f CI---I I 
 T-Pf f FO-I (1 
 T'VU *"S) 
 
 I en-,..... 
 
 T.f k.pf yr ) 
 
 i-Pf T---r 1 
 
 irr-?----- in«li-f--- 
 
 l-SXl h--r.t T-Tl-f-Sl 
 
 5 
 
 LU»ri-?..-- 
 T-INIT.-I 1 
 T-T(iI5(>-l3 
 
 H,-l 
 
 1-KS«---I 1 
 1-TI-I6( -I J 
 
 ir-i-"--- II,-?------ 
 
 1-HKH.M 1-I-MJS5-03 
 l-Ti.161-1-3 1-1H6S-I 3 
 
 rul'M ) <ir,ni nn MM ru .r noi rTr I tp »(-h«v nif.tfjxyj 
 
 1 
 
 lUI -l-.--- 
 
 M t-3«--'^r> 
 
 T-H If (I. I ? 
 
 T-> 5,.fi..rMi 
 1-kf M -•"! 
 1 -iri-po-i- 1 
 
 1, r-,. 
 
 TrP-3«--: I 
 
 Tf p-i.r--i 1 
 l.ri.1 -..I 1 
 I - > f H t- • - r ft 
 T-rJKf'.rl 
 ! . T f 1. 1 . . 1 
 
 tF p.lp.-F 
 T F F - •> J - - 1 (I 
 1-1 • 1 l--r I 
 T-k sr ( .-( 1 
 
 1 -Tl Hjft-i 1 
 
 F-A-;'------ 
 
 Tf f.1H--pl 
 TF P-«.*--P 1 
 
 T-irp---ri 
 ■t-n,! c--r>3 
 T-pF'«s*-rl 
 
 1-1f'F-U7-F I 
 
 F-n-i------ 
 
 TFP-3r--pn 
 Trp-tP'-bo 
 
 T-l'SP»--00 
 T-M^F C-.C5 
 T-pr T---|]| 
 TS-I-- 
 
 MD-? - 
 
 TrR-3c--r-i 
 
 irB-?ip--F'i 
 
 T-MSf»--(.'2 
 T-«SHC--(>? 
 
 T-^ni>r--r,i 
 IS-? 
 
 t-S-l------ 
 
 U K-3U--I0 
 
 1-MSb*--lnl 
 1-HSH)--01 
 
 I s- 
 
 IF (■-3L--I I 
 UF'-''t.--i 1 
 l-> Sl>---( ( 
 1-kSi I --r i 
 l-U.i-l I -I 1 
 
 1«-| 
 
 1FF>-'A--| I 
 Uh-M --t (. 
 
 I-F t. r •-( !i 
 I-li 1 IJ-i 1 
 
 1»-7------ 
 
 TrF^-«B--i 1 
 
 n h-Ml--! 1 
 l-^S(-n--l ? 
 
 1-F SF C--C 7 
 1-TI F-03-F 1 
 
 IMFINJI ^ir.'Al NAlt II^T fll F'f nH'.lr I.St^ «fF:»Y F A I'f e f ( « > » ; 
 
 ;;' 
 
 T • 7 r 1. r /i - ■ 1 
 , hr 1 i"i>.-i ( 
 
 i.FTl 1.P--V3 
 
 l-Il 1 (!■;-. 1 
 
 „l.tl F |i.-1 il 
 
 ,,l,fl,kl,..^(l 
 
 T-TPtOf -c t 
 
 , K'lii n-.i •> 
 
 , Hpl.* Fi--'5>. 
 
 
 f kc f r---l 
 
 (.F/PHF 1'---? 
 
 , HF „F l'--.3 
 
 
 1 F r 1 1 Fir «r j 
 
 l-t MF 0-1 1 
 
 IF riF I-F AT". 
 !-• 1 If f ^M 
 
 •-M T-.-. (1 
 T-1'IT( l-t 1 
 
 
 1 - 1- 1 1 F 3 - r. 1 
 T-' Mf "i-l 1 
 
 T - r M - • I ri 
 
 I-l 1 1-- .rl 
 
 1-1 MF 1-1 1 
 
 '-1 niA-i I 
 
 1 - F: I T . . k , 1 
 
 
 T-r «F<B»?i 1 
 
 T-l «, Hl'rr.fl 
 
 l-rl .C{--1 
 
 T-r^4 PFF f 1 
 
 
 I - F • 1 (I () - r, t 
 
 l.i 1 Fbr-( 1 
 
 1 - F > I- S 1 - ( 1 
 
 
 1-F F |.S9-rl 
 
 i-I»SrTrr.i 
 1-1. t| [ .-r 7 
 
 I-r F 1-K--I 1 
 
 1 - 1 f 1 - 1 - F t 
 
 1 - M s I - • . ( r 
 
 1-FI F A.3-r 1 
 1-1 F P-?-F 1 
 ,-F SI ---( 1 
 
 
 l-f r irM« 1 
 
 T-l f trl-l 1 
 
 l-rAi-cT-i y 
 
 T-PACF TPt I 
 T-PAF;m Cf t 
 
 
 1 - F I I 1 T - - 1 
 
 I-tf-.F .r,) 
 
 T-ti, ---^CO 
 
 ?i 1 
 
 i-<.i 1 nr-ri 
 
 T « F 1 V A - <-, 1 
 
 l-H .-.,r 1 
 1 . '. ( F 1 r <. r 1 
 T . « F. 1. V F - r 1 
 
 1 -Cl •.•.! 1 
 
 1 -<> F n -r 1 
 i-'i-l tf -r 1 
 
 ? 1 1 
 
 TT»--.^r, 1 
 l-TK.fl?F f.l 
 
 T-l FijCI F r 1 
 T-TH(.r?.r.n 
 
 T - 1 1 (. p 1 . r r 
 T-Ti r.P?.rl 
 
 ?M 
 
 T-Tri.nr-r.1 
 
 T-ir K03-I 1 
 
 l-TtiHCf-l 1 
 I-Tl |.(i«.('l 
 
 T-Ti.ini-r 1 
 i-Tf-tpt-ri 
 
 ?«-l 
 
 l-TPK07-ri 
 
 I-TIC07-f 1 
 
 T-i( cri7-i ) 
 
 ?7I 
 
 ?P1 
 
 T-Tr----r,l 
 
 T-1F ( 03-r 1 
 T-TF t--lir.l 
 
 T-TF cor-r 1 
 T-TKl'3-r.1 
 T-Tf r--i'r? 
 
 T-TF roi. -r 1 
 1-TF re j-i 1 
 T-TF r--»ri 
 
 l-Trit07-r1 
 
 ( unt Ci.-ift 
 
 f fcPlik D--?* 
 r.PPli" li.-.n 
 T-Al T---W1 
 
 T-pin 1-1 n 
 T-i-nr 3Sf 1 
 
 1-rlTFf-i 
 T-plT-.i.r.',' 
 
 T-ri V 17--I 
 
 T-r^rdpKrd 
 l-Fi'Fi?-ri 
 T - F F' T B I « r P 
 T - 1 f r - . - r, 1 
 
 T-Fl. -.-p? 
 T-PAPHTF r? 
 T-PAfFf-PF ) 
 T-F A--.>r1 
 
 \.f, -i.-r I 
 T-cr roF fcr.i 
 T-cpi vi>-r.i 
 
 T-TFPOIKf 1 
 T-TFr07-l n 
 T-TPI dl-Pt 
 T-TPtou-l 1 
 T-THl---hf 
 T-TF r(JO-l 1 
 1 - T F r - p 1 
 T-TF cCPFfP 
 
 TS-I------ 
 
 TS-? 
 
 (.Lr----1,( 1 
 
 .Kll M --1 U 
 
 i.hLli' 1 •• 1 1 
 
 f F.(.l'F.O--l? 
 
 pppin n--i7 
 
 r,RpiiF.o--iP 
 
 1 f<ljliM0--19 
 
 ,KUiM --;(• 
 
 1 hLil'l l.--i 1 
 
 I.PtllF U--i? 
 
 'PPiiF n--?7 
 
 P,ROU'.0--^» 
 
 ( HUlU0--^9 
 
 .Mbl F11--1L 
 
 i.hl.c 1 1 •- Jl 
 
 c>( liH)--3? 
 
 pfiPi Nn---s 
 
 (,RriiNn---f 
 
 l,HUliK0---7 
 
 .KUl.F b " 
 
 oKLl ^ 1---9 
 
 Tf CIF !<( !.( 1 
 
 T-AI T---hO 
 
 T-Al T — -I-l 
 
 I-bUU»TAl 
 
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86 
 
 APIENDIX H 
 
 A SAMPLE OUTRJT LISTING OF <BOAKD NAME>/ SIMULA 
 
 ILLIAC IV CONTROL UNIT CARD LOGIC SIMULATOR 
 
 TOFUND SIMULATOR VFRSIUN 1 
 
 SnUJLATinN NliMFER 9 fONDAV.- l/05/70# 9l«9 PM 
 
 SIMUl ATCR HlfTORYt 
 
 PRt.GHAM 
 
 MM LI ST 
 CUhnAHD/llPnATF 
 CUROARO/wfnTRl 
 CURPAPD/wf DTP? 
 ClIBOARD/LF VFLFR 
 tUBPAPD/RFOliCF 
 CUBPARO/HSKf FP 
 CURPAPD/SIHGFn 
 
 DATE AND TIhF RIIN 
 
 fl/0e/«9, 1?|00 AM 
 10/17/69, 2|?3 pM 
 
 10/17/69, 
 10/17/6V, 
 10/17/69, 
 10/17/69, 
 10/17/69, 
 10/J7/6V, 
 
 ?l?4 pM 
 
 2l?6 pM 
 
 2l?7 pM 
 
 2l?7 pM 
 
 2128 pM 
 
 2j28 PM 
 
 RUN f 
 
 LATEST 
 
 SIK'llATlllK Cn^TF^nlLfD FY IFSiA PPHGRAM NiiMpER 10 cRMTED 11/09/69, llibb AM 
 
SIMULATIPN LOG 
 
 87 
 
 I 
 
 STEP NUMBrR 
 
 STrP LABFLrO 
 
 I 
 
 STFPOl 
 
 2 
 
 STrP02 
 
 3 
 
 STFPOS 
 
 4 
 
 STFP04 
 
 5 
 
 STFP05 
 
 6 
 
 STFP06 
 
 7 
 
 STrP07 
 
 8 
 
 STFPOP 
 
 9 
 
 STFP09 
 
 10 
 
 STFPIO 
 
 11 
 
 STFPll 
 
 12 
 
 STFPl? 
 
 13 
 
 STFP13 
 
 14 
 
 STFP14 
 
 15 
 
 STFP15 
 
 16 
 
 STFP16 
 
88 
 
 CPU TIMF USFD » MiN 3 STC 
 
 I/n TIMr USED ■ MiKt 13 SEC 
 
 TOTAL TIME USED ■ MiK' 12 SEC 
 
 16 STEPS SIMULATED AT 76 STEPS PEP MINUTE 
 
89 
 
 APIENDIX I 
 
 A PORTION OF M OUTHJT LISTING FROM CUBD/ PRINTER 
 
 SIMULATION STrP NUMBFP 10 — STEP LABELED "STE'r.'!!" 
 
 10. Oil 
 
 COMPf ACTUAL 00000000 00000000 000 (2> 
 
 FFl ArTUAL 00000000 00000000 (2> 
 
 TROt ACTUAL 00000000 11111111 (2) 
 
 TfiCt ACTUAL 00000000 (2) 
 
 10.021 
 
 COMPI ACTUAL 00000000 OOOOllll 000 (2) 
 
 FFl ArTUAL 00000000 00000000 (2) 
 
 TpOt ArTUAL 00000000 lUlllll (?) 
 
 TGtl ArTUAL OCOOOOOO (2) 
 
 10.C3I 
 
 COMPf ACTUAL 00000000 lUlOOOO 000 (2) 
 
 FFl ArTUAL OCOOOOOO 00000000 (2) 
 
 ThCJi ACTUAL 00000000 lUlllll (2) 
 
 TGtl ACTUAL OCOOOOOO (2) 
 10.04 1 
 
 ooMpi Actual oooooooo iiiniii oic (?) 
 
 FFl Actual oooooooo oooooooo r2) 
 
 TPOi Actual oooooooo iiiiini r2) 
 
 TG*-! Actual oooooooo (2) 
 
 lO.CSl 
 
 ccMPi Actual ooooiiii oooooooo ooo (?) 
 
 FFl actual OOOOllll OOOOOOOO (2> 
 
 TpU| ACTUAI ncOOllU lllllUl (2) 
 
 TGt| ACTUAL OOOOOOOO (2) 
 10,061 
 
 fOMPI ACTUAL OCOOnil OOOOllll 000 (?) 
 
 FFl ACTUAL OOOOllll OOOOOOOO (?) 
 
 TPUi ACTUAL OOOOllll lUlllll (2) 
 
90 
 
 SIMULATION STFP NUMBER 2 — STEP LABELED "STEP2" 
 
 ?.Olt 
 
 TROi ACTUAL 11111111 lUllUl (2) 
 
 COMPI ACTUAL 00000000 00000000 000 (2) 
 
 TGti ACTUAL 00000000 (2) 
 
 rn ACTUAL lUlltll 00000000 (2) 
 
 2.021 
 
 TROi ACTUAL UllUll llllllll (7) 
 
 COMPt ACTUAL 00000000 00001111 000 (2) 
 
 TGi'l ACTUAL 00000000 (?) 
 
 FFI ACTUAL llllllll 00000000 f2? 
 
 2.031 
 
 TPbi ACTUAL llllllll 11111111 (2^ 
 
 COHPI A'-TUAL 00000000 lUlOOOO 000 (2) 
 
 TGCt ACTUAL 00000000 (2) 
 
 FFI ArTUAL 11111U1 OOOOOOOO (2> 
 
 2,f4t 
 
 TptJt AcTllAl lllllin llllllll (2t 
 
 CCMPI ArTUAL OOOOOOOO llllllll OIC (2) 
 
 Tr,Ct ACTUAL OOOOOOOO (2) 
 
 FFI ACTUAL llllllll OOOOOOOO (2) 
 2.C5I 
 
 TPUt ArTUAL OOOOOOOO OOOOOOOO (2^ 
 
 COMPi ACTUAL OOOOllll OOOOOOOO 000 (2) 
 
 TgCi ACTUAL OOOOOOOO (2) 
 
 FFI ACTUAL llllllll OOOOOOOO (2^ 
 2.C6t 
 
 TRUl ACTUAL OOOOOOOO OOOOOOOO (2^ 
 
 CCHPl ACTUAL OOOOllll OOOOllll 000 (2) 
 
 TGti ACTUAL OOOOOOOO (2) 
 
91 
 
 LIST OF REFERENCES 
 
 [1] Abel, L.C, Tanaka, C "Proposal for Control Unit Board Logic Simulator 
 System." Diagnostic Group Memorandum (DM-O31) • Department of Com- 
 puter Science, University of Illinois, November I968. 
 
 [2] Allegre, N.G. "TESLA, A control Language for Logic Simulations of Digital 
 Circuits." Report No. 3^7* Department of Computer Science, Univer- 
 sity of Illinois, August 1969. 
 
 [3] Berge, C "Theory of Graphs and Its Applications." John Wiley & Sons, 
 Inc. 1962. 
 
 [k] Carroll, A.B., Kato, M., Koga, Y., Naemura, K. "A Method of Diagnostic 
 Test Generation." SJCC I969, pp 221-228. 
 
 [5] Harary, F., Norman, R.Z., Cartwright, D. "Structural Models: An Intro- 
 duction to the Theory of Directed Graphs." John Wiley & Sons, Inc. 
 1965. 
 
 [6J Kaufman, A. "Graphs, Dynamic Programming, and Finite Games." Academic 
 Press. 1967. 
 
 [7] Ramamoorthy, CV. "Analysis of Graphs by Connectivity Considerations." 
 JACM Vol. 13, No. 2, April I966, pp 211-222. 
 
 [8] Tanaka, C "Level Assignment Problem for Test Simulator Generator," 
 Diagnostic Group Memorandum (DM-035) ♦ Department of Computer 
 Science, University of Illinois, October I968. 
 
 [9j Abel, L.C, Naemura, K., Tanaka, C "Parallel Logic Simulator and its 
 Use for Test Generation." Workshop on Reliability and Maintain- 
 ability of Computer Systems at Lake of the Ozarks. October 1969* 
 
UNCLASSIFIED 
 
 S«curity CU»«ific«tion 
 
 DOCUMENT CONTROL DATA • R & D 
 
 (Sturitr elmflliemtlmt ot llllt, borfy o/ mbattmel mnd IndmmHit mmotmtlon mumi b0 mntmnd whan tff ovmrmll fport lu claa»IH»d) 
 
 I. OMICINATINO ACTIVITY fCofpor*(« author) 
 
 Department of Computer Science 
 
 University of Illinois at Urt ana- Champaign 
 
 Urbana, Illinois 6180I 
 
 2a. NEPONT SECUMITV C L A isi Fl C A TIOM 
 
 UNCLASSIFIED 
 
 2b. ONOUP 
 
 1. MCPOMT TITLE 
 
 PARALLEL SIMULATION OF DIGITAL SYSTEMS 
 
 4. DEScniPTivE NOTES C7>pa o/r«por( anrfinclualFa dalaaj 
 
 Research Report 
 
 t- AUTHON(S) (Flntnamf, mIMt* Initimt, Immt nmmm) 
 
 Chiyozi Tanaka 
 
 «. NEPONT DATE 
 
 April 30, 1970 
 
 7a. TOTAL NO. OF PACES 
 
 99 
 
 7b. NO. OF NEFS 
 
 M. CONTNACT ON SNANT NO. 
 
 USAF 30(602)-Ul44 
 
 b. PNOJECT NO. 
 
 46-26-15-305 
 
 •a. ONICINATOR'S NEPORT NUMBENO) 
 
 DCS Report No. 382 
 
 •b. OTHEN REPORT NO(SI (Any oCftar nuBtb«n that may ba aaalfnad 
 thia raport) 
 
 ILLIAC IV Document No. 211 
 
 10. DISTRIBUTION STATEMENT 
 
 Qualified requesters may obtain copies from DCS. 
 
 n. SUPPLEMENTARY NOTES 
 
 None 
 
 12. SPONSORING MILITARY ACTIVITY 
 
 Rome Air Development Center 
 Griffiss Air Force Base 
 Rome, New York 13^40 
 
 IS. ABSTRACT 
 
 The paper describes the method used to generate the parallel 
 simulator developed for the ILLIAC IV Project, University of Illinois. 
 The basic approach to achieve an efficient simulator system is parallel 
 logic simulation, package-level simulation, the use of a high level 
 language (ALGOL) and a flexible simulation control language (TESLA). This 
 paper analyzes the problems associated with the ideas and gives the algorithms 
 used to generate the simulator. Emphasis is placed on the algorithms and the 
 implementation of the simulator generator system. 
 
 DD '^'..1473 
 
 UHCLASSIFIED 
 
 Security Classification 
 
UNCLASSIFIED 
 
 Security Classification 
 
 KEY WORDS 
 
 logic design 
 logic simulator 
 design automation 
 diagnostics 
 diagnostic generation 
 ILLIAC IV 
 
 UNCLASSIFIED 
 
 Security Classification 
 
%^^ 
 
 ^9- 
 

^