LIBRARY OF THE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAICN 510.84 >3 CO Digitized by the Internet Archive in 2013 http://archive.org/details/computercircuits77leic UNIVERSITY OF ILLINOIS GRADUATE COLLEGE DIGITAL COMPUTER LABORATORY REPORT NO. 77 COMPUTER CIRCUITS WITH 30 MILLIMICROSECOND OPERATION TIMES by Gene H. Leichner and John L. Muerle February 6, 1957 This work was supported by the Atomic Energy Commission and the Office of Naval Research under AEC Contract AT(ll-l)-4l5 PREFACE This report is a part of the University of Illinois study program on a high speed computer. The report covers a set of circuits which may be said to he fairly conventional in type and are similar to many existing vacuum tube circuits. The circuits differ from their vacuum tube counterparts because of tolerances and emphasis on speed. Other circuits besides these are being worked on in the Laboratory. The circuits represented in this report are not necessarily intended to be final ones. Although fundamental building block circuits are described, other additional circuits such as powerful gate drivers would be necessary for a working machine. R. E. Meagher Introduction This set of direct-coupled logical circuits, using Western Electric GA53233 transistors and National Union T37J diodes, is intended to work in the 30 millimicrosecond speed range. The individual circuits are designed to use only transistor bases as input electrodes and to provide an output capable of driving at least one other circuit without using an emitter- follower . In some cases this requires the use of an input emitter-follower inside the individual logical element (such as in the NOT circuit). The circuits are based on the following tolerances: Transistors 0.90 < dc a < 1.00 (9 < * < <*=>) Emitter-base Drop (Conducting) 0.30v< VV,^ < 0.50v Diode Drop (Conducting) 0.20v to O.^Ov Power Supply Voltages +3$ Resistors +2$ The requirements which were placed on the transistors were chosen partly from manufacturer's specifications but mostly from data taken on 30 units. Of the ^0, only 13 units actually met these specifications. The others were rejected mostly for low dc a, with one rejected for excessive emitter-base drop. Since the degree of variability to be expected from regular production runs is not known as yet, the seriousness of this problem cannot be determined at present. In the cases of emitter- followers and level restorers the tolerances allowed for power supplies and resistors may be broadened and this has been done as shown on the drawings. Flipflop (Figure l) The basic circuit of the flipflop has a single external terminal to which are attached both the input gates and the output emitter- follower when such is required. The design permits an external load on the output lead of 0.5 ma or 2.5 ma from an emitter- follower as shown. This means that one in- put to another logical element can be driven directly or five can be driven from an emitter- follower. The gate diodes are to be driven by emitter-followers. The 22 ohm resistor between the clamp and gate diode pairs permits the gate signals to -1- +a5V±3% GATE SIGNAL NORMALLY -.9 ±.ZV TO SATE: +.75±. 25V +25 V ±5% 5.6K±5% -a5V±3% -25V±5% Operation Time: 16 mj-is Figure 1. Basic Flipflop (shown with emitter- follower) slightly exceed the clamp voltage without drawing excessive current from the gate emitter-followers. The value of the clamp voltage (0.60v) has been chosen so that the emitter-base voltage rating of lv of the flipflop transistors will not be exceeded for the maximum diode forward drop of O.^Ov. The emitter-follower shown with the flipflop may be used with any of the other circuits . The variability indicated in the output signal is due to the forward drop of the clamp diodes (0.20v to OAOv) and the emitter-base drop of the emitter- follower (0.30v to 0.50v). AND and OR Circuits (Figure 2) The actual function of these circuits depends on the polarity of logic chosen. They consist of diode circuits with two emitter-follower inputs and can drive only one input or an emitter- follower. -2- +25V±5% IN, IOKi5%. -4v±l0% 6.2 K ±5% '/2W 430 ±5% ^ w l5Kt5°/ * 10K±5% k OUT IN; '/2 W OUTPUT: 0.0 ±0.2V ABOVE INPUTS _-4V±IO°/o Operation 'irae: A"rprox. 5 m^s t25Vi5"% +25Vt5% 5.1 K± 5% l/ £ W IN -4V± 107c output'. o.o +o.i v ^> 39*5 7, Ve w 0K±5% /£ W ABOVE INPUTS OUT -14 5.1 Kt 5% i/ 2 w IN, -4VilO% N OT Circuit (Figure 3) -25V±5% b Operation time: Amr^x . 1 mu.s Figure 2. AND and OR Circuits The NOT circuit is actually half of the flipflop circuit with an emitter- follower input. It is capable of driving 2 inputs without an out- put emitter-follower or 15 with one. The emitter- follower at the input is an integral part of this circuit. If the transistor in the NOT had an a greater than 0.95> the input emitter- follower could be omitted. +25V±3% +25V±5% 6.2 \<±5%- k 2.2K±2% 1/2 W MINI. INPUT SIGNAL -1-0.5 V -0.4 V -C^i •n 3.6Kt2% 7 2 w +0.6 v ± 3 7. i +0.9 -O.IV • OUT -4v±iOV. iU2Kt2%, < IW -25V±3% l.3K±2 7o i '/ 2 w -0.6 V ±3.Vi -0.9 ±0.1 V Operation time: 20 m^s Figure 3. NOT Circuit -3- Last Moving Point Flipflop (Figure h) This circuit is for control or asynchronous applications where a true indication of the state of the circuit is desired regardless of whether or not it is being gated at the moment in question. The speed of this circuit is not as great as the others shown due to the higher impedance level of the output bleeder. It can drive the same load as the regular flipflop. .SATE SIGNAL NORMALLY ~,9±.2V to sate: +.75±.Z5V £5V±3% •OUT -.9±.IV -6V±3% 1.3 K ±2% IW -afcv±3% c GATE SIGNAL NORMALLY 4-. 9 ±.2 V TO sate; -.75 ±. 25V Operation time: 30 hi|j.s Figure h . Last Moving Point Flipflop Symmetrical Flipflop (Figure 5) This is a modified version of the basic flipflop which provides comple- mentary outputs. It can be used in control or register applications where only approximately asynchronous operation is desired. The internal emitter-followers are required to keep the flipflop fast by providing ample current drives to the flipflop transistor bases where Miller effect capacities occur. (For further discussion on the Miller effect in transistor NOT circuits see report by Sylvian R. Ray. y As a by-product of these internal emitter-followers, the symmetrical flipflop is capable of driving five inputs with either or both of its output terminals . "The Effects of Saturation on the Switching Response of Common-Emitter Amplifiers using Diffused-Base Transistors," Digital Computer Laboratory, File No. 208, by Sylvian R. Ray. -h- Positive going gates turn over the flipflop with the help of the diode in the emitter circuit. Negative going gates cannot be used since a negative voltage excursion of greater than the negative clamp voltage would he required. The 68-A. resistors in the emitter circuit are required to keep the emitter-base voltage within the allowable Iv maximum. +25V±3% +.6V±3% i T -vV- Z.7K ±5% /aw +.6V±3% Z.7K GATE. SIGNAL NORMALLY! -.9±. 2V TO GATE: +.75 ±. 25V / » f 1 ° V if T — " — K W 5 %<±,5% < '*>< J — ° — T7££r-" -4V±io% |^T \^ -4V±io% J. 3KtZ% ^ W +.6±3% >(Z)9!0 aw SATE SIGNAL NORMALLY'- -. 9±.2V TO SATE: +.75±.Z5V t -25V±3% Figure 5- Symmetrical Flipflop Operatic:, time Approx , 30 mu.s Speed Considerations Emitter-follower type circuits: The slowest direction of movement of the output of an emitter-follower (pnp) is positive, for which the transistor is cut off. For a 2.5 ma circuit and 2v signals the operation time is t - £¥ z I = 0.8c mu-s where C is in upf . 5- The speed of bleeder chain circuits is determined by the output impedance level and load capacities. The time constant of the circuit is t = RC mu-s where R is in K_0_ and C is in \i\sf . Cascading Circuits No more than one AND or OR circuit plus one emitter-follower may be inserted between two of the following signal level-restoring circuits in any combination: NOT circuit, basic flipflop, or last moving point flipflop. No more than one AND or OR circuit may be inserted between a symmetrical flipflop and any of the above-named signal level-restoring circuits. Operation Time Tests Several test circuits were built to check the speeds of operation of the logical elements. Since the individual elements are quite fast, direct measurement of a single element is difficult. The test circuits therefore consist of several logical elements connected in such a way that the time for several operations can be determined as a measure of the individual element speeds. While it is true that it is difficult to assign a specific operation time to each element, the measurements do give a good indication of the speeds to be expected in actual applications. "*"" The first test circuit, Figure 6, is a basic flipflop with gates, in — \§m/is -25V TRANSISTORS! W.E. GA53233 0.30 <, OC ^ LOO DIODES! N.U. T37J FLIPFLOP RESISTORS: ±2% OTHER RESISTORS! ±5% H -6V 1 91 -6v j FROM SQ. WAVE GEM. Figure 6. Flipflop Test Circuit -6- +.5V -1.0 V / which the time from the start of the input signal to the completion of the gating operation was measured. This time was 16 mu.s . Of course this time is determined directly by the amount of current used in the gate, but it was found that the flipflop did stay in its new state with a 16 mu-s gate without "falling back." The repetition rate of the pulser was sufficiently low (100 cps ) to establish this fact. The second circuit, Figure 7 t i £ a "racing register" in which two flipflops are permanently connected by gates in such a way as to continuously change states. Last moving point flipflops were used so that a true measure of the flipflop transition time could be made. In addition to the two flipflops, a NOT circuit was required for the necessary phase reversal and its operation time was also included in the measurements. The period of oscillation of the register was 160 mu.s, so that if all the 6 operations which occur (four flip- flop changes and two NOT changes) in one cycle are assumed to be equal, the individual element operation time is l6o/6 = 26.6 mu.s . (The individual times are determined separately in the next paragraph.) +0.5 v -0.5V -6V OUTPUT Figure 7- Racing Register -7- The third circuit, Figure 8, is an asynchronous gate of a last moving point flipflop. It is so arranged that the flipflop causes its own gate signal to he removed when it has arrived at its new state. The gate signal to start the transition is supplied by an external pulser and is made longer than the gate will actually he. The flipflop is reset by another pulse 5 milli- seconds later which is long enough to determine if the flipflop "falls back." • 25V + 25V A +Q.5V OUTPUT n i # i INPUT i 2.1 K W 104 myus +25V it o -ev 1.2x4 " \ OUTPUT -I.OV o » 2.2Ki5.IK> I W > > ffi? -6V * 1 + 25V A SO m/i5- +25 V J^ Muerle •11-