HBSNi BoHHHH Inlii IIW HUtti ma m BH ffi RmHi MB SShbsS ■HH B 88 S:9 ■ ■jjMfifl IflH ■ ■ ■ ■ rf ■^yv ■ :yf$ ■ H B ■. B ■** ;# I w* I •:.'V H BH H HB HH H rVDUH 89 on HI G5BHS m BB BHB H HOE AMvSM BS In » HUSH LIBRARY OF THE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAICN 510.84 no. 308-315 cop2 The person charging this material is re- sponsible for its return to the library from which it was withdrawn on or before the Latest Date stamped below. Theft, mutilation, and underlining of books are reasons for disciplinary action and may result in dismissal from the University. UNIVERSITY OF ILLINOIS LIBRARY AT URBANA-CHAMPAIGN APR 2 6 1974 APH 9 nfi5|i L161 — O-1096 Digitized by the Internet Archive in 2013 http://archive.org/details/displayfordemons312esch Report No. 312 A DISPLAY FOR DEMONSTRATING ANALOG COMPUTATIONS WITH RANDOM PULSE SEQUENCES by J. W. Esch APR J 18S9 March 11, 1969 DEPARTMENT OF COMPUTER SCIENCE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN URBANA, ILLINOIS Report No. 312 A DISPLAY FOR DEMONSTRATING ANALOG COMPUTATIONS WITH RANDOM PULSE SEQUENCES by J. W. Esch March 11, 1969 Department of Computer Science University of Illinois Urbana, Illinois 6l801 This work was supported in part by the Office of Naval Research under Contract N000 IU-67-A-O305-OOO7. A DISPLAY FOR DEMONSTRATING ANALOG COMPUTATIONS WITH RANDOM PULSE SEQUENCES I. Introduction This display, shown in Figure 1, is a demonstration of a new way of electrically representing numbers. The big advantage of this particular representation is that the numbers represented are continuous as in an analog computer and not discrete as in a digital computer. How- ever, the basic operations of addition, subtraction, multiplication, division, and squaring are performed using digital circuits. In short, analog computations are done with digital circuits giving us the advan- tages of continuous variables and fast realiable cheap digital circuits. The Random Pulse Sequences (RPSs) mentioned in the title characterize the way numbers are represented in this display. More fully we are dealing with clocked RPSs (CRPSs). A drawing of a CRPS with respect to the clock pulses would show a sequence of pulses randomly spaced in aribitrary clock periods. The magnitude of the number repre- sented would be the probability that a pulse will occur in some clock period which is e jual to the normalized average number of pulses that occur during some ample time. In this display then, the magnitude of a number is thought of as either the probability of a pulse occurring or the normalized average number of pulses or both. The development of this display is an extension of the work of C. Afuso to include signed numbers and was guided by Prof. W. J. Poppelbaum. Figure 1. Display for Demonstrating Analog Computations with Random Pulse Sequences -3- One property of this representation of numbers is that, if two independent CRPSs are fed into an AND gate, the' output will also be a CRPS. Its probability of having a pulse is the probability that both in- puts have a pulse and the number thus represented is equal to the product of the numbers represented by the input CRPSs. Because the probabilities of pulses occurring during adjacent clock periods of the same CRPS are independent, a second property is that a CRPS can be delayed one clock period with a flip flop. If the original and the delayed CRPSs are then fed into an AND gate, the number represented at its output is the square of the number represented by the original sequence. To see a third property, consider the circuitry in an analog computer to switch one of two desired analog signals onto some bus. In a CRPS system, if the two analog quantities are CRPS-A and CRPS-B, then the Boolean expression for the bus would be SA V SB where S is a digital signal used to switch A or B onto the bus. The cost of performing these properties in a system according to O.E.M. December 1967 prices could be less than 80 cents to multiply, $2.80 to square, and $1.20 to digitally select one of two analog signals. In addition to low cost, a CRPS system has the speed and realibility of integrated circuits . II. Generating a CRPS This section appears before that of the system design so that any readers who might still be confused about the exact nature of CRPSs will have the opportunity to clarify their understanding. The following drawing, Figure 2, illustrates how a CRPS is generated and how some of the signals look. The noise source is a pn junction reversed biased into plasma breakdown. This noise signal is -h- SIMPLIFIED CRPS GENERATOR NOISE SOURCE / \ LEVEL DETECTION J ( SAMPLING JU ANALOG INPUT CLOCK CRPS (DETECTION LEVEL) DETECTION LEVEL TIME Figure 2. Generating a Clocked Random Pulse Sequence (CRPS). -5- fed into a variable level threshold detector. The output of this detector is a logical signal which is a "1" only "when the noise voltage exceeds the threshold voltage. As the threshold is changed, the probability that the detector's output will be a "1" is changed. This signal is then sampled with clock pulses to obtain a signal whose pulses, when they occur, occur during a clock period. Thus as the threshold is changed, the probability that a pulse will occur during some arbitrary clock period is changed. Because the relationship between the threshold voltage and probability is not linear and because the noise characteristics are sen- sitive to the bias voltage and temperature, a smore elaborate circuit, shown in Figure 3? is used which utilizes feedback. In this circuit the SM535^+ transistor's collector to base junction is used to generate the noise. The 100K resistor and +2^v supply act like a current source and provide the bias current necessary to achieve plasma breakdown. The 710 linear integrated comparator circuit acts as the threshold device and the SN7^7^N acts as the clocked sampling unit. Its output pulses are fed back to the 709 linear integrated operational amplifier circuit. This has as its other input the input voltage threshold. The 7^9 is wired to integrate the error between the average voltage of the pulses and the input voltage. The output error plus bias voltage increases if there are too many pulses. This error plus bias signal is fed to an RC circuit to eliminate any noise on that signal. A few millivolts error on this signal can mean a large error in the number of pulses. The output of the RC averaging circuit determines the threshold for the 710 circuit. If this threshold signal increases fewer noise pulses will be larger than the threshold. This results in fewer output pulses which will in turn reduce the threshold voltage. Thus errors in the system tend to be reduced, cX CRPS GENERATOR CARD ( 2 PER CARD * ) ■6- IN>^ AR" 'ar° AR" >A^ * WHERE A WIRE HAS 2 LABELS OR PIN NUMBERS , THE TOP ONE IS FOR THE R N AND THE BOTTOM ONE FOR THE R° CIRCUIT. Figure 3. CRPS Generator Circuit -7- III. System Design and Operation The view a person using the display has' is shown in Figure 1 and the inside of the display is shown in Figure h. The system design is shown in Figure 5- To explain the interactions of the system components, a typical computation will be explained. After the power has been connected and turned on, the system is calibrated. This can be done best by setting the operation code to the A operation and adjusting the A input magnitude potentiometer (pot) so that the count on the Clocked Result banana jack is as close to 500KHz as possible. The calibration pot is then ajusted so that the result meter reads exactly 0.5- The operation switches are not set for any desired operation, the input magnitude pots are adjusted so that the A and B meters indi- cate the desired magnitude for the A and B inputs, and the signs of the A and B inputs are set as desired. The input pots adjust the thresholds of the CRPS converters as discussed in Section II. The CRPSs coming out of the converter go two places . First , they are buffered and then averaged by the A and B meters. Second, they go into the Computing Element where they are operated on according to the operation specified by the sign and operation switches . The outputs of the Computing Element consist of a sign signal which drives the sign bulb and the Result CRPS which is buffered and averaged by the Result meter. The Result CRPS is also clocked and sent to the Clocked Result banana jack. Typically then, the operator sets the input operation and sign switches, adjusts the input magnitude pots while watching the A and B meters, and reads his result from the Result meter and sign bulb. ■8- Figure h. Physical Layout of the Display -9- COMPUTATIONS MAfcNlTUOl ■I" i+uv 5IC>*— POWtR COMMECTOH AMD %VgtTCH OPERATION ANAL0* TO CB.TO COUVtRTM MAC*, t CMU> I «,s]i»*t£jq i.i.uf A CONTROL.* T\WU*»fc tiRdyin RACK 1 CARD 4 RACK. t CARD L — *? s v ' ^L ^m 1,3, XI w* *•*■*, ^.li LL&, Z±- s^ ^ i-,*,1 COMPUTING El.£>A«NT RACK 1 CARDS t,H3 CALIBRATION f -m\ REFERENCE CIRCUIT r^L Ly^Cj_^6^ MtTtR REiO»-T AVERAbED RANDO*' PUI.%1 *t«U%MCt% ■€» SANrMA Co M M|,CTo «> f. (ON MINUSl 4HN OF REiULT Figure 5- System Design -10- IV. Computing Element The computing element as a whole consists of six large sections of gating which form Boolean expressions for the operation to be performed, the J and IC inputs to the output (Result) flip-flop, the UP and DOWN signals for the up-down counter, and the correct sign for the output. There is also a sign flip-flop which indicates the relative magnitudes of the A and B inputs during subtraction. In order to add two CRPSs we literally force the result CRPS to have as many pulses as the sum of the input pulses . This is done by applying a pulse to the output whenever input-A or input-B has a pulse. The need for the up-down counter arises whenever both A and B have pulses. In this case the counter is increased one count. Then, whenever neither A nor B has a pulse and the counter is not empty, the counter is counted down one count and a pulse applied to the output. The equations to do this are: J* = A v B, }£ = ABZ, UP + = ABW, D0WN + = ABZ where Z(W) indi- cates all zeros (ones) in the counter when it is a "1". To subtract CRPC-B from CRPS-A we delete a pulse in the A sequence for each pulse that occurs in the B sequence. A problem arises when the B sequence has a pulse and the A sequence does not. In this case we increase the counter one count. Then, for each A pulse for "which there is not a B pulse, the counter is decreased one count unless it is already empty. In that case a pulse is applied to the output. The equations for a simple subtraction are: J = ABZ, }C = A v B, UP = ABW, DOWN = ABZ. If the B sequence is larger in magnitude than the A sequence, then the counter will continually, on the average, increase its count. Eventually it will become full (W = "1"). When this happens one can commute the inputs and change the sign of the Result. -11- Division is slightly more complicated to understand but as easily performed as addition and subtraction. The number of pulses in the average period of two pulses of a CRPS is equal to the reciprocal of the sequences value. To multiply this quantity times a dividend sequence we output this quantity for each pulse in the devidend sequence. Mathemati- cally the input A and B are characterized by P. = f./f and P^ = f-o/f — — AA'c BB'c where P is probability, f is average frequency, and f is clock frequency. The reciprocal of P is f /f . If this number of pulses is applied to the output for each A pulse, the output sequence has f = f f /f pulses. Normalizing we get P^ = f^/f = f./f., which is correct for division. In R R' c A' B actual practice for each A pulse all the pulses in the next B period are applied to the output. Again a counter is necessary. In this case it keeps track of the number of A pulses which have occurred for which no B periods haA/e occurred. The equations for simple division are: JJ" = BZ v AB, R K^" = ABZ, UP" = ABW, DOWN r = ABZ. Because of overflow problems, the A input sequence is prescaled by .1 in the display. Multiplication is the easiest of the operations because a simple AND gate will form the product of its inputs if all the inputs are independent. Thus, P A = f A /f and P^ = f_/f yield P^ = f.f^/f 2 . ' A A' c B B' c R A B' c 2 2 If P is a delayed version of P , then P = f /f to give a squaring operation. In the diagram that follows, Figure 6, most of the circuitry is necessary to form the expressions J , K_, UP , DOWN from A, B, Z, and W and to form J = J^, K= K±, UP = UP 1 , and DOWN = DOWN 1 . ■12- • > >>- * &-^y* IF -ED ■m E 3 — tr y S> 5>^> a> S*-^ 3> D^ i^> i> 4^h D* ->» ->« ->» -S >< tzrx G^-4y^ -gvg — ►» _ i^g)« % i '.1 •■«©»» ««.» • .an. *..l > •»»•« ««.» m8h B-b*-*— " D — CD B*l ,ym 1 - Q>- A t^~x n> ^-i?- _L n»< © O Figure 6a. Computing Element: Operators and Operands Card ■13- >«• <>- TT • v- ~T z *LV Tl ■<■/ !^> 3> © — i +^> «>2 /-TV *»V -»® _ OiOOt-i lN*%fc Figure 6b. Computing Element: Up-Down Counter Card -1k- ' r«* 1> 4\. 1 «»o Hy^Hjii. ^P Figure 6c. Computing Element: Outputs Card -15- V. Control and Timing There are several major timing considerations. First, the sampling unit in the converter and the output flip-flop in the Computing Element are driven by the same clock. Consequently, the maximum path delay from the sampling unit to the flip-flop must be less than one clock period. Secondly, the sampling unit triggers on the positive clock trans- ition and the flip-flop and counter on the negative transition. This means that the clock pulse must be as narrow as possible and its period must be at least as great as the maximum path delay. The display uses a 1MHz clock frequency with the clock pulse width about 40ns. This is more than adequate to eliminate any timing difficulties. The remainder of the circuits in this unit generate a sequence with a magnitude of .1, buffer the signals going to the meters, and clock the Result sequence so that it can be counter. Figure 7 illustrates these circuits. VI. Sampling CRPSs and Accuracy Because we can square by delaying a sequence one clock period and multiplying the original times the delayed sequence, we know that adjacent clock periods are independent samples of the random variable of the noise being greater than the threshold voltage. If we count, over a period of time, T, the number of clock periods which have a "1", the resulting distribution is binomial because each clock period is essentially an independent trial. When the number of samples n = Tf is large, the distribution becomes Gaussian as shown in Figure 8. The mean is proportional to the clock frequency and the length of time sampled, i.e. proportional to n. The standard deviation is proportional to vn, so accuracy increases as the vn. ■16- > ^ Mooev. ioos Rft>CVC Z CARD Z1 «e»ouT «**\J\_T £•1 ^ > lOMH. riO «* Resu»_T BCD TlO wi*%ou A a o IMW, w ■H A. t>— 1» =>YNC ■5 is ^_y^ 9h +VCC >10K 15p» CLOCK. VfNC /CLOCKZD RE%0\-T RACK 1 CARD A. %VK1C CLOCK. AOni il fl 1 MMiy + 24 VDC > + 12 VDC > +6 VDC > -6 VDC DISPLAY POWER SUPPLY Figure 10. Power Supply Circuit -21- di vision used in this display could be used. If a large system were to be designed, it should include both scaling and non-scaling addition. In a system -which doesn't have scaling, overflows can be a problem. In a system which doesn't have non-scaling addition, the magnitudes of variables may, after many operations, get lost in the variance of the random signals. The second area for improvement is the logical design of the Computing Element. The circuits necessary to do this could be reduced in several ways. First, by making use of the fact that A + B can be per- formed by forming A - B and wiring the up-down counter to always perform subtraction, i.e. UP = AB, DOWN A AB. A close look at B/A shows that up is AB and down is AB. In general then, it should be possible to wire the up-down counter to work the same way for all operations that use it and just put the correct A and B expressions into it. This would eliminate some of the gating necessary to form the UP and DOWN signals as presently designed. Secondly, the logic can be reduced by using a D-type sampling flip-flop. This requires one input which is clocked to the output with each clock pulse. In this case, logic is necessary to form only the D expression and not the J and K^ expressions as is presently being done. Thirdly, when two numbers of the same sign and equal magnitudes are subtracted, the error due to the finite size (3 stages) of the u- down counter becomes quite evident. A four or five stage counter would substantially reduce this error. -22- BIBLIOGRAPHY (Chronologically) 1. Ribeiro, S. T. , "Comments on Pulsed-Data Hybrid Computers" IEEE Transactions on Electronic Computers, Vol. EC-13, October 1964 , pp. 640 and 64l. 2. Afuso, C, "Quarterly Technical Progress Reports", Circuit Research Section, Department of Computer Science, University of Illinois, starting January 196$ to September 1966 . 3. Gilstrap, L. 0., H. J. Cook and C. W. Armstrong, "Study of Large Neuromime Networks", Adaptronics, Interim Engineering, Report No. 1 to the Air Force Avionics Laboratory, USAF, Wright-Patterson A.F.B., Ohio, August 1966, pp. 73-116. 4. Afuso, C. and J. W. Esch, "Quarterly Technical Progress Report", Circuit Research Section, Department of Computer Science, University of Illinois, October 1966 to December 1967 . 5. Gaines, B. R., "Stochastic Computing", AFIPS Proceedings, 1967 SJCC , Vol. 30, pp. 149-156. 6. Gaines, B. R. , "Techniques of Identification With the Stochastic Computer", IF AC Symposium, June 12, 1967, Prague. 7. Ribeiro, S. T. , "Random- Pulse Machines", IEEE Transactions on Electronic Computers, Vol. EC-16, June I967 , pp. 26I-276. 8. Gaines, B. R., "Stochastic Computer Thrives on Noise", Electroincs, Vol. 1+0, No. 14, July 10, 1967, pp. 72-79. 9. Poppelbaum, W. J., C. Afuso and J. W. Esch, "Stochastic Computing Elements and Systems," AFIPS Proceedings, I967 FJCC , Vol. 31, pp. 635-644. 10. Afuso, C, "Analog Computation With Random-Pulse Sequences," University of Illinois, February I968 . 11. Esch, J. W. , "Stochastic Computing: What is it? What can it be used for?" Electronic Communicator, Vol. 3? No. 2, March 1968 , p. 4. Unclassified Security Classification DOCUMENT CONTROL DATA • R&D (Security classitlcation ot title, body of abstract and indexing annotation must be entered when the overall report ia claaailied) I. ORIGINATING ACTIVITY (Corporate author) Department of Computer Science University of Illinois Urbana, Illinois 6l80I 2a REPORT SECURITY CLASSIFICATION Unclassified 26 CROUP 3 REPORT TITLE A DISPLAY FOR DEMONSTRATING ANALOG COMPUTATIONS WITH RANDOM PULSE SEQUENCES 4 DESCRIPTIVE NOTES (Type ot report and Inclualve datea) Technical Report 5 AUTHORfS)(L««ln«me, first name, Initial) Esch, John W. 6 REPORT DATE March 11, I969 la- TOTAL NO. OF PAGES 25 7b. NO. OF REFS 11 8a. CONTRACT OR SRANT NO. 9a. ORIGINATOR'S REPORT NUMBER(S) N000 14-67-A-0305-0007 b. PROJECT NO. 9b. OTHER REPORT no(S) (A ny other numbers that may be assigned this report) None 10. AVAILABILITY/LIMITATION NOTICES 11 SUPPLEMENTARY NOTES None 12. SPONSORING MILITARY ACTIVITY Office of Naval Research 219 South Dearborn Street Chicago, Illinois GoGoh 13 ABSTRACT This display is based on stochastic computing techniques where numbers are represented by probabilities which means that the variables are continuous. The probabilities are electrically simulated by random pulse sequences which are fed into logic gates. For example, the probability of a pulse occurring at the output C of an AND gate where C = A + B is the probability that inputs A and B both have pulses or P(C) = P(A)P(B). Multiplexing one of several analog variables A. , i = i to n onto a common output buss F is accomplished by implementing the Boolean function F = S n A_, v S„A^ v . . . v S A where only one of the selection 112 2 n n signals S. is a logical "1". Since all the mathematical operations are done with digital circuitry, it is easy to combine these outputs with multiplexing to obtain a programable arithmetic computing element in the form of self- contained portable display. D D , W.. 1 473 Unclassified Security Classification Unciassil led. Security Classification KEY WORDS Stochastic Computing Numbers Represented by Probabilities Continuous Variables Random Pulse Sequences Multiplexing Digital Circuitry Programable Arithmetic Computing Element Self-contained Portable Display LINK A LINK B ROLE LINK C INSTRUCTIONS 1. ORIGINATING ACTIVITY: Enter the name and address of the contractor, subcontractor, grantee, Department of De- fense activity or other organization (corporate author) issuing the report. 2a. REPORT SEC I 1RITY CLASSIFICATION: Enter the over- all seountv classification of the report. Indicate whether "Restricted Data'' is included. Marking is to be in accord- ance with appropriate security regulations. 2h. GROUP: Automatic downgrading is specified in DoD Di- rective S200. 10 and Armed Forces Industrial Manual. Enter the grou; number Aim when applicable, show that optional mBtkiiH hsve b»>"r used fir Group 3 and Group 4 as author- ized. 3. REPORT TiTLF: Enter the complete report title in all capital letter*. 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