LIBRARY OF THE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN 510 M ho..?l2-2;2o Digitized by the Internet Archive in 2013 http://archive.org/details/systemdesignfora219esch JJltAJ Re po r t No. 219 MtZj . COO-l^+69-OOU8 T SYSTEM DESIGN FOR ARTRIX GRAPHICAL PROCESSOR by JOHN WILLIAM ESCH January h, 1967 DEPARTMENT OF COMPUTER SCIENCE • UNIVERSITY OF ILLINOIS • URBANA, ILLINOIS Report No. 219 SYSTEM DESIGN FOR ARTRIX GRAPHICAL PROCESSOR by JOHN WILLIAM ESCH January k, 1967 Department of Computer Science University of Illinois Urbana, Illinois 6l801 Ill ACKNOWLEDGEMENT The author wishes to express his gratitude to his advisor, Professor W. J. Poppelbaum, whose counsel and encouragement have been very helpful. The author is also indebted to the Department of Computer Science for the assistantship and facilities which made this project possible . Thanks are also extended to the other members of the Artrix group, Al Irwin, William Kubitz, Peter Oberbeck, and David Rollenhagen, whose help and friendship have been invaluable. IV PREFACE The Artrix system as conceived by Dr. W. J. Poppelbaum is a research venture into display systems. The basic property of Artrix is its ability to store and display graphic information and to do Euclidian construction all ■without the aid of a backup digital computer. This is accomplished by on-line processing of TV-frames using digital control of analog signals . The hardware that the operator sees are a display monitor, a light pen, and a control console. Through the latter the operator indicates to the machine what he wants done and by lighting indicators the machine informs the operator what it has done as well as what state the system is in. The internal hardware is composed of combinations of digi- tal, analog, and hybrid circuits which makes Artrix a "hybrid com- puter" in the true sense of the word. It is to be noted that the analog components have to operate at 10 mc frequency, i.e., that we are talking about circuits several orders of magnitude faster than conventional analog circuits. The Author's Masters Degree project was to design and construct the processor section of the Artrix system. TABLE OF CONTENTS ACKNOWLEDGEMENT iii PREFACE iv LIST OF FIGURES vi 1. THE ARTRIX PROCESSOR 1 1.1 Processor Functions 1 1.2 Example of Processor Operation 3 2. QUALITATIVE DESCRIPTION 5 2.1 Lissajous Patterns 5 2 .2 Hybrid Circuitry to Generate Mathematical Expressions 6 2.3 Counters to Store Points and Magnitudes 7 2.k Example Describing Internal Operation 8 3. SYSTEM PROBLEMS 12 3.1 Five Hundred Line Resolution 12 3.2 Interlacing 12 3.3 Synchronizing Storage System to the Processor 13 3.^ Synchronizing Counters lh 3.5 Ripple Counter Sneak Pulses lh 3.6 Slope Magnitude and Sign l6 k . TECHNICAL DESIGN 18 4.1 Switching Circuits 18 k.2 Counters 18 4.3 Control Circuits 18 5 . SUMMARY AND CONCLUSIONS 23 APPENDIX 26 LIST OF REFERENCES 38 VI. LIST OF FIGURES FIGURE PAGE 1. Artrix Information Flow Diagram 2 2. Processor Information Flow Diagram 10 3. Switching Circuit Schematic 29 k. Horizontal Master (HM) Counter Schematic 30 5. Vertical Master (VM) Counter Schematic 31 6. Horizontal Point One (HP..) Counter Schematic 32 7. Vertical Point One (VP ) Counter Schematic 33 8. Horizontal Point Two (HP p ) Counter Schematic 3^ 9. Vertical Point Two (VP p ) Counter Schematic 35 10. Expanding Radius (ER) Counter Schematic 36 11. Control Circuit Schematic 37 1. THE ARTRIX PROCESSOR 1.1 Processor Functions The processor unit in the "Artrix Information Flow Diagram" Figure 1, on the next page, has several functions. One of these is to communicate with the operator through the control console. The processor continuously lights indicators on the console which inform the operator what state the system is in. In the same manner it informs the operator of its responses to the commands that the operator has sent to the processor through pushbuttons on the console . Besides communicating with the operator through the control console, the processor takes the commands received from the operator and construction points in the point memory indicated "by him and processes this information on-line. The result of this processing is the output signal which effectuates the desired euclidian construction. An additional restraint on the processor is that the operator is not to be able to observe any time lag between his last command and the completion of the construction by the proces- sor. Consequently the processor's circuits (digital, analog, and hybrid) must be very fast. It is also a function of the processor to synchronize the entire Artrix system so that all units have the same time base and phase. DISPLAY light pen enable button STORAGE SYSTEM even odd field construction points commands sync output KL CONTROL CONSOLE PROCESSOR UNIT responses state of system Figure 1. Artrix Information Flow Diagram 1.2 Example of Processor Operation Referring to Figure 1 again, Artrix Information Flow Diagram, consider the case where the operator wishes to draw a line segment between some Point 1 and some other Point 2. The procedure would he as follows: The operator pushes the button labeled "Line". This sends the line mode of operation command to the processor which responds by lighting up that button. The operator then pushes the "Reset Processor" button which sends that command to the processor and is also lit in acknowledgement. The operator now takes the light pen and points it at the point where he would like one end of the line< to be . He pushes the enable button which transmits that point to the processor which in turn responds by lighting up the "Point 1 Stored" button. Since this happens instantaneously as far as the operator can tell, he can immediately indicate a point on the other end of the line seg- ment, Point 2. When he does, by pushing the enable button, "Point 2 Stored" lights up. Again, because of the processor's speed, the "Execute Construct" button lights, telling the operator that the line he wants can be written into memory just by pushing that button Suppose the operator has done this and now wants to construct a circle such that the line segment just described deter- mines the radius and a third point the center of the circle. The procedure is quite similar. The operator pushes the "Circle" mode button which the processor immediately lights in acknowledgement. Because the processor has already stored Point 1, (the center), the operator does not have to indicate that point again. Therefore, instead of resetting the entire processor, he can just reset Point 2, ("Point 2 Stored" light goes out). This is necessary because in the "Line" mode Point 2 stores the lines magnitude and not the actual point. The operator now indicates Point 2 again and pushes the enable button. When he does, the processor lights "Point 2 Stored" and "Execute Construct". Since this circle (which the processor is ready to write into memory) is not centered at the desired point, the operator now resets Point 1 (Point "1" Stored and "Execute Construct" lights go out) and indicates the new center of the circle and pushes the enable button. "Point 1 Stored" again lights as does "Execute Construct" which tells the operator that he has translated the circle to the desired new center and the processor is ready to write that circle into memory. This process of translation can be done in any of the construction modes just by resetting Point 1 and indicating a new Point 1. 2. QUALITATIVE DESCRIPTION 2.1 Lissajous Patterns These patterns are most commonly seen on an oscilloscope ■where the horizontal input is one sinusoid and the vertical input is another sinusoid of a different magnitude and frequency. The resulting trace on the oscilloscope is called a Lissajous Pattern. Under special conditions this pattern takes the form of a circle or a line. The restrictions for a circle to result are that the a.c. component of both inputs have the same frequency and magnitude. In addition, they must be 90 out-of -phase "with each other as, for example, sinout and coscot are. There are no restrictions on the d.c. components because they only determine the translation of the Lissajous Pattern. In general, then, a circle can be expressed mathematically as: X = R cosoot + X , Y = R sinoct + Y . Note that the horizontal deflection, X, and the vertical deflection, Y, have the same frequency, co, and the same magnitude, R, (the radius of the circle) The restrictions for a line to result are that the a.c. components of both inputs have the same frequency and phase. The magnitude then determines the shape. In general the line can be expressed mathematically as: X = A X sinout + X , and Y = A Y sinot + Y-, . Note that X and Y have the same frequency, a>, and phase, sinart, but different magnitudes , -A X and A Y. Also, as for the circle, the translation, (X , Y ) is arbitrary. Going back to the construction in Section 1.2, "we note that both lines and circles were constructed by specifying (with the light pen) two points in succession: For the circle, its center (X.. , Y, ) , and any point (X p , Y p ) on its circumference; for the line segment, its end points (X , Y ) and (X p , Y p ) . To obtain the desired circle, the processor generates the sweep: X = rt coscot + X , Y = rt sincot'. + Y, where r » co, i.e., we generate a circle with slowly expanding radius compared to the rate at which the circle is being swept out. At some time later, t = T, when X = X p and Y = Y simultaneously the radial expansion is stopped, leaving the desired circle X = rT coscot + X , and Y = rT sincot + Y for t > T. Note that rT = R, the radius of the circle, where R 2 = (X - X ) 2 + (Y - Y^ 2 . To obtain a line segment the processor generates the sweep: X = (X 2 - X x ) j sincot | + X x Y = (Y 2 - Y x ) | sincot | + Y 1 Note that this line segment has (X , Y ) at one end of the line segment and not at the midpoint of the line segment because the processor generates the absolute magnitude of sincot. 2.2 Hybrid Circuitry to Generate Mathematical Expressions There are five kinds of hybrid circuits used in the processor. The high speed high precision Digital to Analog Converters are used to transform the digital points (X, , Y, ) and (X p , Y p ), into analog equivalents. The low offset, low noise Digital Controlled Analog Switches have outputs which float for a logical "0" input and are equivalent to the analog inputs for a logical "1" input. The DCVGLA are very accurate linear amplifiers which convert an input sinusoid to another sinusoid of different amplitude. The new amplitude is determined by digital inputs and consequently this device is called a digital controlled variable gain linear amplifier. The Controlled Rectifiers rectify a sinusoidal signal full -wave positive, full wave negative, or not at all depending on the digital control signals. This device has low distortion and offset so that no D.C. error is introduced into the output. The Comparator has the ability to compare two analog signals, positive or negative, over a wide range of voltages and output a logical "1" when they compare withing a very small tolerance . 2.3 Counters to Store Points and Magnitudes There are seven nine-bit counters, HM, VM, HP , VP , HP p , VP , and ER. The HM, Horizontal Master, and VM, Vertical Master, counters run continuously. Their count specifies the horizontal and vertical coordinates of the Storage System's deflections. They also serve to synchronize the storage system to the processor. The HP,, (Horizontal Point One), and VP (Vertical Point One), counters contain the coordinates (X. , Y, ) when Point One is stored. The HP p , (Horizontal Point Two), and VP p (Vertical Point Two) counters contain the coordinates (X p , Y p ) when Point Two is stored in the circle mode and the magnitudes I X - X I , I Y - Y in the line mode. The ER, (Expanding Radius) counter contains the magnitude of the radius, R, in the circle mode. 8 The logic schematics for each of the counters can be found in the Appendix, Figures h through 10, pp. 30 to 36. 2 .h Example Describing Internal Operation The logic circuits for the hardware described below is shown on Figure 11, p. 37 > Control Circuits Schematic. In the example of Section 1.2, the operator "wants to first construct a line . When he pushes the line mode button, a flip-flop is set in the control circuits section of the processor, vhich lights the line button light (processor response) and switches gates for line mode operation within the processor. When the reset processor button is pushed, the HP, and VP, counters are made to run synchronously with the HM and VM counters and the HP and VP p counters are set to zero. When the processor receives the first construction point, Point One, it stops the HP n and VP, counters, lights the "Point 1 Stored" button, and starts the HP p and VP p counters counting. When the second construction point is indicated the processor also stops the HP p and V? p counters and lights the "Point 2 Stored" and "Execute Construct" buttons. Because the reaction time of the operator is in the millisecond range and that of the processor's hybrid circuits in the microsecond range, all of the processor's circuits have settled long be fore the operator can push the "Execute Construct" button. More precisely, when HP and VP stop counting, the digital to analog converters wired to them convert their digital translation to an analog one which can be added with the proper sinusoid to form the mathematical expression for a line. (See Figure 2, Page 10). When HP„ and VP stop counting, their magnitude is switched to the DCVGLA "which amplify sincot terms to that amplitude. Some of the gating that occurs when the line mode flip-flops is set, includes the type of sinusoid going into the DCVGLA (in this case, both sincot terms) and the type of rectification. Continuing with the example, when the circle mode button is pushed, a flip-flop is set in the processor and again the circle mode light is on, the line mode flip-flop is reset, and similar gating is done inside the processor. When Point Two is reset this time, it starts counting in synchronism with HM and VM counters. When Point Two is indicated, the ER counter starts counting and its output, because of the gating, now controls the DCVGLA. When the outputs compare with both X and Y simultaneously, the ER counter is stopped, the "Radius Stored" button, and "Execute Construct" buttons are lighted. To translate the circle to a new point, "Point 1 Stored" is reset, causing HP, and VP, to start counting in synchronism with HM and VM counters and the console to be updated. Indicating a new Point One causes the counters to stop and a new analog translation to be added to the circle of desired radius. Because of the design of the processor, several interesting features are available to the operator. Since the line operation only uses HP,, VP , HP p , and VP counters, an operator can save a radius in the ER counter as long as he likes while he draws lines. In add- ition, since the magnitude of a line is stored in the HP„ and VP p COMMANDS CONSTRUCTION POINTS EVEN ODD FIELD COINCIDENCE I COUNTERS DIGITAL TO ANALOG (X 2 .Y 2 ) 4> CONTROL CIRCUITS SWITCHING NETWORK magnitudes A.C. CONVERTER DIGITAL TO ANALOG T OUTPUT 10 -> RESPONSES -> STATE OF SYSTEM TYPE OF RECTIFICATION 1 SINUSOID GENERATOR amplified b sinusoids CONTROLLED RECTIFIER translations {X,,Y,) ( AND J Figure 2. Processor Information Flow Diagram 11 counters, both a line and a circle can "be saved and translated at •will -without destroying the contents of any of the HP ? , VP p , or ER counters. 12 3- SYSTEM PROBLEMS 3.1 Five Hundred Line Resolution* Our T.V. system has 500 vertical lines and about another 25 for vertical blanking. To insure that the processor be able to equal this resolution, nine-bit counters (512 lines) -were used. The procedure adopted is to start the VM counter from zero at the end of vertical blanking and have it count each line. As it over- flows, it is held until the end of vertical blanking, when it again starts counting. To get 500 line horizontal resolution, the frequency of the T.V. deflection system's horizontal lines was multiplied by 512 to get 8,062 Mhz . A crystal controlled clock at this frequency drives the HM counter "which overflows then at the line frequency of the T.V. system. The clocking signals which are generated to accomp- lish this are called TV and TH respectively. It is worth noting here that, since the magnitude of the field of view of the T.V. screen corresponds to the maximum magnitude of the counters, the magnitude of the complement of the counter's contents plus the magnitude of the counter's counters equals the magnitude of the field of view. 3.2 Interlacing Because T.V. systems are interlaced (all even lines, then all odd lines), the vertical counters had to be designed to take this *The logic circuit schematics and an explanation of the logic signal names can be found in the Appendix. 13 fact into account . Since successive even and odd lines in a normal sequence differ only in the least significant bit, the line count was fed into the second least significant hit and the least signi- ficant bit changed according to -whether or not it was an even or odd field. The effect of doing this is to count by twos through the even field, set the least significant bit and count by twos through the odd field, reset the least significant bit, and start over. 3-3 Synchronizing Storage System to Processor Normally, the T.V. system operates off the crystal in the Camera Control Unit which operates at 31-5 kHz, twice the frequency of line rate, 15*75 kHz. To synchronize the T.V. system to the processor, the output of the second most significant bit of the HM counter is fed into the T.V. Camera Control Unit as an external sync (Remember the most significant bit of the HM counter changes at the line frequency 15»75 kHz). However, this is insufficient for two reasons: When the system is turned on, the Camera Control Unit can lock onto either phase of the 31-5 kHz sync, signal. Consequently, the system could begin operating with the T.V. system's horizontal line beginning in the middle of the processor horizontal line (or vice-versa, depending on which is taken as a reference) . This phase problem was solved by sending the T.V. Camera Control composit sync, signal to the processor control unit. Here the phase is moni- tored continuously and adjusted automatically if the system for some reason should slip out of phase. 11+ The second problem centers around the Camera Control Unit . Even when the phase is adjusted, the horizontal sync, signals produced by the Camera Control Unit lag in time the sync . signals from the processor due to time delays in the Camera Control Unit. This was corrected by shifting the sync . signal from the processor to the Camera Control Unit ahead in time with respect to the old sync, sig- nal by the same amount as the delays in Camera Control Unit. 3-^ Synchronizing Counters In the examples of Section 2 .h it was stated that some of the counters had to be set running synchronously with the HM and VM Counters . The original scheme was to set the counters to zero when the reset button was pushed and start them counting when the HM and VM counters both overflowed simultaneously. However, because of a strange property of the integrated circuit flip-flops used, the ripple type counters could not reliably be set to zero. The solution was to monitor their count also, and, when they both overflowed, to stop them and wait for the next HM and VM overflow to start them again, 3.5 Ripple Counter Sneak Pulses In Section J>.k it was assumed that it would be easy to tell when a counter overflowed. This is usually done by examining all the stages of the counter and judging it an overflow when they change from all ones to all zeros. There are no problems when all the stages change at the same time as in a synchronous counter, but 15 in, a ripple counter there are time delays which allow false counts for very short times. Because, of the very fast speed of the inte- grated circuits used, they are able to pick up the false counts easily o For characteristics used see reference in Bibliography on T.I. circuits * To explain in more detail let us examine the operation of a ripple counter. Say that the changing of a stage from a logical ? °0' : to a logical "l" on its reset side causes the next stage following it to trigger and that there is a delay of t seconds from the "0" to the "1" transition until the next stage flip-flop has changed states. Assume you are monitoring the reset side of the counter with an "And" gate for all ones (which means the set side would be all "0") . When this condition occurs, you know overflow has occurred. Consider the case where the contents of the counter is a string of zeros followed by a string of ones on the reset side. When the next trigger pulse comes along, the first stage will change, causing the second stage to change until the first stage is reached which had a one on the reset side . When the stage before it changes from zero to one, there is a time during which all stages have a one on the reset side before that stage changes from a one to a zero. Because most gates are faster than their compatible flip-flops, sneak pulses will almost always occur under this condition. To gave the reader an idea of the problem faced in debugging the processor the sneak pulses were only 20 ns wide . 16 3»6 Slope Magnitude and Sign Recall that in the construction of lines the HP„ and VP ? counters are started from zero,, when Point One is indicated and stopped -when Point Two is indicated. Since the operator can specify either end of the line first, there are four possible classes of lines . The different classes are determined "by the horizontal deflection of Point Two being larger or smaller than that of Point One and similarly for the vertical deflection. If the horizontal (vertical) deflection of Point Two is larger than that of Point One, then there is no problem, for the HP (VP~) counter contains the correct count. If, however, this is not the case, then the HP„ (VP.) counter contains the one's complement of the desired count because of the properties discussed in Section 3-1° That is to say, if the horizontal (vertical) deflection of Point Two is smaller than that of Point One the count in the HP_ (VP„) counter will be the one's complement of the desired count. The problem of knowing whether or not to use the one's complement or the exact value was solved by the following technique . For' ease of understanding consider first the horizontal case (the vertical case being handled the same way) . Take a f lipoof lop and set it each time the HM counter overflows, reset it each time Point One is reached (.*. HP p overflows), and hold its contents when Point Two is designated. Thus, if Point Two is designated at a point where the horizontal deflection of Point Two is larger than that of Point One, then the flip-flop output will be an "0", since Point One has been passed and the HM counter has not overflowed yet. If the hori- 17 zontal deflection of Point Two is less than that of Point One, the flip-flop output will he a "1". In the first case, logical "0", the HPp contains the correct value, and in the second, logical "1", HP contains the one's complement of the correct value. The problem of slope magnitude is thus solved by looking at the outputs of tvo flip-flops (one for the horizontal and one for vertical) and using the one's complement or not of the HP and VP counters if the respective flip-flops is a logical "1" or not. The problem of slope sign can be solved by full wave recti- vying the output of the DCVGLA in a plus or minus direction according to the same flip-flop signals . Full wave rectifying in a plus direction for logical "0" and in a minus direction for a logical ''1". 18 h . TECHNICAL DESIGN 4.1 Switching Circuits From the discussion in J>.6 on Slope magnitudes and the knowledge that the radius is stored in the ER counter, it is obv- ious that the inputs to the DCVGLA come from several different places depending on certain conditions . Consider the DCVGLA for the horizontal positions. In the circle mode its digital control signals come from the ER counter. The bits of that counter are labeled QJ3R, Q,ER, . .. QoER "where Q is the least significant bit and Qn the most significant bit. The control signal for the circle mode of operation is CR. In the line mode the control signals are CH and CH. CH is a logical "1" when the one complement of HP p counter is to be taken and CH is a "1" when the actual count of HP is to be taken. Both are logical "0" in the circle mode of operation when CR is a "1". That is to say CR-CH = CR'CH = CH'CH = "0". The DCVGLA for the vertical position has control signals CR, CV, and CV with the same meanings only applying to the ER and VP p counters. Figure 3^ labeled Switching Circuit Schematics, gives the details. 4.2 Counters The ripple counter, although easy to design, can have many deficiencies as noted in several earlier sections. The circuits used were the Texas Instruments Series 74 Integrated circuits which are 19 described in the reference on T.I. integrated circuits. The flip-flops trigger on a "0" to ,; 1" transition; consequently, to get an increasing count the output of the reset or Q side is fed to the trigger of the next most significant stage for an increasing binary count . Because these flip-flops have enabling control signals, all of them have to be wired to the enabling state as appropriate. Examples of the ripple counters used are in the Appendix under VM, YP , VP , and ER. (Figures 5, 7 ) 9} and 10, respectively) . The synchronous counter, although harder to design, is more elegant in its operation and easier to use. Here the enabling controls of each flip-flop are very useful, beacuse to have synchronous oper- ation,, each stage must look at all less significant stages. If all of them are at a logical "l", it changes state -when the next clock pulse occurs. As opposed to the ripple counter "where the clock pulse goes only to the first stage, the synchronous counter sends the clock pulse to every stage. Because there is an eight input NAKD in the series 7*+ integrated circuits, it was possible to design the basic synchronous counter with at most one gate between stages. Examples of the synchron- ous counters used are in the Appendix under HM, HP,, and H? p . (Figures h , 6, and 8, respectively) . h ,~$ Control Circuits. It is suggested that at this point the reader skim over the Logical signals section of the Appendix since it will be assumed the reader knows what the control signals talked about in this section stand for. It will also help the reader if he follows the discussion 20 on the control circuit schematic in the Appendix. (Figure ll) . First, let us give a description of the circuits involved in the command, response, and state of the system signals. Since the circle and line mode of operation are mutually exclusive (and, therefore, cannot "be done at the same time) , the circle and line mode push buttons control opposite sides of an RS flip-flop, the outputs of which are CR for circle and CR for line. These then light indicators on the pro- cessor card rack and the Control Console as well as switch gates inside the processor. P. and P are the outputs of a similar RS flip-flop whose inputs are the gated light pen signal on one side and OP-RP and 0P-R1 on the other side. This flip-flop lights indicators on the processor and control console and also switches gates. All light pen pulses are gated to the P.. flip-flop; and, if that has already been set, they are also gated to the P p flip-flop, which is reset by OP-RP or OP-R . The P flip-flop lights indicators and switches gates also. The RS (Radius Stored) flip-flop is set by H . and V . v * * * J come come being a logical one at the same time when in the circle mode operation and P has been set. It is reset by OP-RP or OP-RR and its output also lights indicators and does gating. The PWG signal is the output of an RS flip-flop which is set by XC and reset by the XC signal. The two remaining responses are formed from signals already discussed. PR = P • P# RS and XR = T. • P 2 » CR + P • RS ' CR . Section 3*1 discussed 500 vertical line resolution. This is accomplished by generating the clocking signal TV. This signal is equivalent to the last stage of the HM counter, QoHM, until the VM counter is all zeros when TV is gated to a zero until the 21 end of vertical "blanking when it again is allowed to "be equivalent to QoHM . Section 3-2 discussed Interlacing where the least sig- nificant "bit had to be set for odd fields and reset for even fields. For the VM and VP counters this was easily accomplished. If E is a logical one when VB occurs, then set the least significant bitj and if E is a logical zero when VB occurs, reset it. The VP counter is more complicated "because of its operation in the line mode. The procedure here is to set it when VB occurs if is a logical one where = E * CR + P • CR and to reset it when VB occurs if is a logical one where 9 = E * CR + P ' CR. In Section 3*3 two problems were discussed: Line phase and Camera Control Unit delay . The former was solved by having TH not be equivalent to TM, but by having TH = TM ♦ (A n HM +A,g BM» CS) The latter was solved "by not having the sync, signal equivalent to Q 7 HM but equivalent to Q HM • Q/-HM, which amounted to the appropriate time shift . Section 3°^ discusses the synchronizing of counters. The actual procedure is to sex the counter to zero, then wain until both the HM and VM counters overflow and start the counters counting. The latter is done by resetting the OF, and 0F p flip-flops when the OP-R and CP-R pushbuttons are pushed respectively, and setting them when HM and VM overflow occurs . Then | H = OF • P, , TU = 0F 2 • P 2 • (CR + P x ), |V = |H . (CL 2 — .HP^ + Aj^ VP and r]V = T)H • (CL 2 — HP g ) + Aj^ VP 2 . 22 The problem of sneak pulses in ripple counters, which was discussed in Section 3«5> was solved by clocking all critical signals at a time when no sneak pulse could occur. In this case the edge of the clocking signal opposite to that one which does the triggering. The problem of slope magnitude and sign discussed in Section 3-6 were solved by obtaining the control signals CV, CV , CH, and CH. Essentially CV and CV are opposite sides of an R.S. flip-flop except that both are gated to zero when CR is a logical 1. The flip-flop is set whenever the VM counter overflows, is reset whenever the VP p counter overflows, and is held when P is a logical 1. Similarly, CH and CH are opposite sides of an R.S. flip-flop, except that both are gated to zero when CR is a logical 1. The flip-flop is set whenever the HM counter overflows, is reset whenever the HP counter overflows, and is held when P is a logical 1. It is again brought to the reader's attention that the Appendix contains both an explanation of all logical signals and the circuit schematics of the entire processor. 25 5 - SUMMARY AND CONCLUSIONS In this thesis it was the author's objective to give the reader an understanding of what the Artrix Graphical Processor can do. Firsts the processor communicates with the operator by receiving push button commands and lighting indicators to inform the operator of its responses to those commands and of the state of the system. Secondly, the processor does automatic on-line graphical processing, of which the end results are Euclidian construction. And, thirdly, it synchronizes the rest of the Artrix system. The successful operation of the processor clearly demon- strates the feasibility of doing on-line graphical processirg using hybrid circuitry. It is important to note that the hybrid circuits used respond orders of magnitude faster than conventional analog circuits. It is this speed that makes the concept of on-line graphical processing using hybrid circuits so practical and elegant: Practical and elegant because the systems involved can be designed more simply and straight forwardly. This is because the graphical display is essentially analog in nature and control and switching essentially digital. Consequently the hybrid system can take the best from both worlds. After working with the Artrix system the author has come to several conclusions. Since the operator is controlling the graphical processor with a light pen, the resolution of his work is limited by how fine a line and small a point he can see. Consequently, any processor need have an accuracy only as great as 24 the operator can control the processing. This suggests that one very practical "way to do processing is to give the operator control of the parameters:' instead of having his constructions done automatically. For example, in the circle mode of operation a standard circle could appear "with a small spot at its center . The operator then could translate the circle to the desired position, Toy locking the circle's center to the light pen. The exactness of the move is determined by the operator-s ability to position the center. Similarly, he could next expand the radius to pass through some point. Again the accuracy is determined by the operator's ability to position the edge of the circle. Notice that in the above dis- cussion the operator selects the type of geometric figure he wants to work with. It appears on the monitor, and the operator controls all the parameters of the general equation of the figure which he changes to suit his desire. The accuracy of the final figure is limited by the resolution of the display system and the sensitivity of the operator's controls. Such a system is not confined to a digital, analog, or hybrid system because of the fact that the way the parameter are formed and changed is up to the designer. However, it is the author's feeling that systems using a digital computer are designed around the computer and not designed around the problem at hand. Also, there is a tendency in such systems to push design problems that arise into the computer to be solved by programming. This is wrong. The system should be designed to solve these problems inherently. It is because hybrid circuitry is so versatile that 25 these problems can be solved more easily using them. The system that may best meet these needs is '-one "which has function generators ■whose basic building block is the operational amplifier and -whose interconnections are determined by logic circuitry and digital controlled analog switches. Such a hybrid system could easily be designed to incorporate most of the problems of a graphical pro- cessor . 26 APPENDIX A. . Logical And of bits i through j. -L ""J A- — r Logical And Not of the not side of bits i through j • CH CH means Complement Horizontal if a logical one . CH Don't complement Horizontal if a logical one. CH • CH = CL, Because the gates have a limited fan out, the nine -bit CLp counters need more than one signal to clear them, CL standing for Clear. CR CR stands for Circle and is a logical one when the pro- cessor is in the circle mode of operation. CS CS stands for the Composite Sync, generated by the T.V Camera Control Unit. CV CV means Complement Vertical if a logical one. ' CV CV means don't complement Vertical if a logical one. CV * CV = 0. E E stands for Equivalence and is a logical one "when the two high order bits of the Horizontal Master Counter are the same . EF EF stands for Expanding Frequency and is the frequency ■ ■which drives the Expanding Radius Counter. ER ER stands for Expanding Radius Counter -whose contents is the radius of circles drawn. H. is the i bit of the digital signal which controls the Horizontal DCVGLA. i HM HM stands for the Horizontal Master Counter whosei. contents correspond to the horizontal deflection in the T.V. system HP, HP stands for Horizontal Point One Counter and contains the horizontal coordinate of Point One. HP p EP stands for Horizontal Point Two Counter and contains the horizontal coordinate of Point Two for circles and the horizontal projection of the line for lines. H . H . stands for coincidence of the horizontal sweep coinc coinc with the horizontal coordinate for Point Two. 27 LP LP stands for Light Pen Pulse -which occurs once each time the operator indicates a point on the display in the point memory and pushes the Enable Button. OF OF stands for Overflow and implies the condition that a Counter has gone from all ones to all zeros. OP OP stands for an Operator-controlled signal. PR PR stands for Processor Reset and is a logical one when the processor is reset. PWC- PWG stands for Processor Write Gate and is a logical one ■when the processor output is "being written into the display memory. P, P.. stands for Point One and is a logical one -when P has been indicated by the operator . Pp P„ stands for Point Two and is a logical one when P p has been indicated by the operator. th Q. Q. is the i bit of a counter. Q,. Q. is the not side of the i bit of a counter. i l RP RP stands for Reset Processor and is a logical zero when the processor reset button is pushed. RR RR stands for Reset Radius and is a logical zero when the Radius Reset Button is pushed. RS RS stands for Radius Stored and is a logical one when the proper radius for the circle has been found. R-, R-, stands for Reset Point One and is a logical one when Horizontal and Vertical Point One Counters are being reset Rp Rp stands for Reset Point Two and is a logical one when Horizontal and Vertical Point Two Counters are being reset TH TH stands for Trigger Horizontal and is the clocking sig- nal for all Horizontal Counters . TM TM stands for Trigger Master and is the 8.062 mega hertz square wave . TV TV stands for Trigger Vertical and is the clocking signal for all Vertical Counters . V3 VB stands for the Vertical Blanking signal generated", by the T.V. Camera Control Unit. 28 V V stands for coincidence of the Vertical Sweep with come come r the Vertical Coordinate for Point Two. th V.. V. is the i hit of the digital signals which control the Vertical DCVGLA. 1 VM VM stands for Vertical Master Counter whose contents correspond to the Vertical Deflection in the T.V. system. VP-. V? 1 stands for Vertical Point One^ Counter and contains the Vertical Coordinate of Point One. VPp VP p stands for Vertical Point Two Counter and contains the Vertical Coordinate of Point Two for circles and the Verti- cal Projection of the line for lines. XC XC stands for Execute Construction and is a logical one when the Execute Construct Button is pushed. XR XR stands for Execute Ready and is a logical one when a construction is ready to be written into memory. T)H r]H is a logical one when the Horizontal Point Two Counter is to count. T)V rfv" is a logical one when the Vertical Point Two Counter is to count. 6 6 is a control signal for the Vertical Point Two Counter low order (least significant) 'bite It is a logical one when that hit is to be triggered into the reset state . |H £H is a logical one when the Horizontal Point One Counter is to count. |V |V is a logical one when the Vertical Point One Counter is to count. is Control Signal for the Vertical Point Two Counter low order (least significant) bit. It is a logical one when that stage is to be triggered into the set state. 29 r IL__ li__ o •H -P o -p • -H O !h >H 3 O bO •H W F-4 C •H ,3 O -P •H 30 2 15 < EZ oo.tr -i « r 0*0. X * CT> PO iri jd r- co m * o stsg 2 32 S3 3 , C O X a 0*0. T 10 ffi o f- tt V •H •P 05 S gj 4^ o CO Jh 0) -P O O -4" 0)*-- h 3 5h m aj •H P P>4 w rH cS -P a N • ~ O 31 -I * u. D i. o S I 10 o A U X 0. D < * * nv m ^ ft i ^ ° *"" £ * ** * A Hi I o U CD O •H -P 0) o ra (D ■P O • O LT\ CD S •H *H P-4 CD -P CO H n3 o •H -H *H > 32 jlI o 2 1 10 * * 2 9 ! O ft. C X >« O 3 I K» D < rg(|Hl O •H -P o -P O H VD M 9) Pi fl DO O •H fe -P •H O PM H cS -P o N ■H ?H O W 33 fc> % H « 2 2 8 o a. o- i x * o> a ■» I « 7 * »- «> © >o o k Zi 2+ ■» to S© s© -, ~ It- n « r a 2 • » -i x u- t® "I < x * » S tfl *> 0> O K 2 55 ® * St'" i < m « <-> * r^ *» « a> «j a. a; x -J * U. x 5 a* 10 rO <» O *- IQ <0 Q> iO O U * > Z Z a a * 10 m < < < 36 o •H -P cfl g