LIBRARY OF THE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAICN 510.84 lifer cop. 2 The person charging this material is re- sponsible for its return to the library from which it was withdrawn on or before the Latest Date stamped below. Theft, mutilation, and underlining of books are reasons for disciplinary action and may result in dismissal from the University. UNIVERSITY OF ILLINOIS LIBRARY AT URBANA-CHAMPAIGN L161 — 010% Digitized by the Internet Archive in 2013 http://archive.org/details/ocomoopticalcorr631budz j~ ^ uiucdcs-r-7u-63i jvo. (?3i f OCOMO ClOp- " s ~ OPTICAL CORRELATION MODULATION by Robert L. Budzinski THE LIBRARY OF THE APR 2 5 1974 UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN 7 March, 197^ UIUCDCS-R-7U-631 OCOMO OPTICAL CORRELATION MODULATION by Robert L. Budzinski March, 197^ Department of Computer Science University of Illinois Urbana, Illinois 6l801 This work was supported in part by Contract No. N000 1U-67-A-0305-007 and was submitted in partial fulfillment of the requirements for the degree of Master of Science in Electrical Engineering, March, 197^- Ill ACKNOWLEDGMENT The author wishes to take this opportunity to express his grati- tude to his advisor, W. J. Poppelbaum, for suggesting this thesis, for his support, and his guidance and friendship. He is very thankful for the fine work done "by the fabrication group directed by Frank Serio and by the drafting department directed by Mark Goebel. Special thanks go to Evelyn Huxhold for typing this thesis. He also wishes to thank his wife, Lyn, for all her assistance and patience. IV TABLE OF CONTENTS Chapter Page 1 GENERAL OPERATING PRINCIPLES OF OCOMO 1 1.0 Introduction -------------------- l 1.1 Pulse Code Modulation --------------- l 1.2 The OCOMO Encoder h 1.3 OCOMO Decoder 8 l.k Pulse Code Modulation as a Function of Time - - - - 11 2 OCOMO ENCODER, A CIRCUIT DESCRIPTION 12 2.0 Introduction -12 2.1 Audio Amplifier 12 2.2 The Horizontal Deflection Circuit --------- l6 2.3 The Vertical Deflection Circuit 18 2.k Encoder Power Supplies ---------------21 3 OCOMO DECODER, A CIRCUIT DESCRIPTION 27 3.0 Introduction -------------------- 27 3.1 Word Store Card 29 3.2 The Vertical Voltage Card 32 3.3 Horizontal Ramp and Control Card ---------- 3)+ 3.k The "Sense Amplifier" 38 3.5 The Decoding Circuitry ——————————————— U0 CONCLUSION U6 LIST OF REFERENCES kQ CHAPTER 1 GENERAL PRINCIPLES OF OCOMO 1. Introduction Optical Correlation Modulation is a scheme used to implement the encoder/ decoder section of a digital voice communication system. A one-to-one code is used so that the codewords can be optically correlated to a set of codewords, in order to obtain the original voice-signal amplitude. Figure 1.1 shows a block diagram of the system: The system converts the sampled analog signal to binary sequences with a length of 6 bits. The optical encoder maps a 6-bit sequence into a codeword with a length of 8 bits. This is done on-line. The 8-bit long codewords are then transmitted serially. Upon reception, the optical correlator compares the received codeword with (parts of) the whole set of codewords: The correlator thus remaps the codeword on-line back into the original 6-bit sequence, This sequence is then converted to the original amplitude by means of a D/A con- verter and subsequent filtering. The bandwidth of OCOMO is roughly 7-5 KHz for the voice input signal. 1. 1 Pulse Code Modulation Pulse code modulation is a digital modulation scheme in which an (analog) signal is represented, a sample at a time, by a group of digital pulses. The signal which is to be coded is sampled at a rate which is at least twice the maximum frequency of the signal (Nyquist's Theorem). This sampled signal then has its amplitude quantized: In OCOMO, 6k levels of quantization are used. Associated with each quantized level is a codeword or a train of pulses, with N pulses comprising a codeword. Since 2 or 6k levels are used in OCOMO, at least 6 bits are needed for each level. In short: PCM takes an analog signal (with a bandwidth restriction!), samples it at a fixed rate, quantizes the UJ o < jz. z O o >& i\ oc UJ PCM TO VOICE NVERT O o r\ u bO a) •H P ^ ' O o H pq o o o •H o o ><75 amplitude of the sampled signal, and then transmits a codeword associated with the quantized amplitude of the sampled signal. Let us examine why the signal must be sampled at a rate equal to twice the maximum frequency of the input voice signal, i.e. why Nyquist's Theorem must "be applied. Nyquist's Theorem states: All the information in a signal bandlimited to a frequency f is contained in a sample of the signal taken every — max e D J 2f max seconds. In a qualitative sense the theorem seems reasonable since if one samples too slowly, the signal may change "behind our hack." A more mathematical justifi- cation is readily available: Let g(t) be a signal to be sampled and let G(co) be g(t)'s Fourier trans- form. G(w) is pictured in Figure 1.2a and its bandwidth is f max Figure 1.2b shows G(w) as a periodic function. Then G(u>) = , J- Z C e (,jhaj/2f max ) lul < 2 f ■ (l-l) 4irf n ' ' - max max n=-°° /+2?rf max , . , k G(u>) e l_JM/ ^max J do) (l-2) •Zrtt max /•+2lTf I max . but g(t) = ^ I G(u>) e JWt dw (1-3) max in particular g /+2TTf G(u>) e max do, = - ■2irf "max " •/ -2irf max Thus, if one knows g(t) at times, one can reconstruct the Fourier series of G(w), and if one knows G(w), one can reconstruct g(t). If one applies the above processes, one finds that -27Tf max + 27Tf max Figure 1.2a Signal Spectrum -67Tf max -2wf max + 27Tf max + 67Tf max Figure 1.2b Periodic Signal Spectrum -6TTf max -27Tf max + 27Tf max + 67Tf max Figure 1.2c Periodic Signal Spectrum with Aliasing Figure 1.2 Spectra sin(2-irf (t - n/2f )) /.. \ v / n N max max , v g(t) = z g (- — ) -^ — (t _ n/2f — 5 — (1-5) n=-°° max max max This reconstruction of g(t) thus corresponds to_ passing the samples of g(t ) through an ideal low-pass filter with bandwidth f ! b c max Figure 1.2c shows a sampling rate of less than — . The resulting max aliasing or overlapping of the frequency spectrum waveforms will result in loss of information and therefore distortion. When sampling is done at less than the Nyquist rate, the C ' s of equation (l-U) are no longer equal to a sin- gle discrete sample, but rather they are functions of the previous samples and the next sample. Since proper reconstruction would require an anticipating filter (which is physically unrealizable), some of the information must be lost. Inherent to PCM is quantization noise, caused by quantizing the sampled signal. The RMS value of this noise is: '/- a/2 p N = (i) / M^dM = ^= (1-6) ~ £1/ c. where a is the difference in voltage between two quantization levels. The peak signal is Ma, M being the number of levels. The voltage signal to noise ratio is 2/3 M. For OCOMO, M is 6k : The signal to noise ratio is found to be 221.7. 1.2 The OCOMO Encoder Basic to all pulse code modulators is a circuit to sample and hold the desired signal, a circuit to quantize this sample, and a circuit to digitize this quantized sample. One way to accomplish the above process is to use a Tracking A/D Converter. This is a converter which varies the digital represen- tation to match the analog signal. To ensure good tracking, one must be sure that the slew rate of the A/D Converter is not exceeded by the slew rate of the signal. The maximum slew rate of the signal is given by: — - [V sin(2Trf t)] t = a multiple of — — (1-7) dt max max * f \± i / 6 In order to sample, quantize, and digitize, one only has to store the digital signal from the A/D Converter. This is the method used in OCOMO. After digitizing the sample, one could just transmit the digital repre- sentation, or one could encode it. One can encode for basically two reasons: One reason would he to add error-correction capability. The other reason would be the desire to encode the data in order to ensure secrecy. In OCOMO the latter reason predominates. One straight-forward way to encode is to use the digitized amplitude to address a codeword from a memory. If one uses a semiconductor random-access memory (RAM), the memory must always be energized, or else data must be replaced whenever the system is repowered. This problem can be avoided by using a read only memory (ROM). But an electrical ROM is generally difficult to change. A good compromise between a RAM and an electrical ROM is an optical ROM of the type used in OCOMO. This memory is programmed by placing a plastic transparency with the codeword bits in the form of opaque and transparent rectangles on a filmstrip. An example is shown in Figure 1.3. In this figure, each column is a codeword, i.e. each column is associated with a digitized amplitude. In what follows, these columns will be called codestrips. The memory works as follows. The (digitized) quantized signal is re- converted to an analog form by using a D/A converter, and this signal is used to horizontally deflect the beam of an X-Y oscilloscope. The beam is vertically deflected using a staircase generator . Visibly, when a signal is sampled, the resulting quantized voltage selects _a code strip . Then the beam is deflected so as to scan each bit position of the codeword. To reconvert to an electrical signal, a photo-detector is used. 1.3 OCOMO Decoder The basic procedure used for decoding, is to compare the received code- word with the complement of all the codewords optically. The following ID CO CL CO LU Q O O to CM 0) T3 O O o o o o H 01 •H m p"> (\j convention is made: A logical "0" corresponds to a transparent spot on the codestrip, and a "l" corresponds to an opaque spot. If a particular bit posi- tion in the received codeword is a "0", the corresponding bit position on the complementary codestrip of the received codeword will be dark. If a bit posi- tion is a "l" , the corresponding position will be transparent. If the first bit position of the received codeword is a "0" and the first bit position of the complement of all the codestrips is optically scanned, some of the code- strips, including the one associated with the codeword, will not pass light. If every bit position of the received codeword which has a "0" is similarly scanned, the strip corresponding to the codeword will not pass any light. In order for the above correlation scheme to unambiguously decode, every codeword must have its "0"'s placed so that when the procedure is performed, only the codestrip associated with the codeword does not pass light. Using the above decoding scheme puts certain restrictions on the code. The "all-O-bit" codeword cannot be used because its complementary codestrip would be opaque, and therefore would never pass any light! Thus it would always be decoded as a received word! If we want 6k codewords, we would need at least 7 bits. If one of the 7 bit codewords had one "0" and six "l" ' s, when decoding, only one row would be scanned: To differentiate this word from the other 63, a transparent spot would be required in the corresponding bit of the other 63 words. Thus, these other words would have only 6 independent bits. Now in order to get 63 words from 6 bits, at least one of the words would have only one "0" and five "l"'s. But then this would allow at most 5 independent bits and we could not find enough words. In other words: All words with a single "0" must be excluded . Similar reasoning shows that words with two "0 n, s and five "l'"s must also be excluded. If we use 7 bit codewords with three •7 "0"'s, we have (' ) = 35 decodable codewords. If one tries to include codewords with four "0"'s, a decoding ambiguity will arise. There are (, ) = 35 codewords with four "0"'s. For every four-"0"-codeword in the set, there are ( ) = four three- "0"-codewords whose "0" positions match the "0" positions of the four-"0"- word. If such a four-" 0" -word is received, the decoding scheme will determine that the four-"0"-word and any of the matching three-" 0"-words in the set is the word received. If any four-"0" word is entered into the set of codewords, four of the three-"0"-words must he eliminated. If a second four-"0"-word is added, at least three more three-"0"-words are eliminated. Every other four- "0"-word added, eliminates at least one new three-"0"-word, until all the three-"0"-words have been eliminated. Adding three-"0"-words and eliminating four-" 0" -words leads to the same result. Thus, fewer codewords result from combining the three and four "0" words than not combining the groups! It has thus been shown that the all-"0" ' s-codeword cannot be used, as well as the codewords with one "0" or two "0"'s. Also, it has been proved that the three-"0"-codewords and four-"0 ,r -codewords cannot be used together. This 7 7 7 7 eliminates the following number of codewords: (') + () + (') + () = 6k. This leaves us with at most 6U usable codewords. But the all-"l"-codeword cannot be used either, because this word would cause all of the bit positions to be scanned. (This word could be used if it were assigned to a constant level or special hardware were added to change its level, but this would defeat the ease of changing codeword to level assignments which is the main advantage in using an optical ROM). Therefore, codewords 8 bits long are used. If 8 bits are used, a set of codewords with four "0"'s can be used with the OCOMO decoding scheme. First, (« ) = 70 codewords are available. The scheme works, because checking the four "0'"s of the received word will differentiate the complementary strip associated with the received word from the other com- plementary strips. This can be shown as follows. Since the complement of "0" is an opaque spot, the strip associated with the received word will pass no light. Every other strip must pass light because some of the four "0"'s or 10 opaque spots of every other codeword strip must be in different positions: For if all the positions matched, it would have to "be an identical strip. The exact decoding procedure used in 0C0M0 is as follows. There are 6k flipflops associated in a one-to-one correspondence with the 6k codestrips. After receiving a codeword, each row corresponding to a "0" bit position is scanned. Before any strips are scanned, all 6k flipflops are initialized to the "l"-state. As each strip is scanned, the appropriate flipflop is enabled if light passes from the particular strip. The circuitry is designed so that if a particular strip passes light more than once, the appropriate flipflop changes state only once. After all k x 6k positions are checked, one flip- flop will be in the initialized state and the other 63 will have changed state. Thus , the received codeword is associated with the flipflop which has not changed . Using a 1 of 6k to 6 encoder, a buffer, a D/A converter and a filter, we complete the decoding. A refinement of the above decoding procedure was conceived after 0C0M0 had been built. This decoding scheme places no restrictions on the code, so that 6 bits would be sufficient for 6k codewords. The scheme is as follows: After receiving the 6-bit codeword, the decoder checks the codestrips, codeword by codeword. A particular codeword is checked until there is a discrepancy between the received word and the codestrip: If each codestrip is arranged in the order that it was at the encoder , one merely has to keep track of the number of codestrips that were checked prior to finding the matching codestrip! This second scheme actually requires less checking of codestrip bit positions than the first. The first method required k x 6k = 256 checks. The second method requires only 126 checks in the worst case; this worst case occuring when the received codeword corresponds to 6k. Thus all codestrips must be checked at least once. More precisely: The first bit of the 6k code- words must be checked; of these 32 will agree with the received codeword. 11 Therefore, the second bit must be checked for 32 of the codestrips. Similarily the third bit of l6 strips must be checked, etc. So, in the worst case 6k+32+l6+Q+h+2= 126 positions must be checked. l.U Pulse Code Modulation as a Function of Time There is a straight-forward way to make the quantized signal which selects the codeword to be transmitted as an implicit function of time: One can keep a running M0DUL0-6H-sum of the PCM codewords, and this (newly updated) sum can select the codeword to be transmitted! At the decoder, the PCM level decoded will actually represent the sum: If the previous sum is known, the latest PCM level can be found by subtracting the old sum from the new sum. In this way the one-to-one correspondence between the PCM signal and the OCOMO code- words varies, depending on what the input voice signal to be coded is. Since this signal is a function of time, the mapping of the PCM codeword to the OCOMO codeword is an implicit function of time. This scheme was not implemented. 12 CHAPTER 2 OCOMO ENCODER, A CIRCUIT DESCRIPTION 2.0 Introduction The Block diagram of the OCOMO Encoder is shown in Figure 2.1. The audio amplifier has an Automatic Gain Control (AGC) to ensure that the quanti- zation range of the A/D Converter is not exceeded. The output of the Tracking A/D Converter is sampled and stored in the digital Sample and Hold, which serves as a "buffer register. (The output of the D/A is the quantized, sampled represen- tation of the input signal! ) When applied to the horizontal section of the CRT, this voltage selects one of 6k codestrips placed on the CRT. The synchronized staircase generator then deflects the beam past the bits of the code strip. The light output is detected by a photomultiplier tube, and its (digital) electric output is transmitted. Figure 2.2 shows a set of 6h codestrips as they are arranged on the face of the CRT. 2.1 Audio Amplifier Figure 2.3 shows the audio amplifier circuit. The input signal enters the circuit through a unity-gain buffer. Op Amp 1 is used to amplify the signal to a peak amplitude of 1 to 2 volts. The AGC circuit controls the gain by vary- ing the operating point of the four diodes at the input of Op Amp 2. This Op Amp is used to reamplify the signal^and the differential inputs are connected so that the voltage setting the operating point of the diodes produces a common mode. The circuitry after the stage described above is used to rectify and integrate the signal. The output of the Integrator sets the operating point of the diodes. The transistor is used for current gain. The lOK-pot in the In- tegrator amplifier determines the no-signal operating point of the diodes. Op Amp 3 is used to set the peak-to-peak amplitude of the signal to 10 volts, the quantization range of the Tracking A/D Converter. 13 03 •H Q u o H pq U 0) •a o o a H CJ 0) fa lU w P< •H ^ -P CQ 0) C/> o 0_ o Jn q^ o I- o (/> o 111 o Q O CM O CM 0) to ^ CM a. E-4 If) — o (D m ro cvj OQ t-4 \— c/> 15 CJ •H o > o o w on OJ CD U bO •H 16 2.2 The Horizontal Deflection Circuit Figure 2.k shows the circuitry for the Tracking A/D Converter, the digital sample and hold, and the D/A Converter for driving the horizontal deflec- tion amplifier of the CRT. The input stage of the Tracking A/D Converter is used as a DC level shift and buffer. The D/A Converter sinks current from the buffered input signal. The 72510 Voltage Comparators monitor the voltage drop from the k."JK + variable IK resistor. The difference in voltage between the number 3 pin of each 72510 is set to be one quantization level, which is V max level N n level The V , the maximum quantization level is 10 volts. The N n _ , the number of max level levels, is 6k. In this converter Q = 10 /6k = .156 volt. Pin 3 of the upper com- parator is set at +.078 volt. The other Pin 3 is at -.078 volt. The A/D Converter is designed to keep the voltage at pin 2 of the com- parators between +_. 078 volt. If the voltage is above .078v, the 7^191 counters count down. This increases the current that the MC 1^06 D/A sinks. If the vol- tage is between +_. 078, the counters are disabled. If the voltage is below -.078 volts, the counters count up and thereby decrease the current the D/A sinks. The maximum slew rate of the A/D Converter is: Q lever T clock where T n n is the period of the clock driving the counters. Since the clock clock r functions at 3 MHz, T n . is .33 us. Therefore, the slew rate is clock -^If x 10" 6 = .U68 v/ys The maximum slew rate of the input signal is the derivative of the signal at the maximum voltage and frequency or: 17 > 1 L ♦ ° ' " |i< ! f * o m - N V K 2 ** x (D » a a - H >• :i 10 5; Hi' -P u o o e ■H M v C\J at 18 [5 sin (2tt x 7-5 x 10 3 t)] = 5(2tt x 7.5 x 10 ) volts/sec 2.36 x 10 5 volts/sec = 0.236 volts/ys Therefore, the A/D Converter can track the input signal. The signal is then samplea ana heia digitally. This avoids the cost ana error introaucea "by an analog sample ana hoia circuit. The quantize! samplea ana storea aigital representation of the input signal is then reconvertea to an analog voltage in oraer to select a coaestrip in the optical ROM. 2.3 The Vertical Deflection Circuit Figure 2.5 contains the vertical aeflection circuit, the optical ROM output processor, ana the control signals for the vertical ana horizontal ae- flection circuits. Figure 2.6 shows the vertical def lection voltage, the hori- zontal control signal, a possible output sequence using the combined sync signal, and the clock signal. The vertical deflection voltage is generated by converting the digital output of a counter to an analog voltage. The main system clock drives the coun- ter. Note that the counter converges to the desired state without regard to the initial state: When the counter reaches a maximum (minimum) of all "l"'s (all "0"'s), the Q output of the JK flipflop goes to a "l" on the next falling edge of the clock. This disables the counter for one clock pulse. It also loads in the value "1110" ("0001") into the counter. This loading changes the airection of counting. After the clock perioa, the Q of the flipflop goes to "0". The counter then counts lown (up) to "0000" ("llll"), ana the process reoccurs. Only the lower 3 oraer bits of the counter are usea in the conversion to the analog voltage. The horizontal control pulse is generatea by the NAND of Q ana the in- verse of the MAX/MIN output of the counter. The length of the control pulse is set by a monostable. u to 85 5 a y a: * u • • © 1 3 S " 3 » Hi' d (S) ®^ 2 &* ,r £jl ©«< :> *o — w. • V^\- 1| rQr 8- 8- I 1 T3 o o •H ■P O a; H OJ UJ CC O tO UJ Hi ±; ?uj 2 O o UJ CD CO CO O Q_ DO qUJ u CO o o _j o ^ UJ CO _l 0. o z >- CO bo •H ■H EH U > > 21 Figure 2.7 shows the circuit for the 931A photomultiplier tube. The phosphor for the encoder CRT is P2H. Its persistence fall time is about 1.5 ys. Since the audio signal to be coded is band limited to 7-5 KHz, the sampling rate must occur at a frequency of at least 15 KHz or about once every 6k ys. This in 6h ys , 8 bits must be read out of the ROM or 1 bit in 8 ys. Thus, the persistence time is acceptable. The anode of the photomultiplier tube sinks current: The cur- rent is converted to a voltage using a resistor; since the data rate is relatively slow, this is acceptable. This voltage is then digitized using a comparator. There are two modes of synchronizing the encoder to the decoder. One mode is to use a particular state of the vertical counter: The value we chose is binary 3. The other mode is to combine the sync signal with the data from the optical ROM. In this mode the sync signal is combined by raising the data voltage above the normal "l" voltage by two volts. The sync signal can then be combined only if the data is in a "l" state, so as to avoid entering a false "l" into the data to be transmitted. A third condition can be added to the transmission of a sync pulse. Namely, that monostable A be in the untriggered state. This mono- stable is triggered after each sync pulse is sent : When this third condition is added, the approximate frequency of sync pulses can be controlled, because there is no guarantee that the data will be in the "l" state when the other conditions for sending a sync pulse are met. The sync signal is combined with the data by changing the DC supply voltage of a differential amplifier. When the sync pulse is added, the supply voltage is raised 2 volts. The output of the differential amplifier is then connected to a transistor used as a transmission line driver. 2.k Encoder Power Supplies Figure 2.8 shows the -1050 volt power supply used to operate the photo- multiplier tube. The supply is a basic series transistor regulator. The design output current is 10 ma. The normal operating current is approximately 5 ma. ; At 5 ma of current, the output tipple is .15 volt peak to peak. + 5V 22 ANODE CATHODE 30K 27K 27K 27K 27K 27K 27K 27 K 27 K IK .25 Watt + » CODED DATA T ZZ .005 h* ■it 1 27K ZZ .005 fLf T .005 /if -1050 V 931 A ALL RESISTORS 1W, 5% CARBON UNLESS OTHERWISE SPECIFIED Figure 2.7 Photomultiplier Circuit 23 > O m o p Pi CO a; Js o p., d; •H H Pi •H P H S O P. a) CM a; Jh ."! U •H 2h Figure 2.9 shows the 5 volt power supply used in OCOMO. It is a straight- forward use of a LM 309 5 volt output regulator. The maximum output current is 2.0 amp. A regulated 12 volt supply furnishes the input voltage. The LM 309 was used to isolate the two power supplies. Figure 2.10 shows the -6 volt supply. Duplicate photomultiplier , 5, and -6 volt power supplies are used in the OCOMO Decoder. 25 H ft ft CO -p H o > o\ CM 3 bO •H > CVJ 26 > CM m in CM Id Qu E < CM > -XL CM H ft ft 02 O > VD I o H CM 0) •H 27 CHAPTER 3 OCOMO DECODER, A CIRCUIT DESCRIPTION 3.0 Introduction The OCOMO Decoder "block diagram is shown in Figure 3.1. As a word is being received, the position of the first "0" is stored. When the previ- ous word has been decoded, this position is loaded into a register for con- version into an analog voltage. This voltage is then applied to the vertical deflection plates of the CRT. As the first row is scanned, the position of the next "0" is found. The horizontal deflection voltage is a ramp, synchro- nized to the vertical deflection voltage. (A ramp was used in place of a staircase because the D/A Converter required for this type of staircase cir- cuit is very expensive)! The decoder operates with a one codeword delay. As a new word is being received, the previous word is decoded: That is, the codeword is reassociated with its PCM level by optical correlation. The delay of 6h ys is used because of an improvement in performance over no delay in decoding. With no delay, the longest time available for scanning a row is 10 ys. Every codeword has four "0"'s and four "l"'s. The rows of the codestrips correspond- ing to the bit positions of the "0"'s in the codeword are scanned for decoding. If the "0"'s are in the last four positions, the scanning of the four rows could begin after the fourth "l" is received. This allows about Uo ys to scan the four rows, and therefore 156 ns for each bit in a row. The shortest persistence fall time of a readily available CRT phosphor is about 120 ns. If the no delay procedure is used, there would be an interval of 30 - Uo ns in which the data would be reliable. Such a requirement would necessitate tight specifications for other sub-systems in the decoder. When considering extra cost, lack of real benefit with a no delay procedure, and poorer performance, a one codeword delay is the obvious answer. 28 WORD STORE "0" BIT POSITION DETECTOR AND STORE D/A UA 1 A * i \ CONTROL VERTICAL OEFLECTION 1 ! RAMP GENERATOR HORIZONTA DEFLECTIO L :rt ' LIGHT OUTPUT ! PHOTO DETECTOR 1 r •> "«* ENSE AMPLIFIER" \ ( 1 TO 64 MULTIPLEXER AND CODESTRIP FLIP-FLOPS r' ' \ 1 OF 64 TO 6 CODER J ' v ) ■ V V 1 rlM 1 w auu V ■ L 4 Figure 3.1 Encoder Block Diagram 29 The photodetector to sense the light from the CRT is a photomultiplier tube. The "sense amplifier" consists of a TTL gate and a flipflop controlled "by the system clock to store the data between clock pulses. The photomulti- plier acts as a current switch to turn the TTL gate on and off. Associated with each of the 6k codestrips is a flipflop. When decod- ing begins, each flipflop is initialized. When the beam is behind the code- strip associated with a particular flipflop, the flipflop is enabled, and changes state if light is detected . After all four rows are scanned, only one of the 6h flipflops is in the initial state! Each flipflop is numbered between and 63. After decoding, the flipflop in the initialized state has its number converted to a 6-bit representation by a l-of-6U- to-6-coder. This 6-bit number is stored and converted to an analog signal. After filter- ing, the signal is then amplified to drive a speaker. 3.1 Word Store Card The Word Store Card circuit is shown in Figure 3-2. There are two modes of codeword synchronization as discussed in section 2.3. If the sync is combined with the data, two 72510 voltage comparators are used. One is always used to determine the incoming data bit state. The other comparator discrimi- nates the sync from the data by checking for pulses 2 volts above the normal "l" data level. The other mode uses a sync pulse on a separate line: When a sync pulse is received by either method, the Word Counter is loaded with "1101". The choice of the 2 bit as "l" is arbitrary, since it assigns the count-up mode of the encoder staircase generator to this value. The three lower order bits are determined by the sync pulse occurring during the binary "100" bit position of the codeword. The binary number "101" is loaded into the lower three bits of the counter since the counter is not loaded until the clock pulse occurring during the binary "101" bit position of the codeword. 30 31 Register A is used as a serial-to-parallel-converter. Since the order of the bits changes direction every codeword, the direction of Register A's shifting is changed. The highest order bit of the Word Counter deter- mines the direction of shifting. After the last bit is received, the new word is loaded into Register B. As the new codeword is being received in Register A, the lowest valued "l" position is stored in the Initial Store Flipflops. (The "l" posi- tion is actually a "0" position since the inverse of the received word is shifted in Register A! ) Since the direction of the bits changes every other codeword, some complications arise in storing the lowest valued "l" position. If the bits occur in increasing order, the first "l" position must be stored, and the Word Counter then contains the value of the bit position. If the bits occur in decreasing order, the last "l" position must be stored, and the Word Counter now contains the bit -by-bit inverse of the position . When the bits are increasing, only the first "l" generates an Initial Load pulse. Otherwise each of four "l" positions generates an Initial Load pulse. These pulses are generated on the Vertical Voltage Card described in the next sec- tion. The inversion of the bits is done with two-input EXCLUSIVE-OR gates. If the bits are increasing, one input of each EXCLUSIVE-OR gate is at "0". The other input comes from the Word Counter. Thus, the bits are not inverted. If the bits are decreasing, the common input is one, and the bits will be in- verted. After the new codeword is loaded in Register B and the lowest valued "l" position is loaded into a register on the Vertical Voltage Card, the next l" position must be found. This is accomplished by shifting the B Register. The first "l" position is ignored and the register is shifted until the next 1 appears at the Decode Detector, the signal which controls the shifting circuitry on the Vertical Voltage Card. After the second position is 32 transferred, the next "l" position is found "by shifting. Similarly, the fourth "1" is found. 3.2 The Vertical Voltage Card The circuit for the Vertical Voltage Card is shown in Figure 3.3. The Initial Load signal, which loads the lowest order "l" position on the Word Store Card, is generated by the AND of the Data Bit signal and the de- layed positive edge of the Main Clock from the encoder. The AND of the two signals is used to ensure that the Word Counter on the Word Store Card has settled before bits are stored. If the Direction Compensation signal is low, all four of the "l" bits of the incoming word produce Initial Load pulses. If the Direction Compensation signal is a "l", only the first "l" produces a pulse. This Initial Load pulse changes the state of a flip flop which then inhibits the signal until the next decoding cycle. After decoding a word, the Vertical Counter is loaded with the lowest valued "l" position of the word just received. Shortly after this, the End of Row Decode signal causes the number stored in the counter to be loaded into the Vertical Store Flipflops. The outputs of the flipflops are converted to an analog signal and applied to the vertical deflection amplifier of the CRT. This determines the first row of the codestrips to be scanned. While the row is scanned, the Controlled Decode Clock shifts Register B of the Word Store Card. When the first "l" occurs at the Decode Detector, the clock to the Vertical Counter is enabled as one of the 7^+73 flipflops changes state. Regis- ter B is shifted until the next "l" occurs. The Vertical Counter then con- tains the position of this "l" , and the Controlled Decode Clock is inhibited. At the end of the scanning, the contents of the Vertical Counter are trans- ferred to the Vertical Store Flipflops for D/A conversion. The Controlled Decode Clock is enabled by the falling edge of the End of Row Decode signal. 33 < o o u 2* ,© Hi' o * p - * « :®. a p •» *""©„ go Ld O uj 4 3 " 2 Xd o-WV-vJvl- © 1 — IHi' Hi' £*r 5 © n Hi< *s g U UJ a a 5 S ni o a) bo aJ -P H o > CI ■H QJ on s, •H 3^ The clock continues until the third "l" is found, and the same process occurs as for the second "l". The same procedure is used for the fourth "l". 3.3 Horizontal Ramp and Control Card The circuit diagram for this card is shown in Figure 3.1+, and key waveforms are depicted in Figures 3.5 and 3.6. Figure 3-5 shows the wave- forms during the length of 2 codewords. Figure 3.6 shows the waveforms during one Horizontal Ramp. In Figure 3.6 there are waveforms labeled clock D and D' : The Clock D waveform applies during the first 3 Horizontal Ramps; Clock D' applies during the fourth Horizontal Ramp. The falling edge of the End of Word signal marks the end of the code- word just received and the beginning of a new codeword. The rising edge of the Decode Start signal causes the discharging of the Horizontal Ramp generat- ing capacitor. The rising edge of the Delayed Decode Start signal initializes the circuit and starts the Decode Clock. The Horizontal Counters count from to 63. When the counter reaches 63, the MAX/MIN signals of the counters become "l"'s since the two highest order bits are initially loaded as "l"'s. The Q output of the Delay F.F. becomes a "l" after the falling edge of the next Decode Clock pulse. This inhibits the counters and generates an End of Row Decode pulse. This End of Row Decode pulse stops the charging of the ramp generating capacitor. After a one monostable triggering delay, the dis- charging of the capacitor begins. After a delay of about 5 clock pulses, the positive edge of the Q flipflop appears at the output of the AND Gate Delay and loads the counter to the "11000000" state. This causes the MAX/MIN sig- nal of the higher order bit counter to become a "0". On the next falling edge of the clock, the Q of the Delay F.F. becomes a "0" and enables the Horizon- tal Counters. Also, the negative edge of Q increments a two bit counter. The delay of five clock pulses, about 1.25 ys, is needed to ensure the vertical 35 sr s * r- Hi' > * H. c* s © - S B » ob Hi- > H* ©> 5 > 2 © J S Bfc Hi' Hi- z 3 © 3* jf 3 3 — ^J 08 5gE Q O (j 8 5€ 8* 3 i 5 © 3*h 1 -, --~ 3 a 2 5 © 5 d ft 5 !! 2 UJ? A5v» O H O G O o ph -P G o •H o 00 (IJ 36 END OF WORD DECODE START DELAYED DECODE START END OF DECODE END OF ROW DECODE HORIZONTAL DEFLECTION VOLTAGE 0123456776543210 BIT POSITION NUMBER TYPICAL DATA SEQUENCE RESULTANT VERTICAL DEFLECTION VOLTAGE Figure 3.5 Decoder Waveforms CD 37 o o _i o o o o o < — < E o Cm CO % W •H Ti O O (D Q m D 'J •H 38 D/A and related circuitry has settled. The same cycle occurs 3 more times during the decoding of the codeword. At the end of the fourth cycle, the two bit counter is in the "ll" state. When Q of the Delay F.F. becomes a "l" at the end of the fourth cycle, the End of Decode signal becomes a "l" and inhibits the Decode Clock. The Horizontal Ramp continues to rise until the leading edge of the Decode Start signal occurs; this causes the End of Row Decode signal to become a "l". The leading edge of the Delayed Decode signal starts the first of four cycles. The Horizontal Ramp generator consists of a MPF102 FET, used as a constant current source to charge a capacitor. The horizontal deflection voltage is generated by controlling the current to the current source. In charging, the current from the source is integrated by the capacitor. In discharging, the current to the source is turned off, and a transistor dis- charges the capacitor. The output is taken directly from the capacitor, since it goes into a high input impedance oscilloscope amplifier. The last two waveforms of Figure 3-5 depict a typical data sequence and the resultant vertical deflection voltage. The vertical voltage during the first codeword is the result from the previous codeword (which is not shown in this figure). The output during the second codeword is the result from the first codeword shown. Since there are "0"'s in the first, second, fifth and sixth bit positions, the vertical deflection voltage waveform de- flects the beam behind the first, second, fifth and sixth rows of the code- strip mask. 3.k The "Sense Amplifier" The "sense amplifier" circuit converts the current pulses of the photo- multiplier tube into a digital voltage. The digital voltage is then stored during the center of the current pulses with a flipflop. The circuit diagram is shown in Figure 3.7- 39 ANODE DECODE CLOCK DATA INHIBIT CATHODE H, W>->>-M>^ 3of6 74H04 INVERTERS ^7404 1 « |30K ~ L 1 = 005 >xf -±r |27K - .005 ^f izTK = .005 /if |27K <27K |27K <27K ALL RESIS | 27K UNLESS | 27K 27K > > UNLESS OTHERWISE SPECIFIED PRESET '/ z 7474 CLOCK CLEAR DECODE DATA -1050 V 931 A Figure 3.7 Encoder Phot omul tiplier and "Sense Amplifier" Ho The photomultiplier tube is an RCA 931A. The maximum average anode current of this tube is 1 ma. The current risetime of the anode current is 2 ns. A high speed TTL gate input puts out a current of 2 ma. Since half of the codestrip positions pass light, the average current the photomulti- plier would sink from a high speed TTL gate is 1 ma. Also, since the TTL gate has good noise immunity and speed characteristics, it makes an ideal "interface" between the photomultiplier tube and TTL logic. The amplitude and DC level of the Horizontal Ramp is adjusted so that the CRT beam is in the center of an opaque or transparent rectangle of a code- strip when the Decode Clock makes a positive transition: This adjustment makes the data most reliable, since the effects of drift or non-linearity are mini- mized. The data from the "sense amplifier" is stored at the most "reliable time," so as to optimize performance. The data is stored by activating the preset or clear of the 7^-7^ flipflop. The flipflop can change state only if the Data Inhibit line is in the inactive state ("l") and the Decode Clock is "l". If the above two conditions are met, and no light activates the photo- ■ multiplier tube, the preset is activated. If light is present, the clear is activated. The Data Inhibit signal is used to stop the flipflop from changing during the first three falling edges of the Horizontal Ramp occurring in de- coding a codeword. The flipflop does not change state on the falling edge of the ramp prior to the start of decoding because the Decode Clock signal is a "0" after decoding is completed. 3-5 The Decoding Circuitry Decoding is achieved by scanning the rows of the codestrips as deter- mined by a received codeword. This scanning of the rows reassociates the received word with its PCM level: The codestrip associated with the received word will pass no light. Associated with each codestrip is a flipflop. After the associated codestrip flipflop is found, the proper PCM level is generated Ill and a PCM to analog conversion completes the decoding. Figure 3.8 shows one of four identical circuits which contain l6 codestrip flipflops and a l-of-l6- to-U coder. The F.F. Clear signal, a 200 ns pulse triggered by the rising edge of the Decode Start signal, clears all the codestrip flipflops just prior to the start of decoding. The 7^-15^ H-to-l6 multiplexer is controlled by the Decode Clock. One of l6 lines is selected by the four bits of the lower order Hori- zontal Counter of the Horizontal Voltage card. One of the four circuits is selected by Clock A, B, C, or D. In order for a Q of a particular codestrip flipflop to make a positive transition, the particular Clock A, B, C, or D must be a "0", the Decode Data signal must be a "0", and the 1 of l6 lines associated with this particular flipflop must be selected. These conditions correspond to light passing through the codestrip associated with the flip- flop. The flipflop is connected in the following manner: The lines of the multiplexer are connected to the clock inputs of the 7^73 dual JK flipflops. The J's are at "l" and the K's are at "0". If the multiplexer line makes a negative transition, the Q of that flipflop will be a "l". After decoding, one of the codestrip flipflops will have its Q _in the "0" state because its clock never received a_ falling edge . The l-or-6i+-to-6 encoding then begins on the Codestrip Flipflop Card. On each of the cards is a l-of-l6-to-U coder; a minimal package court is achieved by using 8-input- NAND gates for the coder. The Q's of the codestrip flipflops are connected to the inputs of the appropriate NAND gates, in order to generate the bit-by- bit inverse of the binary number which selects the line associated with the particular Q. For example, if the Q associated with the "0000" line is a "0", the outputs of the k NAND gates will be "llll". The final encoding is completed by the 20-to-6 Coder circuit of Figure 3-9- In this circuit the k NAND gate outputs of each of the four k2 MINIM © I I I I II II II II I I © nrn ®®©@©©@® 6 © ©- © ff> ^-^ y> 2 « r 2 m 0-0 Hi' 4^ e ®- © Hi' n Bl- c „ ©-a " « 0— •> • 4^r ©- ©- » © o —ft II' (A m * m eg Ml © 4>r ©-' © . B— a « li 2 ; _ ^ K * _o* ®-a K 3i°<^}n-?i<^r 9 r I3Hi' & o ft o H Cm ft ■H H ft ■H -P w 0) o o CO on *H w ■H fin A A A A A A 8 IS U3 D2 1 >^ _L^, 2 0DD 1°^ 2 1DD A ^ 22DD L ^ 23DD BAl's > CAl's > D2 3 > DAl's > A)®y ^2 5DD Figure 3-9 20-to-6 Coder kk identical circuits are combined to determine the four lower order "bits. The upper two bits are determined by which one of the four cards contains a Q in the "0" state. A U-input NOR gate is used to combine the four lower order bits. The letter prefixes of the inputs signify which of the four circuit cards the input comes from. Since only the inputs from the card with a Q in the "0" state can be a "l", the inputs from this circuit card determine the four lower order bits. The NOR gates again perform the bit-by-bit inversion of the NAND outputs. The same idea is used to determine the upper two bits, but there is an added complication: Since the "0000" NAND gate output cor- responding to the "llll" line would be undetected, the (B, C or D) l's signal must be included. This coding of the two higher order bits is accomplished by NORing the NAND outputs from one circuit card. The output of the NOR is NANDed with the (B, C or D) l's signal. The output of the NAND will be a "l" only if there is a Q in the initialized state on the related circuit card. The output of the NAND gates are then connected to OR gates in order to gener- ate the proper output. Now the received codeword has been reassociated with its PCM level. This PCM signal is then converted to an analog signal using the circuit of Figure 3.10. The 6-bit PCM signal is loaded by the delayed rising edge of the End of Decode signal into the 7^198 shift-register. This signal is then converted to an analog signal by an MC lU06 D/A Converter, and the analog signal is then filtered by a low-pass active filter. An audio amplifier drives the speaker. i+5 -p u 0) > o o o -p 2 u PL, o H on ■H U6 CONCLUSIONS Oq There are 6hl permutions or about 1.27 x 10 different arrangements o of a set of 6h codewords. Since there are (, ) = 70 different possible code- 70 ft words, there are (/-^) or about 'J. 6 x 10 different sets of codewords. This gives : Qq Q qQ 1.27 x 10. code/set x "J. 6 x 10 sets or about 10 possible codes ! Since the order of the transmission of data bits reverses after each code- word at the encoder, one of two different codes is used for asymmetric code- words. Here "symmetric" means that the first four bits are the mirror image of the last four. One of two different codes is used for asymmetric code- words because the same PCM level appears to have one of two codewords depen- ding on the direction of the transmitted data bits: There are ( ) =6 sym- metric codewords in the set of 70, therefore, any one set containing 6h codewords would have between 91% to 100% asymmetric codewords. If one makes the PCM-level-to-codeword correspondence a function of time, as described in / 89 section 1.3 (which is equivalent to choosing 1 of 1.27 x 10 different codes for each codeword transmitted) it can be seen that deciphering the 0C0M0 code is a formidable task! The optical ROM's at the decoder and encoder were designed to be basically the same. If one assembles the necessary circuitry for the en- coder and decoder, one could use the same ROM for coding and decoding. This could be done by switching-in the vertical and horizontal waveforms of the encoding circuitry to code on-line. To decode, we would switch-in the decode waveforms . The bit rate of the decode optical ROM is near its maximum, about four million bits/sec. If one wanted to increase the bandwidth of the input ^7 signal, this optical memory could be used provided a different decoding scheme is employed. For example, one could decode "by using a look-up scheme and still maintain the advantages of the optical ROM. This would increase the sample rate and therefore the bandwidth by a factor of k3 for the present bit rate, since six versus 256 bits would be read out of the memory for each codeword. The main advantage of the optical ROM used in OCOMO is that the in- formation in the memory can be changed simply, compared to an electrical ROM. One way to change the contents of the ROM would be to have the codestrips stored on spools much like many cameras store film. One could then arrange the codestrips, so the ROM information could be changed by turning the spools in synchronism at the encoder and decoder. The strips could be placed, so that the code mask could be moved one or more codestrips across the face of the CRT.. . In conclusion, the optical ROM used in OCOMO provides flexibility and speed not available in other types of memories. U8 LIST OF REFERENCES 1. Carlson, A. B. , Communication Systems: An Introduction to Signals and Noise in Electrical Communication . McGraw Hill Book Company, 1968. 2. Embinder, J., Fet Applications Handbook . Tab Books, 1970. 3. Schwartz, M. , Information Transmission, Modulation, and Noise . McGraw Hill Book Company, 2nd ed. , 1970. k. RCA Electron Tube Handbook , Radio Corporation of America. Harrison, New Jersey. 5. Photomultiplier Manual , Radio Corporation of America, 1970. 6. The Integrated Circuits Catalog , Texas Instruments, Incorporated. UNCLASSIFIED Security Classification DOCUMENT CONTROL DATA • R&D (Security classification of title, body ot abstract and indexing annotation must be entered when the overall report is classified) 1. ORIGINATING ACTIVITY (Corporate author) Department of Computer Science University of Illinois at Urbana-Champaign Urbana, Illinois 6l801 2a. REPORT SECURITY CLASSIFICATION Unclassified 2b GROUP 3. REPORT TITLE OCOMO: OPTICAL CORRELATION MODULATION 4. DESCRIPTIVE NOTES (Type of report and Inclusive dates) Master's Thesis, Technical Report March, 197^- 5. AUTHORfS,) (Last name, first name, initial) Budzinski, Robert L. 6 REPORT DATE March, 197^ la- TOTAL NO. OF PAGES 7 6 NO. OF REFS 6 8fl. CONTRACT OR GRANT NO. N000 1U-67-A-0305-0007 b. PROJECT NO. 9«. ORIGINATOR'S REPORT NUMBERfS.) 9 6. OTHER REPORT NO(S) (A ny other numbers that may be assigned this report) 10. AVAILABILITY/LIMITATION NOTICES 11. SUPPLEMENTARY NOTES 13 ABSTRACT 12 SPONSORING MILITARY ACTIVITY Office of Naval Research 219 South Dearborn Street Chicago, Illinois 6060U An optical read only memory is used to digitally encode a pulse code modulated voice signal. Decoding is accomplished by using an optical read only memory to correlate the received code- word with the set of codewords. )D /A™ 1473 UNCLASSIFIED Security Classification 1IBLI0GRAPHIC DATA HEET 1. Report No. UIUCDCS-R-71+-631 3. Recipient's Accession No. . Title and Subtitle OCOMO: OPTICAL CORRELATION MODULATION 5. Report Date March, 197I+ Author(s) Robert L. Budzinski 8. Performing Organization Rept. No -UIUCDCS-R-7l+-631 Performing Organization Name and Address Department of Computer Science University of Illinois at Urbana-Champaign Urbana, Illinois 618OI 10. Project/Task/Work Unit No. 11. Contract /Grant No. N000 11+-67-A-0305-007 2. Sponsoring Organization Name and Address Office of Naval Research 219 South Dearborn Street Chicago, Illinois 6060U 13. Type of Report & Period Covered Technical 14. 5. Supplementary Notes 6. Abstracts An optical read only memory is used to digitally encode a pulse code modulated voice signal. Decoding is accomplished by using an optical read only memory to correlate the received code- word with the set of codewords. 7. Key Words and Document Analysis. 17a. Descriptors Private communication Pulse code modulation Optical read only memory 7b. Identifiers/Open-Ended Terms 7c. COSATI Field/Group 1. Availability Statement Unlimited distribution 19. Security Class (This Report) UNCLASSIFIED 20. Security Class (Thi Page UNCLASSIFIED 21. No. of Pages 22. >"M NTIS-35 (10-70) USCOMM-DC 40329-P71 1? » v « tf en 5»* s&