LIBRARY OF THE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN 510 SA vm.o.V5>VS40 cop. & CENTRAL ORCUIAT'ON l-g" the library * ro « *£££,» Date stamped on ° r ^ may be Gorged « minimum belOW , SS ?oC each lost book. fee of $75.ow "»■ reoson> SEP 16 199* «*p new due date below Wten renewing by Phone, -nte new d ^ previous due date. Digitized by the Internet Archive in 2013 http://archive.org/details/realizationofweb539bond Wa. 53? ^ '#%%•> UIUCDCS-R-72-539 COO-2118-0036 Realization of the WEB Language By William D. Bond and Edward S. Davidson August 1972 C00-211 8-0036 UIUCDCS-R-72-539 Realization of the WEB Language By William D. Bond and Edward S. Davidson Department of Computer Science University of Illinois Urbana, Illinois 6l801 This work was supported in part by Contract AT(ll-l)-21l8 with the U.S. Atomic Energy Commission. 1. INTRODUCTION The purpose of this file note is to specify the various subprocesses involved in processing a WEB description of the logical elements in a digital assembly. A knowledge of WEB, the language in which an assembly may be described, is assumed. This language is specified fully in the following file notes and reports: Report : 2l+3 Hazelhurst, J.H. , McCormick, B.H. , Bond, W.D. , "The WEB System, Part I: The Utilization of WEB," September 11, 1967. 232 Bond, W.D., Davidson, E.S., McCormick, B.H. , "The WEB System, Part II: A Formal Description of the WEB Input Language," June 19, 1967. 233 Bond, W.D. , "The WEB System, Part III: WEB Change Orders," June 19, 1967. File Number: 719 Bond, W.D. , "A User's Guide to a Program Which Generates Wiring Lists," October 31, 1966. 6U2 Lieman, D.S. , "Description of the WEB Wiring Table," February U, 1965. -1- GENERAL DESCRIPTION: PASS I The WEB processor incorporates two separate passes of the input description to fulfill its task. Pass I has as its input the WEB logic description, and its function is to expand all logic blocks down to unit level and to generate missing block calls as indicated by the "..." instruction. Two sets of output are generated by this pass: the Packaging Skeleton and an Intermediate Description. 2 .1 The Packaging Skeleton The Packaging Skeleton is a listing of the expanded logical description with appropriate replacement of signal names. As described in File 625, a unique identifying number, called the index number, is assigned to each unit and is printed as a part of the Packaging Skeleton. Contrary to the description in File 625, signal names are printed instead of their internal numbers, and the expanded logic listing discussed there has been incorporated here as a part of the Packaging Skeleton (e.g., see Figure l) . 2 .2 The Intermediate Description For trouble shooting it is desirable to have a description of signal paths, complete with specific pin information- However, rack- connector assignments are not available until the second pass, and the input logic description afforded by the WEB language is not well suited for sequential processing by signal path. Thus, an intermediate description of the assembly being processed is generated in pass I. This description consists of two parts: an Internal Description which is machine-oriented, and a Signal Set Listing provided for users. 2.2.1 The Internal Description The Internal Description is made necessary at this stage as the 1 Alternatively the WEB input description can by extension explicitly indicate iteration by Algol bO-type "FOR" statement. CM m in UJ — 1 O r\ < 1 G. O o z 3 < ci. LTt a _J < z o oo -*• _l < z :_3 00 m _i < i z C5 oo CO LU 2C tsj Z i— • c£ -J UJ < t- z z o i— • »— 1 I/) o t- h- Z> a. z *-t 1-1 < _/ h- < < z Q o UJ i/i _l Q. 2. t- < 0. 00 »— i Of z: o a 1/1 oC CO u. D 1/) t- ^ Q. UJ h- X. 3 < O z z o 1— y- < o z o u _l 1- l_l _l UJ -1 * (-0 00 00 UJ X < z UJ a. »- Q O z 1 «» 1— 1 x. CD (_) UJ < i a a Q UJ UJ r> -O Z Z k- 1— Z z o o o u — ( I— < ^» w 01 oo o o ~* 1— 1 w *-- 1- V— X X UJ UJ UJ UJ •J- *-» — in « ~- OM o o (N, I— » ~* X o ^H X o ~-< I/) u o Ol o u u o l_> o o "■ LL i-H i- M 1— — . ~J t- — X i_) u x oo x o o X 00 uj o o a UJ u- -r in •0 f- - ~* CM ro ~r in o r» ^H M (M »H ^ M ^ fH CM -H M o Q Q Q a a o a o Q a o Q Q o D z z z z z z z z z z z z z z z Z o * in •o h- o o o o o o o o o .-« * o o o o o o o o ^-« r-* * (\J o * o o +j d) H ty ^1 CO bD CJ •H t5D cd o c3 P-i I ■H rack-connector assignments must "be made manually, requiring two separate runs to be submitted to the WEB processor. The Internal Description is a machine oriented set of information which is necessary to communicate the results of pass I to the pass II processor. In a later version of WEB, only one run will be necessary, as the rack-connector assignments will be automated. In this case, it will not be necessary to output the Internal Description. 2.2.2 The Signal Set Listing The other part of the Intermediate Description is the Signal Set Listing (see Figure 2), consisting of the block and position within the 2 terminal list of that block in which a given signal occurs. For example, CSX(O): CC(0)-1, CC(l)-l, ..., CC(9)-1, S-l tells one that the signal path CSX(O) consists of the first terminal of each of blocks CC(0), CC(l), ..., CC(9) and S. It must be noted that a terminal of a block corresponds to a particular pin only when the block itself is a unit. If a block is not a unit, then a given terminal may correspond to more than one pin. For example, CC(o)-l really corresponds to the pins associated with NAKDl(3)-l and NANDl(U)-l. 2 Compare Hazelhurst and McCormick, ibid, p. 18 ■h- - CI in UJ ^ o ei < i a o o 3 < 3t -— ) — < CM (M a 1 1 J- 3* O U o o 1 1 o o o o — « — < 1 1 cm r- o o 1 vT o o (M 1 o o CM 1 CM z 1 a o o CM 1 X o o cm 1 cc o a l_> <_) u 3 z cc l±J i- z "" o — < — < (M CM 1- i i 1 1 (- ■-" s> ■H nO 3 <— MM a o o o o z o o o o *- < t- < a UJ I—) _i _l a X -J < <: r-l i—4 CM CM IS) z 1 1 1 1 T. se O in o in a a: »» » M* M — CM CC UJ o o 1 (_) O 1 Li. i- o u IS) o o is) 1- 3 CJ o a o o i- o o r> o o o X UJ Q Z UJ o o o X z < •— t z 1- 1/1 _l .— « *- < < o o -" -I z o X t~ lA 1- N* IS) X l/l UJ (/) o UJ - X 01 I I O -I T IT a I I o -I •O 00 or or! < <' < <| i i -J rH | I I I — ~ ~ m ro co 1 — < or a: or i i — CM CM t— — < a: oc'or or or or l I o m or cc l l o in tiO •H -P w •H i-q ■p CO a taO •H to C\J •H 3- GENERAL DESCRIPTION: PASS II After the rack-connector assignment for each unit indicated in the Packaging Skeleton has been made, the Packaging Description and the Intermediate Description are input to pass II of the WEB processor. Pass II then generates the signal path description with pins assigned such that wire length is minimized. Wire lists are produced from which a technician may wire the assembly. This pass is accomplished in three phases: 1) Phase I generates a signal path description, but the interconnection of pins associated with this description is only a first approximation to the final result. 2) Phase II consists of the wire length minimization algorithm which operates on the result of phase I, permuting signal names in the description of a signal path until a minimum wire length to interconnect these pins is found. This minimal signal path description is then stored. 3) Phase III then prints the wire lists either with reference to a specific connector, or alternatively listed by signal path name . -6- k. IMPLEMENTATION OF PASS I: PARTIAL SPECIFICATIONS l+.l Iterative Instructions It is convenient to do a prescan of the logic description in order to expand the iterative blocks as indicated implicitly by the " ..." instruction and explicitly by the "FOR" instruction. In each case card images missing due to the use of the more concise iterative instruction are generated and written onto a scratch tape. The tape number and record number of any particular block of card images on a scratch tape are planted in the card image of the particular occurrence of the iterative instruction (in the source input) which caused its generation. When a PACKG or END instruction is sensed, the prescan is completed and the input tape should be rewound to the start of the source input. The main scan can then obtain the information necessary to process an iterative block by referring to the tape record specified by the prescan, the identification of which is now located in the card image of the occurrence of the iterative instruction. h.2 Expanding the Input The UNIT and BLOCK declarations are essentially macro definitions. We adopt the convention that unnamed blocks are given the name NONAME and a sequence number, so that they also may be considered as macros. Thus the logic description is just a set of macro definitions, with an all -encompassing macro whose body of definition consists of NONAME (l), NONAME (2), ..., NONAME (n) . In the logical description, however, no macro is actually called--only definitions are given. Accordingly, we may consider the END operation as a call of the all- encompassing macro, which in turn causes all expansion to take place. This implementation requires that the compiler-compiler have subroutines available which will make it simple to write a macro-compiler. With the macro-compiler written, the expansion of the input is then a simple matter. -7- 1+.3 Unit Identifying Numbers A unique identification of any unit in an expanded input is the succession of block names from the outermost block to the unit itself. For example, in Figure 1, unit number 0103 (part of the Index Number 010103) is really OUTERMOST: N0NAME (l ): CC(o) :NAND1 (3) and 020U is really OUTERMOST: NONAME(i) : CC(l) : NANDl(^) . Using this succession of names as an identification would require quite a large amount of processing just to find the identifying number of a unit given the succession of block names, and so it is not acceptable. The problem is entirely analogous to the problem of encoding the terminal nodes of a tree which may have an arbitrary number of branches emanating from any (non-terminal) node. If one is willing to place an upper bound on the number of members of a sibling set, the following notation could be used: We define a "left-to-right" order among members of a sibling class, and in so doing number the members of such a class sequentially according to this order. For example, we have TREE LEVEL TREE LEVEL 1 TREE LEVEL 2 3 1 2 f3 h A Then a particular node at tree level n may be uniquely specified by the (n + l) -tuple P = (s Q , s x , — -, s r ) where s is the sibling number of the node in question, and s., < i < n-1, is the sibling number of the node at tree level i along the unique path determined by the root node and the node in question. For example, node A above would be designated (l, 3, 3)- Since s is always identically 1, the n-tuple q = (s , ..., s ) is sufficient for identification of a node at tree level n. For implementation this much information is actually necessary, for in pass II the only way one can point to a specific unit is by an -8- appropriate encoding of a succession of block names. When the input description is being expanded, one is doing a prefix scan of the eventual tree, so it is necessary to number block names sequentially at each level of the tree as they are encountered so as to have the numbering scheme as proposed. Thus it will be necessary to retain the name, level, and sequence number of each block. Then, given the succession, of block names N 1 : /:...:<, m m-1 1 one may search level i block names until name N. is found and obtain its sequence number s., and doing this for i = m, m-1, . .., 1 one obtains the m-tuple (s , ..., s n ) . The unique unit number s s . ...s n , called the e N m 1 m m-1 1 index number, is then constructed, and from this the assigned packaging for this unit may be obtained. We adopt the convention that m < 6, and < s < 6U, so that an — — i index number corresponds to the 36 bit word of the IBM 709^- • Thus, in the example above, the index number for A is 010303- k.k The Intermediate Description k.k.l The Signal Set Listing The lists of signal paths, e.g., CSX(O): CC(0)-1, CC(l)-l, ..., CC(9)-1, S-l can be derived from the block declarations themselves, so the actual units involved are not necessary at this stage. We must impose the convention that signal paths begin with a given block declaration and end with the termination of that block's body of definition. This allows one to specify the wiring between blocks. The Signal Set Listing then simply consists of the lists of these signal paths output in the format specified in Figure 2. -9- k.k.2 The Internal Description 1+.1+.2.1 Named Block Table An entry is made in the Named Block Table each time a named block is defined. An unnamed block is given the name NONAME (n) when it is the nth unnamed block, so that all blocks may be considered as named blocks. The entry essentially describes the structure of the block in terms of signal paths rather than functionally. An entry is of variable length; its structure may best be explained through the use of an example. To this end, in Figure 3, we give the entry to be constructed with the occurrence of the definition of block CC as in File 625. CC EXTERNAL INTERNAL AUXILIARY INFORMATION G ' A ! A 1 8 \ R 1 A 1 A 1 10 \ Y 1 A ' A 1 11 K 1 A 1 A 1 12 X 1 A 1 A 1 Ik CCO 1 A 1 A 1 15 ; cci 1 a 1 a I 17 A 1 A 1 A 1 19 t NAND1 1 A 1 3I 1 * NAND1 1 A i k I 1 NAND2 1 A ' A 1 1 * NAND1 1 A 1 6 1 1 NAND1 1 A 1 6 1 2 NAND1 1 A 1 7 1 1 NAND1 1 A I 7 1 2 NAND1 1 A 1 1 1 3 NAND1 1 A 1 2 1 1 NAND1 1 A 1 1 1 2 NAND1 1 A | 2 1 3 1 — ~> \ \ \ \ M k c A 1 A 7 D 1 A 1 A 9 E 1 A 1 A 11 F 1 A 1 A Ik A A 1 A 17 B A • A 19 A A A 21 NAND1 A 1 1 1 NAND1 A 3 3 NAND1 A 2 2 NAND1 A k 3 NAND1 A 3 2 NAND2 A A k NAND1 A 5 1 NAND1 A 1+ 2 NAND2 A A 3 NAND1 A ■? 3 NAND2 A 1 A 2 NAND1 A 1 6 3 NAND1 A 1 °) 2 NAND1 A 1 7 3 Figure 3- Named Block Table Entry -10- As shown, a signal name subentry is of the form: name subscript 1 subscript 2 relative pointer where "A" is used for "no-entry". The relative pointer points to a list of entries which are called the constituent parts of the signal path. These entries are of the form: name subscript 1 subscript 2 position in terminal list The relative pointer of the next signal name subentry minus the current relative pointer gives the number of constituent parts of the current signal name. Thus, as in Figure 3, signal name K has two constituent parts, namely NANDl(6)-2 and NANDl(7)-l The external signal names are those given in the terminal list if a terminal list is given in this block declaration. In this case, internal signal names are those which are used in the block definition, but not given in the terminal list. If no terminal list is given, e.g., in the case of an unnamed block, all signal names in the definition of the block are treated as external signal names. The specification of this entry thus determines the algorithm to be used for processing a named block. U.U.2.2 The Internal Representation of the Signal Set Listing After the Named Block Table has been constructed, one further entry is made for the "outermost block". If we consider an unnamed block to have a pseudo terminal list, i.e., a list of signa] names occurring in the unnamed block, then the additional entry to be made to the Named Block Table consists of a list in lexicographical order of the signal names occurring in the pseudo terminal Lists of the unnamed blocks, with references to the position within each unnamed block's pseudo terminal list at which a given signal name occurs. A.-: described in the previous section, each of these signal name subentries pointr. to the constituent parts of the signal name. -11- The algorithm to generate the Signal Set Listing is as follows: If there are m signal names in the "outermost block" entry of the Named Block Table, then we start with the stack: OUTERMOST - 1 OUTERMOST - (m - l) OUTERMOST - m Now suppose the stack has been processed to the point: OUTERMOST - 1 We now describe the processing, and include as an example, the derivation of the CSX(o) entry of Figure 2: l) Replace the top of stack by its equivalent in the "outermost block" entry. r csx(o) 2) Push into the stack the constituent parts of the top of stack. CSX(O) NONAME(l) - 1 3) Now the top of stack is a signal name of the form BLOCK NAME TERMINAL LIST POSITION. Replace the top of stack by this BLOCK NAME, and push into the stack the constituent parts of the signal name which was the top of stack. csx(o) NONAME(l) CC(O) - 1 CC(l) - 1 / cc(9) - i s - i k) Pop the top of stack into an output stack until a block name is the top of stack. CSX(O) NONAME(l) -12- output stack: cc(o) CC(1) cc(9) - l 5) Pop the top of stack into the output stack. 6) If the top of stack is now a NONAME reference, that is, NONAME(i)-j, then go to 3). If the top of stack is a signal name other that NONAME(i)-j, then pop this signal name into the output stack. 7) If the stack is now empty, go to 8). Otherwise, go to l). 8) Save the output stack on magnetic tape. This is the internal representation of the Signal Set Listing, and is to be used in phase I of pass II. After saving (but not destroying) the output stack, the information in this stack may be popped to the Signal Set Listing print routine, transforming any occurrence of an unnamed block to its appropriate index number. k.k.2.3 The Fill Table As a part of the internal description, a Fill table must be output. An entry is made in this table for each distinct unit in the assembly being processed. Such an entry is: Index Number Rack Connector Unit The index number is the n-tuple discussed in Section ^«3« Pass I must complete this entry except for rack-connector-unit information which is provided by the Fill instruction in the Packaging Description processed by pass II. ■13- 5. IMPLEMENTATION OF PASS II: PARTIAL SPECIFICATIONS The input to pass II consists of the Internal Description generated by pass I, the Packaging Description, as specified in File 625, and the filled Packaging Skeleton, the latter two being provided by the user. 5-1 Phase I From the Internal Description, phase I uses the internal representation of the Signal Set Listing and the macro compiler tables. Phase I generates the set of pins assigned to each of the units in a given signal path, the algorithm being as follows: Consider the internal representation of the following signal from the Signal Set Listing CSX(O): CC(0)-1, CC(l)-l ---, CC(9)-1, S-l processed to the point csx(o) NONAME(l) CC(O) - 1 CC(l) We now describe the processing involved: • CC(l) - 1 is an abbreviation of block name CC(l), position 1, and thus is a signal name -- the first signal name in the declaration of block CC That is, CC(l) - 1 is just another name for the signal G within block CC(l). Accordingly, we replace CC(l) - 1 in the stack by its equivalent: the block name CC(l), and the signal name G (obtained from the Named Block Table, in the entry for CC). csx(o) NONAME(l) cc(o) - 1 CC(l) Then from the Named Block Table of the Internal Description, in the entry for CC, we find that G is the signal path: G: NANDl(3) - 1, NANDl(U) - 1 -Ik- We then replace G in the stack by its constituent parts: csx(o) NONAME(i) CC(O) - 1 CC(1) NANDl(3) NANDl(U) (Actually, the insertion and replacement of the signal name G itself in the stack is for descriptive purposes only, for by the construction of the Named Block Table, the signal path of the first signal of block CC may be obtained just by referring to CC(l) - l). Since the top of stack is a signal name of the form UNIT NAME - TERMINAL LIST POSITION, we now reference the macro table entry for CC, the first block name from the top of stack, to obtain the sequence number of NANDl(U), which is Ok -- this is s of the index number of the unit currently being processed. Similarly, we find that the sequence number of CC(l) in the macro table entry for NONAME(I) is 02 -- this is s of the index number of the unit currently being processed. NONAME(l) has sequence number 01, so that the index number of the unit being processed (that is, the top of stack) is 0102014. With this index number we do a table look-up on the Fill Table, and find that this unit has been assigned to DV9> that is, rack D, connector 0^ and unit position 9* From the board assignment table we find that rack D connector 0^4 has board A-180 in it. Finally, searching the description of board A-180 , we find that the pin associated with the first terminal (the first terminal, because we are working on NANDl( i 4) - l) of unit 9 is pin 16. Thus, we may output the pin number DU-l6. csx(o) NONAME(l) , CC(0) - 1 CC(l) NANDl(3) - 1 output stack: D^-16 Similarly, since the top of stack is again a signal name of a unit, i.e., a signal name of the form UNIT NAME - TERMINAL LIST POSITION, we -l'.- repeat the process yielding: CSX(O) NONAME(l) CC(O) - 1 CC(l) output stack: D3-16 D-4-16 Since top of stack is now just a block name and not a signal name, we remove it and begin anew with the signal name CC(O) - 1. Processing this gives us csx(o) NONAME(l) output stack: Dl-16 D2-16 D3-16 D1+-16 Now an unnamed block "name" is the top of stack, and so we just remove it and continue. If the top of stack is an "outermost block" external signal, then the phase I processing of this signal is complete. Thus, the output stack is now transferred to phase II for optimization of the interconnection of these pins, and this being completed, phase II returns control to phase I to start anew with the next signal path in the stack. Otherwise, the top of stack is a signal name of the form BLOCK NAME TERMINAL LIST POSITION, and processing must continue as previously specified. 5-2 Phase II: Wire Minimization 5*2.1 Backboard Configuration The geometrical configuration of the backboard in terms of the allocation nomenclature is derived from the "PINS" and "CELLS" instructions of the packaging description (of File No. 625). Actually since it is unlikely that WEB will be used in the immediate future for processing machines other than ILLIAC III, it is recommended that interim WEB not require this input. Rather a fixed geometry can be used. Four constants are assumed by the program: the vertical rack to rack spacing, the horizontal cell to cell spacing, and the vertical and horizontal pin to pin -16- spacing within a cell. Using this information each pin of the Signal Path Description is transformed to a pair of Cartesian coordinates. 5-2.2 Distance Matrix For each signal of the Signal Path Description the point-to-point direct distance wire length is calculated for each pair of points in the signal path. These distances are compared to the set of available wire lengths and the minimum available wire length greater than the distance (with a slack factor) is selected. These selected lengths are entered in a Distance Matrix. 5.2.3 Minimization of Total Path Existing procedures for wire minimization based on the Travelling Salesman Problem have serious shortcomings. A new technique, which is an extension of a non-optimal method proposed by Croes, has been developed and does lead to optimum solutions. The details of the method are presented in full in the Department of Computer Science Report No. 201 . This method is now being programmed and will be tested on typical problems for reasonableness in running time and memory requirements. In the iterim a method proposed by Karp and Held of IBM has been made available for our use. This program is the fastest method to date and works well for problems of up to 13 points. It can solve any 13 point problem in 17 seconds, and any 8 point problem in about 20 milliseconds on the IBM 709O. The method is unfortunately not well suited for larger problems . 5-3 Phase III The wire lists generated by phase II are now printed either with reference to a specific connector or with reference to signal path name as in Figure h. See Lieman, "Description of the WEB Wiring Table", Department of Computer Science File No. 6U2, February k, 1965. -17- o m i C Q O z LO LO LO M < Q. O I z CD C£ UJ — IS 3 o o a a UJ UJ LJ UJ or CC a: CH »o ■o •o ■o "> - 1 "-* Y 1 i in 1 Ln o o fH •— i r\J o Q Q a 3 Q Q o l_l UJ LJ UJ & 0£ a! cc O s0 o •o "-' - 1 - 1 - 1 1 1 I l a* o o t-H «— 4 Q Q Q Q a O O Q UJ LU UJ UJ DC CL r: cc o J3 -J3 nC - 1 - 1 - 1 - 1 i 1 CO 1 CI i 00 o o t— i -H Q Q o Q O a o Q u UJ UJ UJ a: OS a: a£ ^0 %o NO vO -o I i 1 1 i (NJ O o *-l i~* (SJ o a O Q Q Q a Q Q Q LJ UJ LU LU LJ as CL 0£ a: o: sO •o -0 -o ■o f-H r-\ ■"' 7 1 "- 1 1 1 _, 1 _< o o ^-* t— t (\l Q a a o a m o f-H o »— t o o X I/? l_> °! UJ < < ? W -P w •H Kl fciD •H u •H 0) •H 6 . SUMMARY The WEB language is designed to describe the interconnection and packaging of the logical elements in a digital assembly. Essentially this language allows one to describe an assembly concisely in terms of the basic functional blocks of the assembly and the nested organization of these blocks. In the implementation of this language it was found that although a functional description was most convenient for the logic designer, the task of producing actual wiring lists for the construction of the assembly could best be performed by using the signal path as the basic entity for processing. The macro nature of the WEB language with its inherent modularity and iterative structure allows the transition from this language to an intermediate language having signal paths as its basic constituents to be performed most easily by using a push down stack algorithm. By extension, a push down stack algorithm is also used for determining the pins associated with a given signal path described in this intermediate language. Finally the minimization of the wire length of the interconnection of pins in a given signal path is performed. The WEB language is the vital means of communication between the logic designer and computational facilities at his disposal. The implementation of this language in a time sharing environment will provide real time information concerning the numerous physical and functional limitations the logic designer must face in the design of a digital assembly. -19- FormAEC-427 U.S. ATOMIC ENERGY COMMISSION appm 6 ?^! UNIVERSITY-TYPE CONTRACTOR'S RECOMMENDATION FOR DISPOSITION OF SCIENTIFJC AND TECHNICAL DOCUMENT { S*» Instructions on Rtytrm Sid* ) 1. AEC REPORT NO. COO-2118-0036 UIUCDCS-R-T2-539 2. TITLE Realization of the WEB Language 3. TYPE OF DOCUMENT (Check one): Q a. Scientific and technical report [~~[ b. Conference paper not to be published in a journal: Title of conference __, Date of conference Exact location of conference. Sponsoring organization □ c. Other (Specify) 4. RECOMMENDED ANNOUNCEMENT AND DISTRIBUTION (Check one): Q5 a. AEC* normal announcement and distribution procedures may be followed. ~2 b. Make available only within AEC and to AEC contractors and other U.S. Government agencies and their contractors. ~2 c. Make no announcement or distrubution. 5. REASON FOR RECOMMENDED RESTRICTIONS: 6. SUBMITTED BY: NAME AND POSITION (Please print or type) William D. Bond and Edward S. Davidson , Research Assistants Bruce H. McCormick, Principal Investigator Organization Department of Computer Science University of Illinois Urbana, Illinois 618OI Signature S-AC e e« t Jl£ Date August 1, 1972 FOR AEC USE ONLY 7. AEC CONTRACT ADMINISTRATOR'S COMMENTS, IF ANY, ON ABOVE ANNOUNCEMENT AND DISTRIBUTION RECOMMENDATION: 8. PATENT CLEARANCE: I I a. AEC patent clearance has been granted by responsible AEC patent group. I~] b. Report has been sent to responsible AEC patent group for clearance. I I c. Patent clearance not required. IBLIOGRAPHIC DATA 1EET 1. Report No. UIUCDCS-R-72-539 3. Recipient's Accession No. Title and Subtitle Realization of the WEB Language 5. Report Date August, 1972 Author(s) William D. Bond and Edward S. Davidson 8> Performing Organization Rept. No. Performing Organization Name and Address Dept. of Computer Science Univ. of Illinois at Urb an a- Champaign Urbana, Illinois 6l801 10. Project/Task/Work Unit No. ILLIAC III 11. Contract /Grant No. AT (ll-l) -2118 I, Sponsoring Organization Name and Address U. S. Atomic Energy Commission 13. Type of Report & Period Covered 14. Feb. - June, 1972 1, Supplementary Notes Abstracts WEB: a language to describe the interconnection and packaging of the logical units in a digital processor has been fully discussed in previous reports. The purpose of this report is to specify the various subprocesses involved in processing a WEB description of the logical elements in a digital assembly. A knowledge of WEB, the language in which an assembly may be described, is assumed. Key Words and Document Analysis. 17o. Descriptors descriptors programming language interconnection packaging design automation digital processor b. Identifiers/Open-Ended Terms COSATI Field/Group Availability Statement RELEASE UNLIMITED 19. Security Class (This Report) .■ . UNCLASSIFIED 20. Security Class (This Page UNCLASSIFIED 21. No. of Pages 22. Price IM N TI3-3B ( 10-70) USCOMM-DC 4032O-P7I >Cr <^a 1972 I