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 ho.£|-8>0 
 
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Digitized by the Internet Archive 
 
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 http://archive.org/details/theoryofasynchro75mull 
 
UNIVERSITY OF ILLINOIS 
 GRADUATE COLLEGE 
 DIGITAL COMPUTER LABORATORY 
 
 REPORT NO. 75 
 
 A THEORY OF ASYNCHRONOUS CIRCUITS I 
 
 D. E. Muller and W. Scott Bartky 
 
 November 7 > 1956 
 
 This work has been supported in part by 
 the Office of Naval Research under 
 Contract NR 0^ 001 
 
1. Introduction 
 
 1.1 Switching circuits are commonly classified as being either synchro- 
 nous or asynchronous, depending upon whether or not the signals in the circuit 
 are synchronized with some source of fundamental frequency (or clock) which 
 regulates the entire circuit. Much of the mathematical theory of switching 
 circuits and many design techniques have been limited to synchronous circuits, 
 because it is possible to predict the state (or condition) of a synchronous 
 circuit at the time of any given clock signal if one knows the initial state of 
 the circuit and its logical characteristics. As a result, many design problems 
 may be handled by logical algebra. However, in an asynchronous circuit it is not 
 possible to predict the state immediately resulting from a previous state from a 
 knowledge of the logical characteristics of the circuit alone. The resulting 
 state may also depend upon the relative speeds of some of the logical elements which 
 comprise the circuit. The possibility of such "races" in asynchronous circuits 
 complicates the theory unless one is prepared to make definite assumptions concerning 
 element speeds, and thus reduce the problem to the synchronous case, or else design 
 one's circuits so that only one logical element is able to change at a time. 
 
 1.2 We shall not attempt here to extend the theory of synchronous circuits 
 to cover the asynchronous case, but rather develope a comprehensive theory of 
 asynchronous circuits which will differ from the synchronous theory in many 
 fundamental respects. One of our main objects will be to describe the 
 properties of circuits which are speed independent in the sense that their 
 ultimate behaviors do not depend upon the relative speeds of their elements. 
 What is meant by "ultimate behavior" will be set down precisely in the later 
 discussion and techniques for designing speed independent circuits will be 
 described toward the end. 
 
 1.3 Existing theories of asynchronous circuits have been mostly concerned 
 with what might be called the "black box" model of a circuit. It 
 
 deals with a "black box" or circuit having a number of inputs, a number of 
 outputs, and a number of internal states. When the input signals are changed, 
 the circuit proceeds from its existing internal state to another uniquely 
 determined internal state and the outputs change accordingly. One must always 
 assume that no further change is made in the inputs until this second internal 
 
 -1- 
 
If 
 
 ll 
 
 Hi 
 
 ii ii 
 
 
state has actually "been achieved, for otherwise the behavior of the circuit 
 would be indeterminate. The theory treats the way the states and outputs 
 change as a result of manipulating the inputs and in most respects is similar 
 to the corresponding theory of synchronous circuits . 
 
 1.4 The theory presented here is not a revision of the "black box" 
 theories but may be regarded as a supplement to them since it is concerned 
 with the changes which the circuit undergoes if the inputs, if any, are held 
 fixed. It therefore deals with those transitions which occur between input 
 changes. It might also be used to describe the action of a circuit which has 
 no inputs of the type referred to above; for example, an automatic computer. 
 Since the inputs, if they exist, are regarded as fixed in the present theory 
 they need not appear explicitly in our description of a circuit and may be 
 regarded as parameters affecting the circuit's logical properties. 
 
 2 . Description of a Circuit 
 
 2.1 In an idealized switching circuit the physical signal present at 
 any point within the circuit may assume one of a discrete set of values. 
 This physical signal may take the form of a voltage, current, position, or 
 other measurable quantity. Let us assume that n such measurements are 
 sufficient to specify the state of the circuit so that any other measurements 
 may be uniquely determined from the given n, These n signals will be denoted 
 by symbols such as z. ,z , ... ,z and the n-tuple z = (z , z , ... , z ) 
 will be taken as representing the state of the circuit. 
 
 2.2 Each signal z. may assume one of a discrete set of values S., 
 where the elements of S. are finite in number and totally ordered. They may 
 therefore be set into correspondence with the integers 0,1, ... ,k. -1, where 
 it is assumed that S contains k elements. The set S of states is, thus, 
 also finite and contains all n-tuples z whose components z. are taken from 
 
 the sets S. . 
 
 l 
 
 2.3 An important special case is that of the binary switching circuit in 
 which a signal may take one of but two possible values so that k.=2 for each 
 i=l,2, ... ,n. Thus, in the binary case the signal z. may be either or 1, 
 while in the general case, it may be any member of the ordered set of values 
 
 -2- 
 
0,1, ... ,k -1. The binary case is so important that it would hardly be worth- 
 while treating the more general case were it not possible to do so with very 
 little additional difficulty. 
 
 2 .k In a relay switching circuit the signal z. may be conveniently taken 
 as describing the position of the i'th relay. If this relay is of the usual 
 two position (open or closed) type, the signal will be binary while a relay 
 having k. standard positions could be described by the more general type of 
 s ignal . 
 
 2.5 In an electronic switching circuit the signals are usually interpreted 
 as voltages, and although it is true that voltages in a circuit change in a 
 continuous fashion, one may assume that each signal value merely specifies a range 
 of voltage rather than an exact voltage Naturally, we may only use this 
 simplified treatment of the signals if the behavior of the circuit is adaquately 
 described by the discrete signals. 
 
 2.6 The switching properties of an idealized switching circuit can be 
 expressed as a set of functions 
 
 ; ' = f . (z. ,z_, ... ,z ) ; 1=1,2, 
 
 1 1 1 2 n 3 ' ' 
 
 where the dependent variables z.' lie in the sets S.. Each z.' is assumed to be 
 
 1 11 
 
 uniquely determined by the state z=(z, ,z , . . . ,z ). In a binary circuit these 
 functions will be Boolean functions since all signals are assumed to be either 
 or 1. In an electronic circuit these functions represent individual logical 
 elements which form the circuit and serve to describe their interconnections, 
 while in a relay circuit these functions express the behavior of the networks 
 of contacts . 
 
 2.7 Our theory will therefore be concerned with the following concepts: 
 
 (2:1a) n signals z. 5 1=1,2, ... ,n, each taken from a set S. of k. 
 
 ordered elements, which will be written 0,1, ... ,k.-l. 
 (2:1b) The set S of n-tuples of signals z=(z, ,z p , ... ,z ), called 
 
 states . 
 (2:1c) n functions z.' = f . (z ,z p , ... ,z ) which define a mapping of 
 
 S onto itself o 
 
 A more general switching circuit will also be influenced by outside parameters or 
 "inputs" which should properly be included in equations (2:1c). Since the present 
 
 ■3- 
 
theory is only concerned with the behavior of circuits during the time that such 
 inputs (if present at all) are held fixed, we need not include them explicitly in 
 the functions (2:1c). 
 
 3° Circuit Behavior 
 
 3.1 We now wish to set down a mathematical description of the behavior 
 of an asynchronous, or non-clocked, switching circuit* If the circuit is placed 
 in a state a=(a.,,a , ... ,a ), some of the signals will generally tend to change 
 and the circuit will pass to another state b=(b,,b , . . . ,b ) . If the circuit 
 is synchronous this "next" state b will occur just one clock interval later 
 and will be uniquely determined by the functions (2:1c). In fact, b will be just 
 a'= (a ' ,a ' , ... ,a '). In an asynchronous circuit, on the other hand, there 
 is no clock, or source of fundamental frequency, and the relative times which 
 the various signals take to change will depend on physical properties of the 
 circuit elements and will be unrelated to the logical properties expressed in 
 (2 sic). The state b is, thus, not always uniquely determined by the functions 
 (2?lc) in the asynchronous case and, in general, may be any one of several 
 states depending on these relative speeds. 
 
 3°2 We wish to make no specific assumptions concerning relative speeds 
 of circuit elements in the asynchronous case and we shall try to describe all 
 possible states b into which the circuit may pass from a given state a. This 
 concept is expressed in terms of a relationship 0c . 
 
 (3sl) a^-b means that each signal b. of b satisfies either 
 
 a.< b.< a „ ' or a.> b.> a . ' , depending upon whether a.< a. ' or a.> a. ' . 
 i-* 1— 1 1— 1— 1 * 1—1 1—1 
 
 Clearly a$,a and a&a' , but, in general, there may be other states b as 
 
 well which satisfy a Jib, and in asynchronous circuit theory all such "next" 
 
 states will be regarded as possible. If one thinks of a. as the existing signal 
 
 and a.' as a new signal toward which point i is tending, then (3^1) may be 
 
 thought of intuitively as saying, that in the "next" state b the signal b, at 
 
 point i may have changed so that it lies anywhere in the closed interval a. to a.' 
 
 (3:2) A partial allowed sequence of k states a(l),a(2), ... ,a(k) is 
 
 any sequence of k > 1 states which, whenever k > 2, satisfies 
 a(j)02. a(j+l) and a(j) + a(j+l) for all j=l,2, ... ,k~l. 
 
3«3 A partial allowed sequence is a sequence of states which is intended 
 to describe the possible behavior of a circuit which starts in state a(l) and 
 passes through succeeding states a (2), ... ,a(k). The circuit may go on to 
 other states after reaching a(k) and so to complete the description of the 
 circuit's behavior we require? 
 
 (3*3) An allowed sequence of states a(l),a(2), ... (which may be either 
 
 finite or infinite) is any sequence satisfying: 
 (3^3a) a ( j ) (X. a(j+l) and a(j) \ a(j+l) for all consecutive pairs of 
 
 states a(j),a(j+l) in the sequence. 
 
 and 
 (3 Ob) No signal a.(j) may satisfy either 
 
 a . ( j ) =a.(k)<a ! . (k) for all signals t. . (k) with k > j 
 
 or 
 
 a. (j ) = a. (k) > a' . (k) for ail signals a. (k) with k > j. 
 
 3 A An allowed sequence may be regarded as a possible sequence of states 
 through which an asynchronous circuit might pass if placed initially in state a(l) 
 This definition (3° 3) was chosen because it was thought to best represent 
 asynchronous circuit behavior. Other possible definitions may be more convenient 
 from a mathematical standpoint but would fail to yield a realistic theory „ 
 Condition (3»3b) requires that no point i in the circuit may retain a signal a . ( j ) 
 indefinitely if it is tending toward some other value a.'(k) which remains either 
 greater than a. ( j ) or less than a. (j) for the rest of the sequence » We note that 
 (3*3b) permits a. (j) to remain fixed indefinitely if a'.(j) is alternately greater 
 and less than a.(j)o 
 
 (3*^0 Any finite, consecutive, set of states in an allowed sequence forms 
 
 a partial allowed sequence. 
 (3»5) If both a(l),a(2), ... ,a(k) and a(k),a(k+l), ... ,a(m) are partial 
 
 allowed sequences, then a(l),a(2), » . . ,a(k), ... ,a (m) is a partial 
 
 allowed sequence. 
 (3^5b) If the sequence a(k),a (k+l), » . . is an allowed sequence and 
 
 a(l),a(2), o.. ,a(k) is a partial allowed sequence, then the composite 
 
 sequence a(l),a(2), ... ,a(k), ... is an allowed sequence. 
 (3s 6) Allowed squences may be either finite or infinite, but if a finite 
 
 sequence a(l),a(2), . = . ,a(m) is allowed, then the terminal state a(m) 
 
 must be an equilibrium state, i.e. one for which a(m) = a'(m) 
 
 -5- 
 
l! " 
 H 
 
 H 
 
 ii i 
 i 
 ii ■ 
 
 i 
 
 II 
 
 1 1 
 
 iii 
 
 t i ' 
 I ' I 
 
 I' 1 
 i' 
 
 I' \\ I 
 
The statements above follow from the definitions of allowed and of partial 
 allowed sequences. (3=6) must hold in order to avoid a violation of (3s3b)» 
 (3* 3b) also restricts infinite allowed sequences, but in a more subtle way as 
 will be demonstrated later. 
 
 3-5 If an allowed sequence does indeed represent a possible sequence of 
 states through which the circuit might pass, then it should be possible to show 
 that at least one allowed sequence exists which starts with any state a(l) as 
 the initial state . If no allowed sequence exists then we must seek someother 
 way of describing the behavior of the circuit when placed in state a(l). 
 
 (3: A) Given any state a(l), there must exist at least one allowed 
 sequence a(l),a(2), . .. having a(l) as its initial state. 
 Proof ; Form the sequence a(l),a(2), ... by the rules 
 (3:7a) Let a(j+l) = a'(j) if a'(j) + a(j). 
 (3? 7b) Let the sequence terminate with a(j) if a T (j) = a(j). 
 
 That this sequence satisfies (3:3a), may be seen from the property a(j) 83. a' ( j ) . 
 (3? 3b) may also be seen to hold if one notes that either a. (j) = a ' ( j ) or else 
 a. (j) 4 a « ' («J) = a -t (j + l) so "that either a. (k) = a ' (k); with k = j, or else 
 a ± U) 4 a i (k); with k=j+l. 
 
 3.6 In the relationship a (R. b we have expressed the notion that state b 
 may come after state a with no intervening states , We now go on to define a new 
 relationship a # b which will indicate that b may come after a but that intervening 
 states may separate them. 
 
 (3?8) a 5b, a is followed by b, means that a partial allowed sequence exists 
 having a as its first and b as its last state . 
 
 Two properties of the a relationship may be immediately noted . 
 (3?9a) a &a for all states a . 
 
 We note that any state a by itself forms a partial allowed sequence. 
 (3s 9b) a <£ b and b <f c implies a # c . 
 
 The composite sequence a, ... ,b, ... ,c is a partial allowed sequence. 
 
 3 »7 Unfortunately the & relationship does not produce a partial ordering of 
 the states since we may have a # b and b & a and yet a 4 b° A partial ordering 
 may be constructed between sets of states rather than states, in a manner described 
 in the following theory. 
 
 -6- 
 
(3: 
 
 •10) 
 
 (3: 
 
 :B) 
 
 
 Proof 
 
 af b means a J b and b £f a . 
 r is an equivalence relation. 
 We need only notes 
 (3:11a) a £ a for all a 
 (3; lib) a £ b implies b£ a. 
 (3:11c) a £ b and b £ c imply a £ c. 
 
 which follow from the properties of fr • 
 
 Since the states are finite in number, by construction, we see that the 
 £. relationship breaks the set of states S into a finite number of non-void 
 equivalence sets A,B,C, ... • 
 
 (3:12) Two states a and b lie in the same equivalence set C if and 
 
 only if a C- b . 
 (3:13) A «? B, A is followed by B, means that there is a state a in A 
 
 and a state b in B such that a ? b . 
 (3:C) If a is in A and B is in B, and if A?B, then a ££ b . 
 
 Proof: By (3s 13) we can find a state a* in A and a state b* in B so that 
 a*£^b*. Then since a 3 a*, a* & b*, b*^t>, we have a # b. 
 
 (3°D) The ^ relationship defines a partial ordering between equivalence 
 
 sets . 
 Proof : We must show? 
 (3:lta) A & A for all A. 
 (y.lkb) A# Band B# C implies A# C 
 
 O^c) A ^ B and B 5- A implies A = B. 
 These three properties may be easily deduced from (3:13) and (3°C). 
 
 3«8 Since the number of equivalence sets is finite and partially ordered, 
 there must exist at least one maximum or final set. 
 
 (3:15) M is a final set if and only if there is no set M* different 
 
 from M, such that M # M*. 
 (3°l6) Given any equivalence set A there must exist at least one final 
 
 set M such that A <£ M. 
 
 If we deny (3:l6) we may construct a sequence of sets A, A(l), A (2), ... of 
 indefinite length such that A(j) & A(j+l) and A(j) 4 Mj+l), and involving no 
 repetitions because of partial ordering. This requires an infinite number of 
 sets. Similarly, a minimum set may be shown to exist, but such sets will have 
 little importance in the present theory. 
 
 -7- 
 
(3?E) a = a' (i.e. a is an equilibrium state) if and only if its 
 equivalence set A is a final set containing just one state. 
 
 Proof : If a = a', then a 5£b implies a = b. Hence A is a set containing 
 just one state, and consequently is a final set since A ^ B would imply a ^ b 
 for a state b in B. 
 
 If A is a final set containing just one state a then since a #? a' we have 
 either a' in B with A «£ B which is impossible or else a' in A which means a = a' . 
 (3j17) A pseudo-final set P is an equivalence set of states p(l), ••• >p(r) 
 
 which is not final and for which there is no signal index i such that 
 
 p.(j) is constant over all j = 1, ... ,r 
 
 and either j, 
 
 P i (j ) < P i ' (j ) for all j = lj ... ,r 
 
 or 
 
 P 1 (J) > Pi'Cj) for all j =1, ... ,r 
 
 We note that a pseudo-final set must contain more than one state, 
 
 (3?F) Any allowed sequence a(l),a(2), ... must contain a state a(m) 
 
 such that all states a(m),a(m+l), ••• lie in the same equivalence set 
 T (called the terminal set of the sequence), which is either final or 
 pseudo-final. 
 Proof ; Since the number of equivalence sets is finite, we see that the 
 number of sets which are represented in any allowed sequence is also finite. Hence 
 there must be a state a(m) such that all equivalence sets in the entire allowed 
 sequence are represented in the partial allowed sequence a(l),a(2), «.. ,a(m). 
 Now if a(m) is in T, then all states following a(m) must also be in T. Otherwise, 
 partial ordering of the sets would be violated. 
 
 We must now show that T is either final or pseudo-final. Assume T is neither. 
 In this case we have either 
 a 1 (m) = a.(k) < a.'(k) 
 for some i and all k > m 
 or 
 
 a.(m) = a.(k) >a.'(k) 
 for some i and all k > m 
 and consequently we have violated (3? 3b). 
 
 3-9 In view of (3s l6) we note that if any initial state u is chosen, we may 
 always form an allowed sequence starting with u whose terminal set is final. A 
 
 -8- 
 
somewhat stronger result may be proved, however. 
 
 (3:G) If u is any state and U is its equivalence set, then if T is any 
 final or pseudo-final set such that U & T, an allowed sequence may be 
 constructed starting with u whose terminal set is To 
 
 Proof : If T is a final set and t(0) is any state in T, we may form a partial 
 allowed sequence u, ... , t(o) by (3^8) and (3^C). An allowed sequence starting 
 with t may now be formed by the method of (3'A). Since T is final, the sequence 
 must be entirely in T for if some member of the sequence lies in another set T, 
 we would have T c? T*. Now if we combine these two sequences by (3°5b), w e 
 obtain the desired sequence u, ... ,t(0), ... 
 
 If T is a pseudo-final set, the same proof may be used provided we may form 
 an allowed sequence starting with t(o) and lying entirely in T. This is done in 
 the following paragraph . 
 
 Let t(0),t(l), . .. ,t(k) be the states in the pseudo-final set T. Construct 
 k + 1 partial allowed sequences t(0), ... ,t(l) ; t(l), . .. ,t(2) ; 
 t(2), ... ,t(3) % ?.. J t(k-l), ... ,t(k) 5 t(k), ... ,t(0) ; by use of (3:8). 
 Since the states at the ends of these partial allowed sequences match they may be 
 combined by (3°5a) into a single partial allowed sequence 
 
 t(0), «o. ,t(l), ooo ,t(2), . .. , ... ,t(k), ... ,t(0) contaxuing all states in T> 
 Let us now repeat this partial allowed sequence indefinitely always letting the 
 last member of the previous partial allowed sequence be the first member of the 
 next. This resulting sequence is allowed since all states in T are present and 
 (3:1?) gives us (3s 3b), 
 
 k. An Examp le of a Circuit 
 
 k ol As an example, consider the binary circuit whose defining equations 
 (2:1c) are the Boolean equations 
 (k'.l) z ± ' = z 2 v z^ 
 
 V =I i 
 
 z 3* = \ ( z i v z 2^ 
 
 z k = S 
 This circuit, if represented by a logical diagram, would consist of two "not" 
 elements, an "or" element, and a special element for producing the function 
 
 -9- 
 
V 
 
 ll 
 
 i 
 
 ! 
 
 
 r 
 
 I 
 
z, (z. V z ) They are to be connected as in figure 1, where 
 4 1 , ^ 
 
 W T 
 
 Figure 1 
 E represents the special element. 
 
 4.2 If one writes the W relationships between the sixteen states and the 
 corresponding J% relationships it can be shown that there are four equivalence 
 sets. They may be designated by A,B,C, and D as follows. 
 
 A contains (0000), (0010), (0011), (0100), (0110), (Olll), (1000), (1011), (1100), 
 
 (1111) 
 B contains (0001), (0101) , (1001), (1101) 
 G contains (1110) 
 D contains (1010) 
 
 We have A^B, A^C, A^D, and C ^D„ We note also that B and D are final sets, 
 while A is pseudo-final and C is neither final nor pseudo-final. Since (1010) is 
 an equilibrium state, we see by (3 : ^) that its set contains no other state and 
 must be final, 
 
 4.3 If we start with the initial state (llll) we may illustrate some of the 
 possible allowed sequences. 
 
 (4:2) 
 (4:3) 
 (4:4) 
 (4:5) 
 
 (1111), (1010) 
 
 (1111), (1110), (1010) 
 
 (1111), (1101), (1001), (0001), (0101), (1101), (1001), ... c 
 
 (1111), (0111), (0110), (0100), (1100), (1000), (0000), (0010), 
 
 (0110), (0100), ... . 
 
 The last two allowed sequences are infinite having cycles of four and six states 
 respectively. 
 
 Sequences (4:2) and (4:3) have the final set D as their terminal set. Since 
 this set contains just the equilibrium state (1010) we see that both these allowed 
 sequences are finite. The sequence (4:2) proceeds directly from A to D while 
 (4:3) goes through the intermediate set G before terminating in D. 
 
 -10- 
 
1 
 
 ll ! 
 
 II 
 
 lis 
 
 ill i" 
 
Sequence (k°k) goes from A to B, and since B is final this must be its 
 terminal set. This sequence enters a cycle of states in B and does not terminate. 
 
 Sequence (hz^) remains, indefinitely, in the pseudo-final set A. It may 
 appear as if condition (3? 3b) is violated in the cycle because the fourth signal 
 never changes after the first two states but since a^' (k) = a. (k) for states 
 (0110) and (0010) we see that no violation has occurred „ 
 
 5* Speed Independence 
 
 5.1 In the previous discussion we have sought to describe the behavior 
 of a circuit by means of the concept of an allowed sequence. In (3»F) we saw 
 that the circuit eventually passes into a final or pseudo-final set of states 
 and stays in this set from then on. If the terminal set consists of one state, 
 this means that the circuit goes to equilibrium and the allowed sequence terminates 
 Otherwise the circuit may never reach equilibrium but one may regard the final or 
 pseudo-final set, which perpetuates itself, as a sort of dynamic equilibrium. 
 
 5.2 Of special interest are those circuits in which the ultimate behavior 
 of the circuit does not depend on the relative speeds of the elements . Such 
 circuits, which will be called speed independent, may be designed without regard 
 to time tolerances and capacities of elements and wiring. Hence they should be 
 easier to design and more reliable than asynchronous circuits which require time 
 tolerances on the elements for proper operation. 
 
 There remains the problem of selecting a suitable definition for speed 
 independence in asynchronous circuits <, One might choose the requirement that all 
 allowed sequences starting with a given initial state u shall terminate in an 
 equilibrium state m. This requirement has been expressed before in slightly 
 different terms by another author , and it has the advantage that it ensures a 
 unique final condition for the circuit „ On the other hand, it precludes the 
 possibility of having speed independent circuits which "cycle" indefinitely 
 (within a final or pseudo-final set) and for this reason we shall use a somewhat 
 broader definition for speed independence „ 
 
 (5°l) A circuit is said to be speed independent with respect to an 
 
 initial state u if there exists a final set M such that every allowed 
 sequence beginning with u contains a state in M. 
 
 ■11- 
 
(5:A) If a circuit is speed independent with respect to u, then the 
 terminal set of every allowed sequence starting with u must be M. 
 
 Proof: Let an allowed sequence under consideration be u, a(l), a(2), ... , 
 and let a ( j ) be a state of the sequence which is in M. Then a(j),a(j+l), ... 
 must all lie in M for if a(k) with k > j is in M*, then M & M*, which is 
 impossible. Thus M is the terminal set of all allowed sequences starting with u. 
 
 Theorem (5 'A) shows that the ultimate behavior of the circuit, when placed 
 in state u, will not depend upon the relative speeds of the elements . That is, 
 we interpret the rather loose concept of ultimate behavior as meaning a speci- 
 fication of which terminal set is attained by an allowed sequence. Thus if all 
 allowed sequences starting with u have the same terminal set we mean that the 
 circuit will always arrive, ultimately, at a unique static or dynamic condition. 
 
 (5:B) A circuit is speed independent with respect to u if and only if 
 
 U, the set of u, is followed by just one final set and no pseudo-final 
 sets . 
 
 Proof : Assume U <$ M, where M is final, and that U is followed by no other 
 final set and no pseudo-final sets. Then any allowed sequence u, a(l),a(2), ... 
 must have M as its terminal set, for if the terminal set T of the sequence is 
 not equal to M then U & T in contradiction of the hypothesis . 
 
 Assume the circuit is speed independent with respect to u. Now if U & T, 
 where T is either final or pseudo-final but not equal to M, we may construct an 
 allowed sequence whose initial state is u and whose terminal set is T by (3°G). 
 Since by hypothesis this sequence contains a state m of M, we have M ^ T which 
 contradicts the assumption that M is final. 
 
 5-3 When we face the involved problem of circuit design it becomes apparent 
 
 that (5*1) is not a convenient definition for speed independence from the point 
 
 of view of applications . It is usually difficult to determine whether or not a 
 
 given circuit is speed independent since the number of states, sets, and allowed 
 
 sequences starting with an initial state u may be very great. Therefore, in the 
 
 following paragraphs we shall discuss other conditions which do not have this 
 
 disadvantage yet imply speed independence . 
 
 1 2 
 5 '4 One such condition which has been used by other authors ' is: 
 
 (5'2) A circuit is totally sequential with respect to an initial state 
 
 u if and only if there is only one allowed sequence starting with u. 
 
 -12- 
 
ll ! 
 H 
 
 
This condition does imply speed independence since U, the set of u is 
 followed by some final set M. Hence, by (3:G) the single allowed sequence 
 starting with u must have terminal set M. 
 
 If we assume that u,a(l),a(2), ... is the only allowed sequence starting 
 with u then we must have u $a(l), ... ,a ( j ) #£ a(j+l), ... but there can be 
 no other state b(j+l) such that a ( j ) 5^ b(j+l). Thus a(j+l) = a'(j) and by 
 (3:1) we see that there is at most one signal a.(j) of a(j) for which 
 a.(j) 4 a -'(j)* For this signal we must have either a . ( j ) = a . ' ( j ) + 1 or 
 a.(j) = a.'(j)-l. Thus, only one signal tends to change at a time in a totally 
 sequential circuit so that no circuits can be totally sequential and have 
 parallel changes occur in them. Many modern computers use just such parallel 
 changes to achieve their extraordinary speeds. Therefore we seek some other 
 condition to impose on our circuits which is less restrictive than that they be 
 totally sequential. 
 
 (5:3) A circuit is semi -modular with respect to an initial state u if 
 and only if for all states b and c such that u <£ b and b 0\ c the 
 relationship c 2R b 1 also holds. 
 
 ^ .k The name "semi -modular" was given to this condition because of its 
 connection with a semi -modular lattice which will be discussed later. An 
 immediate consequence of (5: 3) is the property that for any three states a, b, 
 and c such that u cr a, a £R b and a (K c there must be a fourth state d such that 
 b 3R d and cj^d. We see that d = a' has these properties. A more useful state 
 d of this type is defined by: 
 
 (5:^-) If a circuit is semi -modular with respect to u and u era, a J<b, 
 and a^ c then the state d = M[a ; b, c] is defined componentwise 
 by 
 
 (5:ta) d. = Max (b., c. ) if a . < a. ' 
 
 and 
 
 (5 : kb ) d . = Min (b . , c . ) if a . > a . ' 
 v ' l v \' l l—i 
 
 This definition is not inconsistent in case a. = a , ' since then a.=b.=c. . 
 
 l i l l i 
 
 (5:5) In (5:*0 a lR d, b# d, and c # d. 
 
 Proof: Since b. and c. both satisfy the conditions of (3:1) we see that d. 
 i i J v ' l 
 
 must also and hence a?Rd. Now if a . < b . < a . ' we have b .' < d . < a . ' < b ' by 
 
 l—i.i .1—1—1-1 
 
 (5:3) and (3:1). Similarly if a . > b . > a . * we have b. > d . > a . : >b.'. However, 
 
 -13- 
 
if Id . = a. ' then we have b = d. . Hence in any case we satisfy (3:1) giving 
 biRd. Similarly c }R d . 
 
 (5:6) In a circuit semi -modular with respect to u let u <ra(0) and let 
 
 a(0),a(l), ... ,a(k) be a partial allowed sequence. If a(0)#? b(0) 
 then we may define a sequence b(0), b(l), ... ,b(k) where 
 b(«j) = M[a(j-1) ; a(j), b(j-l)] when j = 1, 2, ... , k. 
 
 Proof : Since u cf a(0), a(0) 0? a(l), and a(0) $ b(0) we may form b(l) and 
 by (5:5) we have a(l) 2R b(l). Assume b(j) may be defined as in (5:6) and that 
 a (j)$ b(j). Then since u$ a(j) by (3: 9b) and a(j)£^a(j+l) we may define 
 b(j+l) and by (5:5) we have a(j+l)$ b(j+l). Hence by induction we may define 
 b(j) for J = 1, 2, ... , k. 
 
 (5:C) A circuit which is semi -modular with respect to u is speed 
 independent with respect to u. 
 
 Proof : We shall make use of (5:B) and show that U_, the set of u is followed 
 by just one final and no pseudo-final sets. 
 
 To show that U is followed by just one final set let us assume that there are 
 two distinct final sets M and M* such that U £ M and U^M*. By (3:8) and (3:C) we 
 form a partial allowed sequence u,a(l),a(2), ... ,a(k), m where m is a state in M. 
 Let m* be some state in M*. Now u^# by (3:C) but m^m*, (m* does not follow m) 
 since M is a final set. Let a(j+l) be the first state in the sequence for which 
 a(j+l)J? m*. (Take a(0) = u and a(k+l) = m for notational convenience.) Thus 
 a (j)<3> m*. Construct a partial allowed sequence a(j), b(l), b(2), ... ,b(h), m*. 
 (Again let b(0) = a ( j ) and b(h+l) = m* for notational convenience.) By (5^6) we 
 may define c(l) = M[a (j ) ja (j+l) ,b (l)] and c(p) = M[b(p-l); b(p), c(p-l)] for 
 p = 2,3, ...,li+l. Also by (5:5) we have a(j+l)3? c(l) & c(2)# . .. ^ c(h+l). 
 Now we obtain a(j+l)<7 c(h+l) by (3:9b). Also c(h+l) ^ m* since a (j+l),*7 m* and 
 by (5:5) nr* = b(h+l) o" c(h+l). Thus M* cannot be final in contradiction of our 
 hypothesis . 
 
 Next assume that U is followed by a pBeudo-f inal set T composed of states 
 t(0),t(l), ... ,t(k). Since T is not final there must be some set D =f T such 
 that T & D. Construct a partial allowed sequence t(0), ... ,d, where d is a 
 state in D. Let q(0) be the first state in this sequence which is not in T. 
 Thus, we have t(j)$3 a(0) for some state t(j) in T which directly precedes q in 
 the sequence. We lose no generality by making j = since the numbering of the 
 states in T is arbitrary. Thus we take t(0)$^q(0). 
 
 -ll+- 
 
II 
 II 
 
 I 
 
 I 
 
 Il , ! > 
 I 
 
 !! |J 
 ii i« 
 
Construct a partial allowed sequence t(0), ... ,t(l), ... , ... ,t(k), ... ,t(0) 
 in the manner of the proof of (3:G) so that all states in T appear in the sequence. 
 States in this partial allowed sequence may be renamed p(0),p(l),p(2), . . .,p(r),p(0), 
 where p(o)-=t(0) and all the other k states have been renamed as one or more of 
 the states p(j). Since utfp(O) by (3:C) we may define 
 q(j) = M[p(j-1) ; p(j), q(j-l)] for j = 1,2, ... ,r and 
 q(r+l) = M[p(r) ; p(0), q(r)] by use of (5:6)* By (5:5) we have 
 q(0)$ q(l) $. ... ^q(r+l). By (3:9b) we have q(0) <£q(r+l). Now q(r+l) cannot 
 lie in T, for if so we would have p(0)£R q(0) & q(r+l) and q(0) would also lie 
 in T. Thus p(0) \ q(r+l) so that p(0) and q(r+l) must differ in at least one 
 signal, say p i (0) \ q ± (r+l). This implies p i (j) 4 ( l i (j) f ° r all J = 0,1, ... ,r, 
 for if p.(j) = q.(j) then p. (j+l) = q. (j+l) by (5:^) and hence by induction 
 p. (0) = q. (r+l), which violates our assumption. 
 
 We assume now that p. (0) < q. (0) . Then it follows that p. (j ) < q. (j ) < p. ' (j ) 
 for all j = 0,1, ... ,r. For assume it is true for j = 0,1, ... ,s. Then since 
 p(s)2R q(s) and p j _ (s ) < q ± (s) < p ± « (s), we have q^s+l) = Max [p i (s+l), q i (s)] . 
 But q. (s+l) 4 P- ( s +l) and p( s +l)y? Q.(s+l) so p. (s+l) < q. (s+l) < p. ' (s+l) . Since 
 V ± U) < Pi' (J) for all j = 0,1, ... , r , we have p.(0) < p.(l) < ... < p. (r) < p. (0). 
 Hence p ± (0) = p. ( j ) < p.' (j) for all j = 0,1, ... , r , so that t. (0) = t.(j) < t.' (j ) 
 for all j = 0,1, ... ,k. This contradicts the assumption (3:17) that T is pseudo- 
 final. 
 
 If, on the other hand we assume that p. (0) > q. (0) we may make a similar 
 argument with the sense of the inequalities reversed and giving t. (0) = t.(j) > t.'(j) 
 for all j = 0,1, ... ,k. This also contradicts assumption (3:17) • 
 
 .5.5 The condition (5*-3) for semi -modularity is a convenient one to use, 
 since it is defined with respect to individual transitions which may occur between 
 states and does not refer to allowed sequences and the system of states as a whole. 
 These transitions may be examined individually to see if they satisfy b $ a ' when- 
 ever a ^ b, but no such method seems possible if (5:1) is used. It is true that 
 (5:3) is more restrictive than (5:1) but, in practice, no useful circuits have been 
 found which satisfy the weaker and not the stronger condition. Parallel changes 
 for example, may occur, under (5:3) and common computer circuits such as counters, 
 parallel adders, and shifting registers have been designed subject to it. Although 
 circuit design techniques will be discussed in a later paper we should note that 
 all these techniques require at least the assumption of semii-modularity. 
 
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Bibliography 
 
 1. D. A. Huffman, "The Synthesis of Sequential Switching Circuits", 
 Journal of the Franklin Institute, Vol. 257, Nos . 3 and k (195*0 
 
 2. G. H. Mealy, "A Method for Synthesizing Sequential Circuits", 
 Bell Systems Technical Journal, September 1955 , P-P- 10^5-79- 
 
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