510.84 I £6r no. 997-1005 1979-80 lncompl . copy 2 CENTRAL CIRCULATION BOOKSTACKS «Jf ? M S °r n c} } ar S^g this material is re- fee of $75.00 for each lost book A- UnlvrX mOY reiU,t ' n dlSm, "°' *«" TO RENEW CALl TEIEPHONE CENTER, 333-8400 L162 6 10. S L l -yib. I60H Report No. UIUCDCS-R-81-1004 UILU-ENG 81 1706 A SYSTEMATIC APPROACH TO THE DESIGN OF STRUCTURES FOR ARITHMETIC "■»* -**>«+* by James E. Robertson imr >c> '«» % r-l, where r is the radix. 2.6 A composite digit set is a combination of two or more appropriately weighted digit sets. For example, an adder output a is usually represented by a carry c and a sum s, with a = re + s. If the diminished cardinalities of the digit sets of a, c and s are 6 , 6 and 5 respectively, then 6 = r6 + 6 . If all a c s J acs possible values of a are to be consecutive integers, (and hence conform to the definition of a digit set) it is necessary that 6 > r-1. s — 2.7 The range of the diminished cardinality of a digit set is 1 £ 6 <_ 2 (r-1). The lower limit is essential; the upper limit is arbitrary, but sufficiently large for most practical purposes. 2.8 The magnitude of the smallest Integer of a digit set is the off- set co of the digit set. A normalized digit set is converted to a generalized digit set by subtracting the offset co from each value of the normalized digit set. 2.9 Zero is always an element of a digit set. This implies that the smallest value -co satisfies 2 can be represented as combinations of two and three valued digit sets, with appropriate binary weights. These are useful in the design of radix 2 (k an integer) structures, and are listed in Table 2.1. It is useful to refer to the class of digit sets of a given diminished cardinality without specifying the offset. This generality can be achieved by adopting the convention that a letter without superscripts designates the class of all digit sets of the corresponding diminished cardinality, and a superscript is always used when a specific offset is necessary. In particular, a normalized digit set will always be designated by a letter with superscript 0. Designation 6 representation bi a 1 a 1 b 2 b 2 c 3 2a+a 2 d 4 2a+b 3 e 5 2b+a 3 f 6 2b+b 4 g 7 4a+2a+a 3 h 8 4a+2a+b 4 i 9 4a+2b+a 4 J 10 4a+2b+b 5 k 11 4b+2a+a 4 1 12 4b+2a+b 5 m 13 4b+2b+a 5 n 14 4b+2b+b 6 o 15 8a+4a+2a+a 4 P 16 8a+4a+2a+b 5 q 17 8a+4a+2b+a 5 r 18 8a+4a+2b+b 6 s 19 8a+4b+2a+a 5 t 20 8a+4b+2a+b 6 u 21 8a+4b+2b+a 6 V 22 8a+4b+2b+b 7 w 23 8b+4a+2a+a 5 X 24 8b+4a+2a+b 6 y 25 8b+4a+2b+a 6 z 26 8b+4a+2b+b 7 A 27 8b+4b+2a+a 6 B 28 8b+4b+2a+b 7 C 29 8b+4b+2b+a 7 D 30 8b+4b+2b+b 8 E 31 16a+8a+4a+2a+a 5 Table 2.1 Binary representation of digit sets of higher cardinality. 3. Structures for Addition and Subtraction and their Properties The basic properties of structures for addition and subtraction are quite simple, and follow directly from the basic principles of arithmetic . 3.1 The diminished cardinality of the output digit set is equal to the sum of the diminished cardinalities of the input digit sets. The proof is trivial. Let the j input sets be {-to,, -oj.,+1, •••, -oj-,+6, ) with diminished cardinality 6 , {-to -to +1, ..., -to +6„} with diminished cardinality 6„, • . • , and {-to., -to. +1, ..., -to .+6.} with diminished cardinality 6.. The digit set of the output is the sum of the inputs and is j j j j {-£ w- » ~£ to. + 1, ..., -E id. + X {.}. The diminished cardinality of 1=1 X 1=1 X 1=1 X 1=1 1 j of the output digit set is £ 6. and is clearly the sum of the 1=1 X diminished cardinalities of the input digit sets. 3-2 The offset of the output digit set is equal to the sum of the offsets of the input digit sets. The proof is included in the proof of the previous paragraph, since the offset of a digit set is the negative of the smallest value of the digit set. Since the smallest value of the output digit set is the sum of the smallest values of the input digit sets, the same is true of offsets. The proof also follows from the observation that if s = b + d, then (s - to ) = (b -to^) + (d -to ,) if co s = to^ + io,. 3.3 If s = b + d, then -s = (-b) + (-d) . Each structure for addition has a negative, found by replacing each of the inputs and outputs by its negative. If all inputs and outputs are uniquely represented (i.e., not redundant), the logical designs of a structure and its negative are identical. For redundant digit sets (see section 5), difficulties are apparently encountered 10 with symmetric digit sets, but these are easily resolved. For each symmetric digit set, there corresponds a specific binary state assignment; for the negative digit set, found by replacing each value by its negative, there also corresponds a specific state assignment. Since the design process is exhaustive and includes all state assignments, the problem is reduced to one of identification of the correct state assignment. The correspondence between digit set formats and state assignments of Table 5.3 are made with this in mind. In summary, a structure for addition and subtraction transforms one or more input digit sets into one or more output digit sets in such a way that certain properties behave in predictable ways. In particular, diminished cardinality and offset remain unchanged, hence it is appropriate to refer to the diminished cardinality and offset of a structure . 3.4 Classification Conventions for Structures Structures may be classified in a general way by listing, in order, the radix r, the diminished cardinality 5 of the structure, the number j of input digit sets to the structure, and the offset ^ of the structure. These parameters are listed as a sequence of numerals, separated by periods, in the order listed above. Examples of commonly used structures are 2.2.2.0 Half adder 2.3.3.0 Full adder 2.3.3.2 Full subtracter This classification scheme is useful for compiling a comprehensive catalog of structures, but it must be augmented with additional parameters, particularly for higher values of 6. Among the parameters that may need additional specifications are 11 1. Distribution of 6 and w among the input digit sets. 2. Distribution of weighted values of 6 and w among the output digit sets. 3. Which one of several possible logical designs is used. The structural types may be catalogued in order of complexity, beginning with the simplest, as indicated in Table 3.4.1 and Figure 3.4.1, a a b 2a a 2a a 2.2.1 f f f 1 /JWJX 2.2.1 i 2.2.2 i .1 1 2.3.2 2.3.3 2.2.2 T ft t r • ' i b a a b a a a a 2.3.2 2a b 2a b 2a b 2.3.3 2.4.2 f A J L 2.4.3 /JL_ ...f _, 2 .4.4 2.4.2 -t f tt ^\ A, 2.4.3 b b baa a a a a 2.4.4 Table 3.4.1 Figure 3.4.1 Simple structural types 12 All structures catalogued in this way preserve diminished cardinality and the variants preserve offset as well. The crucial observation, initially made by Nguyen , is that the more complicated structures can be realized as combinations of the three simplest structures 2.2.1, 2.2.2, and 2.3.2. For example, the full adder 2.3.3 can be realized as a combination of 2.2.2 and 2.3.2 as shown in Figure 3.4.2. The same pair of simple structures may also be combined in a different way to form the carry-save adders 2.4.3, as shown in Figure 3.4.3. Note that the carry save adders are a subset of structures 2.4.3, since they require that the carry output 2a must be independent of one of the a inputs. This classification method, useful for cataloging, is included here for historical reasons, and has been superseded by the design language described in the next section. 2a a 2.3.2 b ^~ 7N 2.2.2 TT a a 2a 2.2.2 2.3.2 TT b a Figure 3.4.2 Full Adder Figure 3.4.3 Carry-save adder * Nguyen, Diem Dinh, private communication, Feb., 1980 13 4. A Design Language for Structures 4.1 Normalized Structures The design language for structures expresses relations between output and input digit sets of structures for arithmetic. The variables represent digit sets; equations then characterize structures. The design language is described first for normalized digit sets; extensions to other digit sets, including the symmetric, are described next. Letters are used to designate digit sets; the letter a is used for a digit set of diminished cardinality 1, b for diminished cardinality 2, c for diminished cardinality 3, etc. The superscript specifies the off- set, and the subscript is used to designate the format of the binary , , representation of the digit set. Thus a designates the digit set {0,1} 2 - - d the digit set {2,1,0,1,2}, and i the normalized decimal digit set {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}. If the superscript is omitted, the letter represents all digit sets, in general, of the implied diminished cardinality. The subscript is not used unless specification of a particular format is desired. There are three fundamental structural types, combinations of which yield most, but not all, useful structures for binary arithmetic. These are, for normalized digit sets, 1) Conversion network a + a = b 2) Generalized half adder b = a + a 3) Carry generator 2a + a = b + a The second equation represents the structure shown in Figure 4.1. Note that in the equation the expression to the left f the symbol "=" is the output; that to the right designates the inputs to the structure. The relation 0,1,2" =" is not reflexive as is mathematical equality 1 1 tin Figure 4.1 Generalized Half -adder a a b l 1 1 1 1 1 1 2 14 in the sense that b = a + a and a + a = b may represent different _ * structures. Only in the special case of format l can we write v _ _ u . . .. . b = a + a = b , since the digit set b, is represented by two binary digits in such a way that each value of b 1 is the sum of the values of the two as. In the special case of format 1, Table 4.1. Format 1 no hardware is required for either n 0,0 b n = a + a or a + a = b.. . The approach here requires that all structures preserve diminished cardinality; i.e., the diminished cardinality of the outputs must equal the diminished cardinality of the inputs. In particular, the generalized half-adder b = a + a is a structure that converts two binary digit sets into one three-valued digit set. The usual usage of the expression "half-adder" implies that two binary digits are used to represent the digit set of the output and one is associated with a carry and the other with a sum, that is, b„ = a + a. In the absence of the subscript, b may be represented by any binary format or by some form of three-valued logic circuitry, with no connotation of a separate carry. In a purely symbolic sense, without reference to the structures implied, the relation "=" is reflexive for the three fundamental structures. Both b = a + a and a + a = b are included as fundamental structures. It is also correct to write b + a = 2a + a , since there is a fanout function , ... ,0 0,0 ,,0 0,0 a + a = 2a , yielding b +a =a +a + a , and b = a + a . The fanout function must be used with extreme care. In particular, it is not correct to use the fanout function a + a = 2a followed by *See section 5. 15 b° = a° + a°, and conclude that b° = 2a° since b is the digit set {0, 1, 2}, and 2a° is the set {0, 2}. The arrangement of Fig. 4.2 is valid, however, since 2a° + a° is the digit set {0, 1, 2, 3} which can The situation is perhaps best stated be decomposed to the two digit sets a = {0, 1} and b - {0, 1, 2}. q *o T T - ± - by saying that for good design it is desirable to use o o . the structure implied by 2a + a = b + a . It is r o therefore necessary to treat the relation "=" as non- reflexive, and adopt the convention that the expression for the outputs is to the left, and the expression for the inputs is to the right of the symbol "=" . T ^ ji 7K 2a lo Fig. 4.2 Structure for b +a =2a +a A structure is called "decomposable" if the diminished cardinality of the output is identical to the diminished cardinality of the inputs. Since it must be possible to represent, at the output, all input combinations, the input diminished cardinality cannot exceed the output diminished cardinality. It is, however, necessary to consider, for more complex configurations, structures which are not decomposable, for which the output diminished cardinality exceeds the input diminished cardinality. Such a structure can be made decomposable by providing "mythical" inputs to the extent necessary to achieve balance in diminished cardinality. The mythical inputs can then be used to simplify the structure. Examples of the use of mythical inputs to obtain decomposable structures are found in the design of parallel counters, and occur when the number of input bits differs from 2^-1, with k an integer. The simplest example is a counter for two input bits. The input is a + a , with diminished cardinality 2, and the output is 2a + a with 6=3. Hence for a decomposable structure one mythical input is necessary, and the expression for the decompos- able structure is 2a + a =a +a + a ( which is a full adder). The structural simplification is that of a full adder redesigned with one input always zero, which reduces the structure to a half adder of the type b„ = a + a . 16 Note that there is no cancellation law in the design language o . . . ,'..-. n . of structures. The expression 2a + a = b + a is valid, but 2a = b is not, since 2a represents the set {0, 2} and b represents the digit set {0, 1, 2}. 17 4.2 The Design Language for Structures with Offset Negative values may be introduced into digit sets in two ways. Let the arithmetic property of a structure be given, for example, by the expression s = y + z where s is one value of the output digit set and y and z are values of the input digit sets. Clearly, s-w = y - u> + z -w~ Eq. 4.1 and also, -s = -y + (-z) Eq. 4.2 As previously noted, offset can be introduced into the notation by use of non-zero superscripts. If, for normalized digit sets (oj = 0), o , , ■ C IK o 01 u 10 2a + a = b + a , the expressions for w = 1 become 2a + a = b + a , or 2a + a = b + a where b is {1, 0, 1} and a is {1, 0}. For oj = 2, 2a 1 + a° = b 2 + a , or 2a 1 + a = b 1 + a 1 , where b 2 is {2, I, 0} 112 1 For (D = 3, 2a +a =b +a Note that, because of the condition that zero is a member of every digit set, the range of the negative offset to is limited to CKuj<_6, where 6 is the diminished cardinality of the digit set. It is also convenient to employ the notation -a = a for the digit set {l, 0}, -b = b 2 for {2, I, 0}, -b 1 = b 1 for (l, 0, 1}, etc. The use of the symbol "-" is unnecessary, but convenient, just as equation 4.2 is unnecessary if equation 4.1 is applied exhaustively. Both equations 4.1 and 4.2 preserve offset. This clearly follows from a).. = uj + w_ for equation 4.1. For equation 4.2, observe first that if a digit set has diminished cardinality 6 and offset w, the negative has offset 6 - w. Since a decomposable expression preserves both 6 and w, negating the expression also preserves 6 and w (i.e.) the values of 6 and oo for the expression to the left of the relation "=" are equal to the corresponding value to the right, both before and after the operation of negation. 18 The fundamental structures, with offset variants included, are: 2. 2. 1.0. a a° + a° = b° 9 11 ° ° k 1 ° 1 u 1 2.2.1.1 a-a=b a+a=b 2. 2. 1.2. a a 1 + a 1 = b 2 o o o n u° ° j ° 2.2.2.0 b =a +a 2.2.2.1 b=a-a b = a + a 2.2.2.2 b 2 = a 1 + a 1 o o. o n o ° ° k° , ° 2.3.2.0 2a +a =b +a 2. 3. 2.1. a 2a -a =b +a 2a +a =b + a oo.oik o° °k° o 1,0 1 2.3.2.1.b 2a -a =b -a 2a +a =b + a 2. 3. 2. 2. a 2a 1 + a° = b 2 + a° 2. 3.2. 2. b 2a 1 + a° = b 1 - a° 2a 1 + a° = b 1 + a 1 2.3.2.3 2a 1 + a 1 = b 2 + a 1 For generality, the fanout functions are also listed: o o i n k ° , ° o ° 2.2.1.0.b a +a =2a 2. 2.1. 2. b a 1 + a 1 = 2a 1 o i i n o ° ° ° 2.1.1.0 2a -a =a 2.1.1.1 2a +a =a -2a + a = -a 19 5. Binary Formats for Throe-Valued Digit Sets For binary arithmetic, the only permissible digit sets are of cardinality 2 or 3. The problems introduced into logical design by digit sets of cardinality 3 have been studied extensively. A three-valued digit y* can be represented by two binary digits n and y, which have four states. It is assumed temporarily that y* has four values, the fourth value designated by x. The assignment of four states to four values can be made in 4! = 24 different ways, as indicated in Table 5.1. The fourth value of y*, designated x, may itself have four values; either of the three values of y* may be repeated, or x may be the logical design "don't care". The use of the "don't care" state may simplify the design if y* is an input, but may complicate the design if y* is an output, since the design must be such that n and y cannot have the values assigned to the "don't care" state. The fact that the fourth state x has four values apparently increases the number of state assignments from 24 to 96, each of which corresponds to a distinct logical design. Table 5.2 indicates in part how the labor can be significantly reduced. First, the twenty four state assignments of n and y can be reduced to three groups of eight, each of the three groups containing eight state assignments equivalent under permutation and negation of n and y. For example, if we have the Boolean equations for a design using state assignment 1, the equations for assignment 8 can be obtained by replacing y by y in the equations, etc. Thus the one design for state assignment 1 is representative of the eight designs of the group under permutation and negation of n and y. 20 The twelve representative designs can be reduced to nine because of the duplication in the values of y* in three cases. For example, fory* having the values 0,1,2 with x = 0, the first and fourth rows may be interchanged. Group 1 then becomes identical with group 3, and one of the representative designs is unnecessary. Similar results are obtained by interchanging rows 1 and 3 for x = 1, and for rows 2 and 3 for x = 2. For the nine designs, any one state assignment of the group may be chosen as representative. The actual assignments selected and detailed designs are given in tables 5.3 and 5.4 and section 6. For brevity, it is convenient to use the word format for the digital values corresponding to a state assignment. The next problem is the choice of nine formats, each corresponding to one of eight state assignments of each group. Although which of the eight state assignments of a group corresponds to a particular format is theoretically arbitrary, certain choices lead to an algebraic relationship between format values and the corresponding state assignment. Consider Table 5.3, in conjunction with Table 5.2. If the double zero, 1,1 format (#1) of x* is associated with either state as- signment^ or state assignments of group 2 of Table 5.2, the result is that x* = x - 5. Format 2 of Table 6.3 for the particular state assignment chosen has the relationship x* = -2? + x, with £x = 0, hence the "don't care". Similarly for format 3, x* = 2£ -x, with £x = 0, and for format 4, 5 is the sign and x the magnitude of *•*, or x* = (l-20x. For the remaining formats of Table 5.3, the choices for Formats 5, 6, and 8 are arbitrary. Formats 6 and 7 are a pair with corresponding rows negatives of one another, as are Formats 8 and 9. 21 The choice of formats for the digit set {0,1,2} involves more arbitrary choices. The formats of Table 5.4 are found by adding 1 to the formats of Table 5.3, and complementing either n, or y, or both in such a way that is the value of y* in the first row. For the first three formats, the following relationships exist between y* and n and y. Format 1 y* = n + y Format 2 y* = 2r> + y, ny = Format 3 y* = 2r] - y ny = No explicit relationships are believed to exist for the remaining formats. 22 cr a> en 3- n> ro -p» to c+ O) c+ to to to' 3 rt> 3 r+ Q. O O C -s < o -h << * X r\3 — o - o o o o 3 *< o -; o o o 3 << - o o o o << o o -; o o o o o - o << o o o - o o o o o - 4 o o o o - J *< o o o o - o o o o - << o o o o - 3 << o o o o - 3 X -i o H * X f\3 — ' CD © - o o o o 3 << o - o o o << - o o o o J << © o - o o o J << © o o - o o a © o o - o o J «< © — 1 o o o o << © —J o - o o o << © - o o o o 3 © o o - o o 3 © o o o -; o J << © o o o - o J *< © X — ' O — 'I * X * 23 o o ro — ' o o ro — 1 o — 1 _. r>o —1 o ai O" no ro — ' o — i a> en l\3 — i O — 1 o t/> o — < — • o c+ o> r+ a> Q) co —j o _, o CO — ■ o o — ' 00 a> cl- O — > CD — I to O — ' — i o Q) 00 c+ 3" -s O — -* o — * a> —J o o —J n> to -s o c -a O —J —J o CO — ' o - -* o c 3 a. -s o 1 1 o -a o —J o —J a> -s 3 c ri- ot 3 fl> c+ — ■ o o — ■ — ■ o — > o — ■ o o — ' o — ■ o — ■ o o o o o o * S: © Qci [us* <<' 3! © © 3 I (o j! Cq * o ro o ro ^ ro ro ro o o o o — • — • o o O — ' — ' o — ■ — • o o — ■ O O — ' O O — ■ — ' O — ' — ■ o O O — ' — ■ — ■ O O — ' CD — ' — ■ o — i — • o o O — > — ' o O O — ' — ' — • O O — ' — ' — • o o — ' o o — ■ O O — ■ — ' o o o o o CD * © «' © o -M — . —. o — '1 * © 4,® :■© © 3.© 5'® 24 State Assignment Format number of x* |x 1 2 3 4 5 6 7 8 9 00 01 1 1 T 1 1 1 T 1 T 10 T D.C. D.C. T T l 1 T 11 T 1 T D.C. T l T 1 Table 5.3 Formats for the symmetric digit set {1,0,1} State Assignment Format number of y* ny 1 2 3 4 5 6 7 8 9 00 01 1 1 D.C. 1 D.C. 1 2 1 10 1 2 2 2 1 1 2 2 2 11 2 D.C. 1 1 2 2 2 1 Table 5.4 Formats for the normalized digit set {0,1,2} 25 6. Logical Design 6.1 Notation There appears to be no satisfactory notation for logical design, when designs are used in combination to form more complex designs. The difficulty is that it is notationally necessary to distinguish between outputs and inputs; but when a combination is considered, the output of one is an input to the other, and the notations are incompatible. For the designs of the fundamental structures, the following notation is employed: a) For inputs: Digit set .0, 1 w;y Digit set 1, x;z Digit set 0_, 1 , 2 n>y Digit set 1, 0, 1 £,x b) For outputs Digit set Q_, 1 s;u Digit set 1, t;v Digit set , 1 , 2 a jS Digit set l, 0, 1 x,t For logical design purposes, a three valued digit set is represented by a pair of letters; the first Greek and the second the corresponding English letter. 6.2 Designs of the Fundamental Structures The variants of the basic structures are shown in block diagram form in figures 6.2.1, 6.2.2, and 6.2.3. The design of 6.2.1c is formally identical to the design to 6.2.1 .a except that n and y represent the digit set {0,T , 2} and s and u represent digit sets { 0,1'}. Similarly, the design of 6,2.2c is formally identical to 6. 2. 2. a, 6.2.3.f is identical to 6. 2. 3. a, and 6.2.3e is identical to 6.2 .3 . b . For this reason, logical designs for 6.2.1c, 6.2.2c, 6.2.3e, and 6.2.3f are not included in the tables of logical design. The pairs of structures referred to above are negatives of one 26 another with a = -a and b * -b . It should be noted that structure 6.2.3d is the negative of 6.2.3c, with b » -b . The design of 6.2.3d may there- fore be inferred from 6.2.3c, but in a more complex way. Basic structures 0,1 0,1 ,1 T,o i,o r,o _±. T T t f t 1 1 .2! a + a = b : 1 f ' : a ♦ a - b° ! 1 0,1 J a + a = b T " T 0,1,2 T.0,1 ZJ.O (a) (b) (c) Figure 6.2.1 Converter Structures 0,1,2 TXl 2,T,0 t t t 1 b° = a° + a ] .1 1 ib = a + a 1 . .2 1 1 b = a + a T T / \ / \ A fr ' 0,1 0,1 (a) 0. l l (b) ",o T,o T,o (c) Figure 6.2.2. Generalized Half-Adder Structures 27 0,2 0,1 T 0,2 1,0 0,2 1,0 ° + a =b° + a ! I2A. 1 ^b^a 1 ! 2a° + a 1 ■ b 1 ♦ a t A 0,1,2 0,1 (a) t t 0,1,2 1,0 (b) 1,0,1 0,1 (c) 2,0 0,1 4 s * A 2,0 0,1 /IN /1\ -,r 2,0 1,0 t r I 2a 1 ♦a^b 1 .a 1 ! 2a 1 + a - 7+ a^a 1 + a 1 = b + a / r t 1,0,1 1,0 (d) 2,1,0 0,1 (e) ± _t 2,1,0 1,0 (f) Figure 6.2.3. Carry Generator Structures Consider Table 5.3. If l's are replaced by l's, and vice versa, corresponding to negation of digit set b\ formats 2 and 3 are interchanged. Thus the design of 6.2.3d for format 2 is the same as the design of 6.2.3c for format 3, and vice versa. Similarly, formats 6 and 7 and formats 8 and 9 are corresponding pairs under negation of b . It should be recalled that each format is representative of eight, under permutation and negation of 5 and x. For format 1, negation of b corresponds to permuting 5 a" d x i for format 4 > ? is ne 9 ated '> and for format 5, 5 and x are permuted. The detailed logical- designs are given in Tables 6.2.1 through 6.2.9 28 a + aO = bO a + a 1 = bl u = n U = X s = y v = ? b° = a + a° ,1 = a + a 1 a = w t = x s = y t = w 2a + a O = b O + a o 2a° + a 1 = b° + a 1 2a0 + a 1 = b 1 + a 2a 1 4- a = b 1 + a 1 u = wy v ny v riw s = w +< ri <+' y u = nx v yz v yz v — r\ (§) y + z u = xy v "£x v ^y v = £ + x + y t = £z v £x v xz s = £ + x .+ z TABLE 6.2.1 LOGICAL DESIGNS FOR FORMAT 1 29 a + a" = b u = r| s = nvy a° + a=b u = s" v = £ v x b=a+a a = wy s = w €) y b = a + a x = wx t = w © x ,00.00 as 2a+a=b+a u = n v wy s = w © y 2a+a=b+a u = ti v yz v = y © z 2a° + a 1 = b 1 + a° u = 1 (x v y) v = x ©y 2a 1 + a = b 1 + a 1 t = £ v xz s = x ® z TABLE 6.2.2 LOGICAL DESIGNS FOR FORMAT 2 30 0.0 a+a=b u = ny s = n 1,1 a+a=b u = £ v = £x D=a+a a=wvy s = w © y b=a+a t = wx t = w © x 2a+a=b+a u = n ( w v y) s = w © y 2a+a=b+a u = n(yvz) v = y €>z 2a+a=b+a u = £ v xy v = x ©y 2a 1 + a° = b 1 + a 1 t = ? (x v z) s = x © z TABLE 6.2.3 LOGICAL DESIGNS FOR FORMAT 3 31 0.0 a + a = b u = ny s = n v y ] J a + a = b u = ?x V = ex .o b = a + a a = w s = w 0y J j 1 b = a + a T = X t = w X , 0,0 2a + a = b + a u = ny V wy s - w ©y 1.0 2a + a = b + 1 a u = ny V yz V = y ©z 9 1,1 2a + a = b + a u = 5x V xy V = x ©y ,1 0.1 2a + a = b + 1 a t = £x V xz s = x © z TABLE 6.2.4. LOGICAL DESIGNS FOR FORMAT 4 32 a+a=b u = n s=y a + a = b u = x v = £ uO b=a+a a = wvy s = wy b=a+a x = wx t = wx o L - ^ 2a+a=b+a u = yvnw s = ny ©w 2a+a=b+a u = yvnz v = ny © z q ° 1 J - ~ <:a + a = b + a u = x v £y v = (£ v x) ® y 2a + a = b + a t = g v xz s = U v x) @ z TABLE 6.2.5. LOGICAL DESIGNS FOR FORMAT 5 33 0.0 a+a=b u = n s = ny 1 .1 a+a=b u = £x v = £ . b=a+a a=wvy s=wy b=a+a t = wx t = wx 2a+a=b+a u = n (w v y) s = ny © w 2a + a = b + a u = n(yvi) v = ny © z 2a° + a 1 = b 1 + a u = f (x v y) v = U v x) © y 2a + a = b + a t = ? v xz s = U v x) © z TABLE 6.2.6. LOGICAL DESIGNS FOR FORMAT 6 34 0.0 a+a=b u = n s = n v y 1,1 a+a=b u = 5 v = £x b=a+a a = wy s=wvy b=a+a x=wx t = wx 2a+a=b+a u = nvwy s = ny (J) w 2a+a=b+a u = 1 v yz v = ny ® z 2a+a=b+a u = £ v xy v = (c v x) (Dy 2a 1 + a = b 1 + a 1 t = I (x v z) s = (£ v x) 9 z TABLE 6.2.7. LOGICAL DESIGNS FOR FORMAT 7 35 ,0 /tn a+a=b u = ii v y s=n ^y a + a 1 = b 1 u = sG)x v = 5x u0 -v b=a+a a = wvy s=w ©y b=a+a x = wx t = w © x 2a+a=b+a u = riy v wy v ny s = r\y © w 2a+a=b+a u = iiy v ny v yz v = ny © z 2a +a 1 = b +a° u = £; x v £x v xy V = (£ v x) ©y 2a+a=b+a t = £x v £xz s = U v x) © z TABLE 6.2.8. LOGICAL DESIGNS FOR FORMAT 8 36 ,° j .0 a + a = b u = ny s = n€>y a+a=b u = £x v = £ €>x b=a+a a=wy s = w © y b=a+a t = wx t = w © x 2a+a=b+a u = ny v nwy s = ry © w 2a+a=b+a u = riy v nyz v = ry © z 2a+a=b+a u = 4x v £xy v = ( £ v x) © y 2a+a=b+a t = £x v Cx v xz s = U v x) © z TABLE 6.2.9. LOGICAL DESIGNS FOR FORMAT 9 37 6.3 Comments on the Logical Designs For format 1, for digit set b, , the value y* = n + y , and for b-,^ x* = -£ + x. Thus, n, x, and y represent digit set a , and -£ represents a ; and no hardware is required for converters a + a = b, or for generalized half adders b = a + a. The carry generator 2a + a = b + a becomes a full adder 2a+a=a+a+a. This reduction of the three structural types to onemakes possible a simplified theory of decomposticn of structures, to be described in section 8. For format 2, for digit set b^, y* = 2n + y and for digit set bp> x* = -2^ + x. The structure b = a + a is a half adder and b = a + a o 0,0 . is a half subtracter.. The carry generator 2a + a = b + a is also a half adder, with the additional OR gate needed for a full adder. Similarly 2a + a = b + a is a half-subtracter with the OR gate needed for borrow propagation. Format 3, except for b 3 = a + a , appears to be similar to the Boolean dual of format 2, and hence is equally simple. For this format, y* = 2n - y for b~, and x* = 2^-x for b Format 4, in effect, transfers the AND gate of the carry of the half adder from the generalized half adder to the carry generator. For this format, b. is the sign and magnitude representation of x*, with e, the sign and x the magnitude. This format simplifies negation to complementation of E,. Format 5 is of some theoretical interest, since the number of structural types is reduced to two, with no hardware required for the converter structures. This format transfers a gate of the EXCLUSIVE OR from the generalized half adder to the carry generator. Format 5, like format 1, 1 requires permutation of E and x for negation of b . Formats 6 and 7 are similar to format 5, except that the converter 38 requires either an AND or an OR gate. Formats 8 and 9 appear to be too complex to merit further consideration. A generalized theory of decomposition, applicable to all formats, is discussed in section 9. One result is that the number of generalized half-adders is less than the number of carry generators for many structures, and the number of converters is quite small. From this point of view, the formats with the simplest carry generators, such as 2 and 3, appear to be preferable. Format 4, with a slightly more complex carry generator, may be useful for some applications because of the ease of negation of b . Although the formats for b and b are discussed and listed together in the design tables, they are independent. Thus a design involving structures using b« and b., for example, may be quite reasonable for some applications. 39 6.4 Logical Design Combinations The process of designing a structure as a combination of simpler structures is a subject of great interest and practical importance. A common example is an adder formed by combining two half adders. (To be precise, 2a +a =a +a +a is a combination of b = a + a and 2a° + a° = b° + a°.) Example 6.4.1: Carry-propagating adder 2k _0,_2 s 0,1 The notation and interconnections for structure 2a +a =a+a +a as a combination of structures .0 0,0 , ,0 b =a +a and 2a +a =b +a are shown in Figure 6.4.1. Since there are nine formats for d*, h ° + ^ a = b - a d* c 0,1,2 b° = a + a * — 7F 0,1 0,1 0,1 Figure 6.4.1 . Full Adder 40 there are nine designs. If format #1 is chosen from Table 6.2.1, the equations are 5 = x,d = y for b = a + a and s = 6 Q d © c and k = Sd v dc v c6 for 2a + a = b + a and for this format, b° = a + a is vacuous and 2a + a = b + a is the adder. For format #2, the equations are 6 = xy and d = x©yforb =a +a and k = 6 v cd and s = c ©d for 2a + a = b + a . This design is two half adders, with the extra OR needed for an adder incorporated in 2a + a = b + a The other designs are also adders. If format #5, (which is the same as #7), is chosen, the design equations are 6 = xy d = x v y for b = a + a and k = 6 v cd s = c © 6d for 2a° + a = b° + a It may be verified that this is an adder by substituting for 6 and d k = xy v c(x v y) s = c© (xy)(x vy) =c©x©y It is interesting that the simplest realization for x©y for the vacuum tube technology of Illiac I was x©y = xy(x v y), represented here by 66. 41 Example 6.4.2: Carry-save adder 2a +b =b +a + a Sf ^ 0,1 ,2 b = a + a 4v 4^ 0,1 . o x .0 0,1 ,0.0,0 2a +b =b +a +a c. 0,1 0,1,2 m. a? i l For this example, structures u0 . „ 0.0 b = a + a and 2a + a = b + a 2c are used again, but in inverse i-1 0,2 order, as indicated in Figure 6.4.2. In the past, the design was considered complete with the separate designs of b = a + a and 2a + a = b + a Figure 6.4.2 Carry save adder It is possible, however, to consider the design of 2a +b =b +a +a as a unit. For design #1 of Table 6.2.1, it is found that structure b = a + a is vacuous and 0.0 . . . D . . . .0 . 2a + a = b + a is an adder. By designing 2a +b = b +a +a as an independent entity, many variations (255, not allowing for obvious symmetries) are found, as indicated in Figure 6.4.3. The output carry c. , remains unchanged, but the complexity of formation of a. and s. may be shifted in many gradations from to o. =c. s. = a i ea 1 @m 1 a. = a. © a . © m. s. = c. One of the many intermediate solutions is shown in Figure 6.4.3, namely: o. = a i c i v a.jU.j ©nu) s i = *i c i v a i( a i ^ m i) The remaining intermediate solutions have not been investigated. 42 Design 2a° + b°= bjO + a + a 1111 ViVi r 2 110 1 1 1 1 1 1 2 1 2 2 3 1 'i-l a i 2 c i-i 01/10 01/10 100/011 01/10 100/011 100/011 1 01/10 01/10 100/011 100/011 1 01/10 100/011 01/10 01/10 1 1 k 3 o k 5 i k 6 k 12 l 1 1 k g 1 10 o k 1 R 3 k 2 k 4 ^5 k 7 ^6 k l2 k 13 l k ]4 k 8 R 9 k ll R 10 R 1 R 3 R 2 £ R R R K 4 K 5 K 7 K 6 \c \c 1 R K 12 13 ' 14 E E £ k K 8 9 K 11 K 10 i-l a i c. t not a fn of c. implies i-l i k 3 = o k 5 = o ko = k in = 1 k 6 = 1 k 12 = l 10 c i 11 1111 11 m. k l 1 k 2 k 4 k 7 \i i 1 k 11 k 8 1 k ll *1 1 K 2 " k 4 " k 7 k 13 1 k 14 E 8 1 Si i-l = Vi v a i m T V a i m i Let k odd C i-Yl s = 1 k even = £il adder TT~r °i a i m i c. l a. = Ci Si = a.c^m. v a.a.m. v a.a.m. v i.a^m. = a . © a . © m i Diagonal elements = 1 others ^ = a iCi v a.a.m. v S.a.m. = a^. v l.{^ s. = a.c i v a i (a i <&m.) a. ®m.) Figure 6.4.3 Carry save adder design 2a + b, = bi + a + a 43 Some of the complexities of logical design are illustrated in Figure 6.4.3. The first is the existence of "coupled don't-cares". In this example, these are of two kinds. The output value is 2c.-, + a. + s. If this value is one, then c. -. = 0, and either a. = 1, s. = 0, or a. = 0, s. = 1. If 2c_-| + a. + s. = 2, then the two choices are c. -, = 1 , c. = s • = 0, or c . •, = 0, c. = s . = 1 . The designer then has freedom of choice of a., say, if he chooses the corresponding values of the other outputs. Coupled don't cares have the infuriating property that simplification of one output tends to complicate the other (or others) . A second feature which simplifies the design is a consequence of the carry-save property of the structure; namely the output carry c. -, cannot be a function of c.. Consider minterms a.a.m.c. and a.a.m.c.. For the former c_, =0; for the latter, the coupled don't care is resolved by the necessity of choosing c. -, =0, hence a. = s. = 1 for minterm 3. In this particular example; all don't cares coupling all three outputs are resolved by this requirement of functional independence for Cj -I . So far, logical designs for structure 2a° + b? = b? + a + a have been partially investigated. Some details for structure2a + b? = b + a + a" are given () .0 , i + bp = b„ + a + in Figure 6.4.4. A third type of design complexity is apparent here. The state a. = a. = 1 is a don't care for the input at; for consistency in the representation of s*, the condition a. = s. = 1 must be prevented. 44 Design of 2a° + b° - b° + a ♦ a ( f - 2a, ♦ i, a. a, - jesi gn ot ca t u 2 - u 2 2 111 2 2 1 a i a i m i c i c i-l i 5. 1 roooo ) 00 ° ] i 1 I 1 l 1 M) 1 1 2 01/10 ro i o o 1 1 i / 10 1 2 01/10 ] O 1 1 2 01/10 Lo iii 3 01/10 1 ri ooo 2 01/10 2 < 10 1 10 10 3 3 01/10 01/10 1 1 Li o i i 4 1 1 f\ 1 - X X X J 1 1 1 - X X X J 1 1 1 - X X X Li l i l - x x X c . ^A 1 1 ( 1 1 1 X X X X \ aA \ 1 1 1 I '1-1 c. , not a fn of c.. implies: a i m. S i : a. ©m i © Cj k 3 = 0, k 5 = 0, k 7 = k 6 , k 8 = k g , k Q = 1 = 1 =1 a.s. = implies: V.-, = 1 k 9 = k 10 = ] 10 10 o o k 6 k 5 1 k 6 R 6 X X X X X X X X X X X X k 8 k 8 i i R 8 R 8 1 o 11 k 6 = ] k 8 = ] c i-l = a i V a i m i 1 = c i^ a i® m i ) Previously known solution: b. , a a^ v a^m.. d.. - a.. © m.. a. = b.d. 1 1 1 s i = b i® d i ; i-T$* Figure 6.4.4 Structure 2a 4 b« = b 2 + a + a HA HA 7FT c i "T T a. m. 45 This condition resolves the coupled don't-cares for minterms 7, 9, and 10 for which s. = 1; the requirement for functional independence of c. -. resolves the remaining coupled don't-cares. A solution is then obtained by conventional logical design techniques which is a rearrangement of the solution known for many years. 46 7. Information Theory and Arithmetic Information theory is applied here in a limited and specialized way. The application is limited to structures for addition and subtraction, and it is assumed that each two-valued binary digit which is an input to the structure conveys one bit of information, i.e., each input binary digit value is equally likely and each digit is independent of the others. Although this assumption is frequently unrealistic, it is nontheless extremely useful in determining the internal characteristics of a complex structure. As an example of the particular way information theory is employed here, consider a three by two multiplier array. If the eight values of the multiplier and the four values of the multiplicand are each equally likely, the input information content is five bits. The information content of the product is obtained from Table 7.1. Since the product value occurs 11 times, the value 6 occurs three times, the values 2,3,4, and 12 each twice, and 1,5,7,8,9,10,14,15,18, and 21 each once, the information content of the product is 47 mul ti- multi- array output product pl ier pl icand 4 2 1 2 1 8 4 4 2 2 1 16 8 4 2 1 11 1 1 1 1 2 2 1 1 3 2 1 4 2 1 1 1 5 1 1 1 1 6 3 1 1 1 1 1 1 7 1 1 8 1 1 1 1 9 1 1 1 1 10 1 1 1 1 1 1 1 12 2 1 1 14 1 1 1 1 1 1 15 1 1 1 1 1 1 18 1 1 1 1 1 1 1 1 1 21 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Table 7, .1 Mul tit )lication Table for a 3 x 2 binary array multiplier 48 -I Pi log 2 p . 11 , 11 3 32 log. ^ + 2 32 ' 32 log 2 32 + 4 ^32 log 2 32^ + 10 (32-109,, 3I) i no Z 11 3 8 10x = log 2 32 (— + — + — + —) (32" log 2 11 + -^ log 2 3 + 32 lo 9 2 2 = 3^- [5 (32) - (11 • 3.45942) + 3 • 1.58496 + 8)] " 32 [160 - (38.05362 + 4.75488 + 8)] 109.19 32 = 3.412 bits The array consists in part of eight lxl digit multipliers, each of which is an AND gate. These outputs are also listed in Table 7.1. The information content at the output of the AND gate array can be calculated by noting that 000000 occurs 11 times and the remaining 21 symbols occur only once each. Therefore -EP i log2P i = -[^log 2 ll + 21 (^ log 2 3})] = 5 - (li log 2 ID = 5 - 11 (3.45942) = 5 - 1.189 = 3.811 bits Thus the AND gate array reduces the information content from 5 bits to 3.811, and the addition hardware reduces the information content further to 3.412 bits. Here, the concern is solely with the hardware for addition, which has an input of six bits from the AND gate array and an output of five bits. The assumption is made that the two values and 1 are equally likely at each AND gate output, which is false in this case since the probability of zero is 3/4 and of one is 1/4, and hence has an information content of 0.811 bit. The assumption is also made that all six digit symbols are equally likely, which is also false, since the symbol 000000 occurs 11 times and ten symbols do nnt nrrnr at all 49 The essence of the process is that the structure to be designed will be capable of accepting all 64 input symbols and generating the correct sum, independent of the specific nature of the problem, and no attempt is made to take advantage of the fact that some symbols do not occur. The emphasis is on the addition process alone, without reference to the context in which it is used. Another assumption made here is that a three-valued digit set requires two bits. This is a reasonable assumption from the practical point of view of logical design, and is especially obvious for format 1. However, Table 7.2 indicates that for the output b , the probability a a b of and 2 are 1/4 each, 1 1 1 1 and the probability of 112 1 is 1/2, hence the Table 7.2. Half-adder information content of b is 1.5 bits. Although some preliminary studies were made under the assumption that digit set b conveys 1.5 bits, the decomposition procedures of section 9 are simplest under the assumption that digit set b conveys 2 bits. 50 8. A Simplified Theory of Decomposition for Format 1. 8.1 Introduction It has been noted in section 6 that for format 1, the three fundamental structural types are reduced to one; namely, the carry generator 2a + a = b + a, which is for this format equivalent to the full adder . 2a+a=a+a+a. In section 7, it has been observed that addition and subtraction result in a loss of information. In this section, the following theorem is presented: Theorem 8. The information loss in a structure for addition or subtraction is a measure of the cost of the structure. A corollary is that the object of good design is to lose information as quickly as possible. It is also useful to prepare a chart showing the flow of information loss, which then serves as a guide to the layout of the structure. It has been observed that the fundamental structural types preserve diminished cardinality and offset. For a complex structure to be realizable and decomposable, and for Theorem 8 to be applicable, the complex structure must also preserve diminished cardinality and offset. Algebraicly 6 . = 6 . r J 3 J out in and w „ . = w . , where 6 designates the diminished cardinality and go the out in 3 J offset. Three cases may occur: 1)6 < 6 . . The structure cannot be realized, since not all combinations ' out in of input digital values can be represented by the output digit sets. 2) 6 = 6 . . The structure can be realized and can be decomposed. out in 3) 6 . 6 . . The structure is realizable and can be made decomposable by the addition of mythical inputs, so that 6 . = 6 . + 6 vth - The mythical inputs can later be used to simplify the decomposed structure. These concepts are illustrated by the examples which follow. 51 8.2 Parallel counters The function of a parallel counter is to count the number of non-zero bits in a register as quickly as possible. Consider first the simple case of a 3 bit register. Example 8.2.1 3 bit Parallel Counter The input is a + a + a with 6 = 3, a> =0, and X =2. The out out out information loss is A . - A =1 bit and the cost is one adder in out 2a +a =a +a + a . The process may be summarized by a chart, called an information loss chart, which lists the number of bits of each weight, as shown in Table 8.2.1. In this simple case, the headings in the first row A 2 1 3 3 include the weights. The second row 2 1 1 indicates the distribution of Table 8.2.1 Information loss chart for one full adder information bits by weight at the input, and the third row gives a similar indication at the output. The purpose of this trivial example is to emphasize that the effect of the use of one k k + 1 full adder is to transform 3 bits of weight 2 into one bit of weight 2 k and 1 bit of weight 2 , with a loss of 1 bit of information. Example 8.2.2 15 bit Parallel Counter The input is a + a + ••• + a (15 inputs), with 6 . = 15 and go . =0. in in The information content of the input is A • = 15. The output desired is 8a + 4a + 2a + a , with 6 . = 15, oj . = 0, and A . = 4. The information loss chart is shown in table 8.2.2. A 8 4 2 1 The chart corresponds 15 15 10 5 5 to the decomposed 8 14 3 6 2 3 1 structure of Figure 8.2.2 5 3 1 1 4 1111 Table 8.2.2 Information loss chart for 15-bit Parallel counter I ! a c 4° a , i I I L -^ i°! y a a c U° 4-^ L. u I a "^ \> y_ >/ Zd c fw I V f ; fa ! __4jd£| £* >/ d i i 1 ; i ; i . I I I ! ■ i_J i-KiuRf $.2, Z. i pECanrcfeti StKoctvkF' go k A • ■ ■ ■ : : ; j_ I i ' ■ i i i , I ; I j ! i T ; I 1 1 ' l| j j ; -i ' i j ! i _i I j I J , ' ;" |"~T~ I™ I ' i ! _ j- I i ; ■ ! rj rr □ L { L i 1 L L __L I ; ! 53 The correspondence between Table 8.2.2 and Figure 8.2.2 is reasonably obvious. The transformations of fifteen a 's into five a 's of weight two and five a 's of weight one is achieved by replicating 2a +a ■ a +a +a five times, with an information decrease from 15 to 10 bits. Each row of table 8.2.2 indicates the distribution by weight of digit sets between levels on Figure 8.2.2, with the decrease in information content between rows of the table corresponding to the number of adders on the corresponding level of Figure 8.2.2. The total cost of the structure is 11 adders, which is the information loss from input to output. Example 8.2.3 10 bit Parallel Counter The input is a + a + ••• + a (10 inputs), with 5 . =10 and uj . =0. K in in The information content of the input is A . =10. The output necessary is 8a + 4a + 2a + a , with 6 . = 15, w . = 0, and X = 4. Since out out out 6 . > 6 . , it is necessary to provide mythical inputs 6 .. = 5, so that 15 = 6 ni . = 8 , + 6 „, w+ l,. The designer has considerable freedom in providing out in myth s r 3 mythical inputs; but limited experience indicates it is usually best to minimize A mvth' so 6 mvth = ^ a + a ls cnosen - The information loss chart is shown in input Table 8.2.2. The cost mythical input decomposable input is 8 adders, of which 2 have mythical inputs. For these, one input is output always zero, hence each of Table 8.2.2 Information loss chart for a 10 bit Parallel Counter the two adders is reduced to a hal f adder. A 8 4 2 1 10 10 2 1 1 12 1 11 9 1 3 5 7 2 2 3 6 2 3 1 5 3 1 1 4 1 1 1 1 54 8.3 Array multipl iers As noted in section 7, the decomposition procedures are applied to convert the outputs of an AND gate array to the conventional binary representation of the product. A 5 x 5 array is chosen to illustrate the procedure. Example 8.3 A 5 x 5 array multiplier. For a 5 x 5 array multiplier, the maximum product is (2 - 1) = 961, hence <5 in = 961 , to in = 0. The output is the 10 bit product 512a° + 256a° + ••• + 4a° + 2a° + a°. Therefore 6 mi+ = 1023, co . = 0, and 6 .. = 1023 - 961 = 62 out ' out myth The information loss chart is given in Table 8.3. The 25 inputs from the AND gate array are distributed by weight as shown in the input row of the table, and the mythical input is 32a + 16a + 8a + 4a + 2a , as the mythical input row indicates, with X .. = 5, Seven adders are used for the input row of the structure, one each at weights 2,4,8,32, and 64, 512 256 128 64 32 16 8 4 2 1 25 1 2 3 4 5 4 3 2 1 Input 5 1 1 1 1 1 Mythical input 30 1 2 3 5 6 5 4 3 1 Decomposable input 23 1 3 2 5 3 4 3 1 18 2 1 3 4 2 3 1 15 2 2 2 2 3 1 14 2 2 2 3 1 13 2 2 3 1 1 12 2 3 1 1 1 11 3 1 1 1 1 10 1 1 1 1 1 1 Table 8.3 Information loss chart for a 5 x 5 array multipl ier for which the number of inputs ranges from 3 to 5, and two adders at weight 16, for which the number of inputs is 6. The information content decreases rapidly from 30 to 15, with 15 adders employed in the first three levels. At X = 15, the pattern 022223 emerges, which can be recognized as the 55 beginning of a carry propagation. Note that X then decreases by one unit for each level, as the carry propagates through a single adder at a time to the digital position of next higher significance. The cost of the decomposed structure is 20 adders, of which 5 are half-adders. The results of the analysis of the 5x5 array multiplier generalize o o o easily. For an n x n array, 6 = (2 - 1) , x . = n 6 _ 11+ =2 - 1, J in • in out A ou t = 2n, so & myth = 2(2 n - 1) and A th = n. The cost in n(n -1) adders, of which n are half-adders. The number of levels is 2(n - 1). The precise distribution and numbers of adders at the input and nearby levels does not generalize easily, but there does not appear to be any problem in determining one more final product digit per step, as the triangular growth of l's to the left indicates in Table 8.3. 56 9. A General Theory of Decomposition for all Formats 9.1 Introduction One may expect the general theory of decomposition to be more complex than the simple theory for format 1, since three fundamental structural types are needed rather than the one type for format 1 . The general strategy is similar, however; an accounting of the number of digit sets of type b and of type a is employed, as well as an accounting of the information content. It is convenient to begin by analyzing the effect of using each of the three fundamental structural types, as summarized in Table 9.1.1. In the table, x is a measure of the information content, as in section 8, a is a count of type a digit sets, and 3 is a count of the type b digit sets. AX = X in - X nilt > Aa = a - a . and A3 = B - 3 in out in out: in out a+a=b No. X x in 2 X out 2 a in a out 2 e in 1 3 out AX Aa -2 A3 1 b=a+a y 2 2 2 1 2 -1 2a+a=b+a z 3 2 1 2 1 1 -1 1 TABLE 9.1.1 Analysis of the Fundamental Structural Types For example, the carry generator 2a+a = b+a transforms an input of one b and one a, with X. = 3, into an output of two a's, with x . = 2. Thus AX=1 ; similarly Aa = a- - a . = -1, and A3 = 1 . Note that, always, x = a + 23, hence one of the parameters is unnecessary. In a complex structure consisting of x converters (a+a = b), y generalized half-adders (b= a+a), and z carry generators (2a+a = b+a), the ax for the structure is z; similarly, Aa = 2(y-x) -z, and A3 = z -(y-x). Given the specifications of a complex structure, which is decomposable in the sense of section 8, the ax, A3, and Aa of the complex structure are known, and the values of x, y, and z are unknown. The equations for the 57 complex structure may be solved, as follows: z = aa 9.1.1 y-x = Ay - A3 9.1.2 y-x = 1/2 (AA + Aa) 9.1 .3 The equations 9.1.2 and 9.1.3 reduce to AA = Aa + 2ab; only one of the two is necessary. It should also be noted that only the difference y-z can be determined. This should not be surprising, since the converter and generalized half-adder are inverse structures; the use of one cancels the effect of the other. The expression z = aa has the interpretation that the information loss of a structure measures the flow of carries across digital position boundaries. The interpretation of the expressions for y-z can be more easily explained after consideration is given to the examples which follow. 2 k+l 2k 2 k+1 2 k 2 k+1 2 k bab a baba baba input 0011 0002 0010 output 0101 0010 0002 a)carry b)general ized c)converter generator half-adder Table 9.1.2 Information Loss Charts for the Three Structural Types The information loss chart of section 8, for use with format 1, must be replaced by more complex charts, such as those shown in Table 9.1.2, which provide a means of accounting for the parameters e and a of the structure. 58 9.2 Redesign of the conventional Array Multiplier of Section 8. For the array multiplier of section 8, all inputs and all outputs are type a digit sets, therefore, A3 = and Aa = AX. From equations 9.1.1 and 9.1.2, z = y - x. There is no need for converters a + a = b, hence x = and z = y. The only need for generalized half-adders (b = a + a) is to provide the b input to the carry generator 2a + a = b + a. The pair b = a + a and 2a + a = b + a used in this way is equivalent to a full adder; hence the net effect of the redesign for all formats is to decompose each full adder into a carry generator and a generalized half-adder. 9.3 Redundant Array Multipliers It is assumed, for a redundant 4x4 array multiplier, that both multiplier and multiplicand are of the form 8b 1 + 4b 1 + 2b 1 + b 1 , where b 1 is the digit set {T, 0, 1}. The product is also redundant and is z 2 n b , with a diminished cardinality 6 = 510 and an offset i=l out u . = 255. The elementary multiplier array consists of sixteen structures each performing the operation b = b x b . Since the product ranges from -225 to +225, 6. = 450 and a). = 225. Therefore 6., = 510 - 450 = 60 in in myth and u> . = 30, so the mythical input is 16b + 8b + 4b + 2b . The parameters that determine the complexity of the structure area t = 0, e out = 8 ' x out = 16 ' a in = °' 6 in = 16 ' A in = 32 and "myth = °- 6 myth = 4 ' and x .. = 8. Temporarily ignoring the simplifications due to mythical inputs, the structure requires z = A. + A .. - A . = 32 + 8 - 16 = 24 carry generators, and the cost parameter y-x is z - A3 where A3 = 3- + 3 myth W = 12, so y - x = 12. 59 Since the carry generator 2a + a = b + a requires an a input, the first operation necessarily requires use of a converter a + a = b. The tables 9.3.1, 9.3.2, and 9.3.3 illustrate the effect on the array structure of using 1, 2, and 4 converters, respectively. The entries in the table show the effect of the use of the fundamental structural types, as shown in table 9.1.2. Two lines are used per step in tables 9.3.1 to 9.3.3 when two structural types can be used in parallel. For example, consider the relevant portion of steps 2 and 3 of Table 9.3.1. For digital position 4, 8 4 2 Step b a b a b a No 2a + a = b + a can 5 5 4 4 2 1 ^ 2 be applied twice. 5 5 2 1 ? 2 j 2 1 3a Specifically, the entries 5 5 2^2 2 2^ I 1 3b for step 2, digital position 4 represent (4b 1 + 4b 1 ) + 4b + 4b + 4a + 4a° 6( ) 12 9 (o 4 3 Z 1 (o i < >_ 4 «h — — X $ o( b a. b a 6 a. b a b 6. b a b a b a. t — ! Ihf * 32 t(> /' Z z 3 3 4 4 3 3 2 2 /' J i Myth . 1 h ^ a; ► J 4 /' /' /' /' — P. /ft/ ?t<.j . ftf 20 2* 4 f ^ 4 f 3* /' 1 fib A- 40 n z e 4* 5* t* ** 2'' 1 i :a +■ ,. 6^ -a 3? a 4- z z 4* S s t 4 2' 2' z ! 6 fa 34 1ST 6 z x 4* S s 2' 2 2 2' 2' 3c. b~~ sm! a 3(, It 4 z z 4* A 2' 2 1 2' l' 3 _t I- 5k - t> fa 32 12 ? 2 Z 4-+ 2' 3 3 4 2 Z 1 (' 1 4- ! ! i i i *> + CL 27 7 /3 2* Z l z z 5 3 4-' 2* 1' H ' 1 a It-ai 27 ? /I Z z 2' Z z ^ J f' 1' /' i i frf i ! M + 4-jtH ■a. 23 4 /5 2' 4 2 5 3 4-' r r 1 ■ ! 6 6- y r !a 4 a 23 6 II 2' 4 2 /' 3 2 /° 2' r i' i 7a M + a =1 b- ha 20 3 14 I 1 2° 5" 3 4' 2' r i' b = a. i\ a. 20 5" /0 l' 2* l' 3 2 1° *' 2' i« /' 1 It b " "i «-a Iff 3 12 i' 3' 4-' 2' 2.' i' /' 8 bj = a + M i — n. 'til* *?. 3. / /c e t iu K ( J< H < ^r ITA / /* k /f '> /# e c l oi ' a X M ! I ! r — 1 i i — — Oe a- 6 L f2 .8 6 4 3 ^ 1 6 i < f. < } . < 'J.ef lie. X A o( b ft b a b ft b ft b « 6 ^ b ft b r ft X. - t 40 2d /' Z z 4 4 G k f* 3 5 l' 40 3b /* 4 !' Z z 4- 4 " S 2' 4 + z l l' 1 la Za /4 ■tf /' z l 4 + 2' Z z 2' 4^ Z' 2' z I - t = b-l ■ft — 30 ? /4 /' 2 2 2' 2 2 4> 4 2 2 2 2' 2' 3k b- c b\z 30 1 IZ /' 2 2 2' 2 2 4 Z 4 2 2 J 2' l' $*i •a Z4 3 IS /' 2' 4 Z 4 2 b 3 2' /' -fi a. 2f b IZ /' 2' 4* r 2' Z l 2' 2' (' f r t Za + c b- -ft zo a /fe /« 2° fT 3 4' 2' 2' /' 5"ft ' - <■ a - b~ fa zo 5 /o l» Z° 2 l /' 4' 2' /' /' 5^ Zai + c 1 i*< ii 4 7 // 5" /' 3 1 1° l' 4' 2' r I 1 6 ^c a 1' 1° /' f° I 1 /° JL' l' i' /' fa b Zc i + b + c it. 4 ff 2' 2' 2' Z' r i" 1' 7 i Ic - at * ff l« 1' 1' i' i' i' r y 1 1 _4 ^ I I 1 i.] I 4 / 7 // e»- U) ;t A X- r Z _ — . I r- /; :* 6 4 3 Z i 1 ' i _ > J ► 5 ^ ( ' A £ <*.' fc 0. b ft b ft b a. b ft b ft y a. b ft Yoj 4-i /* fu f- 4o 20 /' 2 2 4 f !T S 4 4 3 3 ■i Z.<*\ + c i - 6 4o /6 * /' 2 L 3 3 z l f + 2' 3 3 2' z 7 - z' 1 -1 ol >1 ol ol 1 ,1 Step No. Table 9.4 Format 1 design of a Redundant Array Multiplier, 64 The information loss chart indicates a cost of 24 full adders and a time requirement of 4 steps. However, in terms of the parameters of section 9.3 each full adder is a combination of one carry generator and one half adder, hence the cost is 24 carry generators and 24 half adders. The time for use of a full adder, shown as 1 step in Table 9.4, requires the sequential use of a half adder and a carry generator, and thus represents 2 steps for the tables of section 9.3. Thus 8 steps are needed for table 9.4, to be compared with 7 steps each in tables 9.3.2 and 9.3.3, and 10 steps in table 9.3.1. 9.5 The Design of Signed-Digit Adders 9.5.1 Introduction Signed-digit adders differ from previous designs in a number of important respects. First, the initial specification is incomplete, in that only a symmetric output digit set with diminished cardinality 6. and offset u>j = 1/2 6,, and two input digit sets, identical to the output, are specified. A transfer, with parameters 6. and co. is needed, so that r6 t + 6 d = 6 t + 26 d + 6 myth 9 ' 5J ro, t + u, d = a) t + u> d + %yth 9.5.2 where 6. and u). are chosen to minimize 6^ .. and a> +.U- t t myth myth Once the parameters of the structure are known, the designer must be aware of the carry-save property of the structure; the output digit must be a function of as few input digits as possible. Alternatively, the functional dependance of the output transfer must be controlled; the structure consists of either two or three levels, and each level must be designed separately. For the first time, the decomposition procedures will be applied to higher radix structures; in particular to radix 4 and radix 16, as well as binary. This involves making assumptions about the representation of higher radix digit sets which may or may not be justified. 65 Addition structures may be classified by the diminished cardinality 6 d of the operand and sum digit sets. If 6 . = r - 1 , there is no redundancy, and the carry save property is impossible. Equation 9.5.1 may be rewritten as rs t + 6 d ^6 t + 26 d (r-l)6 t >_ 6 d 9.5.3 If 6. = r-1 , 6. = 1 . The resulting structure is a carry propagating adder, characterized by r&. + 6 . = 26. + 6. with 6. = 1, 6 . = r-1 . t d d t t d If 6 d = r, the digit set is redundant, and the carry-save property can be achieved. Note first that with 6. = r, equation 9.5.3 requires 6. = 2. The output level sums two digit sets in accordance with 6. = 6 + 6. , where 6 must meet the general requirement 6 >r - 1. Since 6. = r, the only solution is 5 = r - 1 , s. = 1 . Thus the transfer, with 6. = 2, must be broken into two digit sets, and a three level structure is needed. It is relatively straight forward to determine the details of each level as follows: output level r, the carry-save property can be achieved with a two level structure. To be specific, let r + 1 < 6, <_2 (r-1) and let 6 . = r + y, with 1 <. y £ r " 2. The characteristics of the structure are then output level 6 d = 6 s + 6 t 6 d = r + y 6 t = 2 6 s = r + Y " 2 input level r« t + « s = 2« d + « myth « myth = (r-2) -y 66 The general characteristics of signed-digi t structures are presented in Table 9.5.1. In the table, the values of A, $, and a for the operand and sum digit are taken from table 2.1. The mythical inputs are assumed to be in the simplest binary form; for example, if 6 .. = 6, the input is assumed to be 4a + 2a, with A .. =2. In a detailed design, offset considerations may require that the mythical input be 2b + b , for example. For <5 . = r, with 5. = 2, it is assumed that the transfer t = a + a, since a 3-level structure is necessary; otherwise, for <5 . > r and 5. - 2, it is assumed that t = b. ■ 4 X I iSvi < 5 ■M Up I — 6 1 — M (Sl o <\1 rJ 4 (V) (V) 4 ro va lo ^ lo lo 4 4 NO - - _ O O o ^ o — o — ^ — vD T! . N ro M 4 ro In ^ 4 to 4 «s* IV) >4J - N M!^- 4 4 4 ro vQ va sD >a xs ^? NO sD k y o o o - - O - O >Ni M - ^ N 0 tr> o O N r*) U, ^ lo U N o 1 { O • — : O 1 -n i O -In ro o o - (M »v> r\i ro fv> 4 o O 1 1 ■<0 o o °: o - - o - o cvl (Ni — r4 - — o <\! : ! — ( Oo i IVj ^0 , va; *° to h- Q O 4) h- I s - oo -0 1 o j ! =t . o <\i — 0| M •o >o lo «si- r^ ^f - o >Q VJ ; i l ■J _ I . ro ^> y^ -- o rs( 4 r*- to op o rvl rvl ^3 sy O ro V i ^ rJ rO 4 c- Vn 4 rsl ^0 rs) 5? ^7 |ol 4 „ + v*a Co O© a >o «sS 4 1 1 - rvi \3' ! H — (Vf <\1 «M »*0 - c4 N rJ rvl rsi fvi fvi ro to" 1 1 rJ ro (S j . ro "4 ^ vS r^ N <5o Cr- o — cvi rO 4 W> *+j r^j r\J — ^h 1 4 CO N 4 4 4 o© oo oc Oo oo OO - I ^- '■T-\- .1 I _. xi ! o rtsi o© h- N-| I s -: v<) r- i v9 vO va ^a l/j r- i L_ __j J _._j__ ^. oo oo! v*, Ooj Qoi "° O |_ sS o^ 63 sS >s! ^ ■o vO vQ ■ i ■- -, — t r iTT ! 1" ~\ i p C*> Oo to ^n 4~ r i *o ! I —f- r — r h~l i nj , — I f\,| ; — ; -». o <*"> "T — "I " "1 ; K to X 4 3 CO. 0- <*> O <+! O -^- ^ m IvO l^V r*~) . i i o, *- ^ : N| <*i M ! ^ ! ° ' ^f ! ; I I r i oo^ : o,^> O' o' o'o!°iQ!oi^l ol o! o|o r '•o X- c^ : ■ ' , [ i I — i — I" — ~T~ ~] Q -^ (M f") (Nl ; ro ■ ro | ^. Mro ro j ^*- CO j <^- 1 ^-! *0 ^> ^ £ -< ■o O f° |V> N r>o N N — ro r\l t\J — oJ ^ i^ ' I*-! &© ■ f*- oo vs c-; r- 1 o© : ©^ . o^i w~ 2 ^ UQ l/t> *2 lA> O i [^ ^ ~ ^ & *~ *■*> ^- j ^S Cv •**- m <>• — j O j J i . i i I ! I i — 4~ O ©*> O i r«J "*- j' «X5! P l^i ^-i SI 1 '\)i Q ^| ' tr, '-O fv^r^N^^l-^- -^-^. >4- to. '■o! '^ t/v tr>| >£ ; >S ! v9- i I r^ ^- <4- -1 , - - — j 1 -. i a- .O 7~" /^i r-o "^ i^ S> I s - '-spy y* O 5T C^: U to ^ toi U ^>: ^! C^ ( to! >© t- -• - t -»| rg^ ^r- «o ^s P-- -I — ro> fv> (v« : r^ (V^.rv-> IV)i (») , fw M f>Ojf>0 ^ | (>0 I fO ' 4- [ _ j j i i i ! I ! I — Nrvl rJN N (s|fs/r\j!(\j|cvf;cv/!rvJir\/!r\j|(\J;r>o i • r -'■ v ■• ! : -+- ■; - - ; -i — ^ ; r~ 00 o4 O 00 c— rs) ^' --o' ^1 ^' "^ ^ ^ ^j ^i ^ I I III: J ; 1 ._ 1 I 4 xn fs^i ! tu v5 o >s 0-' UJ -J 69 The column headed x reflects the fact that whenever 6, is even, the input level has two b inputs of weight 1, hence a converter a + a = b is necessary. The cost estimates implied by columns x, y, and z do not take into account the cost reductions due to mythical inputs. Table 9.5.1 is intended to provide a rough overview of the general characteristics of signed digit structures. Detailed designs may differ in a number of respects from the results indicated in the table. Example 9.5.1 Radix 2 signed digit adder. The design objectives are to form the sum of two numbers, for which each digit of the sum and of the two operands is from the digit set b , {1, 1}. Each sum digit is to be a function of a minimum number of operand digits, i.e., a carry-save structure is desired. Consider first the diminished cardinality 6., for the operand and sum digit sets. For one digital position, the input 26 , is 4 for the two operands and 6 = 2 for the output, hence a transfer of diminished cardinality 6. is necessary. The diminished cardinality expression becomes 26. + 2 > 6. + 4, or 6. > 2. The choice 6. = 2 is made. The carry-save requirement translates into a level -by-level design procedure, beginning with the input level. The 6 expression is 26 c + 6 = 4, so 6 = 1 for the carry and 6 =2 for the input to the second level. The input level structure is therefore 2a + b = b + b. For the intermediate level, the input is c + s, and the output is cardinality 26. + 6 = 3, or 5, = 6 =1. Therefore the intermediate J b a b a level is 2a + a = b + a. 70 The inputs to the output level are a + a, the desired output is b, so the structure is b = a + a. The input level structure is not one of the fundamental structures, so it is necessary either to design it directly or to break it into less complex structures. This leads to b+a+a=b+b, using a + a = b 2a+a+a=b+a+ausing2a+a=b+a 2a+b=2a+a+a, using b = a + a The final steps of the design involve introducing the offset, and parallel those of the normalized digit set designs. For the overall structure, 2u t + 1 = o> t + 2, so the collective offset of the two carries is 1. The input level structure is either 2a 1 + b° = b 1 + b 1 , or 2a° + b 2 = b 1 + b 1 . For the first choice, the intermediate and output levels are 2a + a = b° + a 1 , and b 1 = a 1 + a For the second choice, the structures are 2a 1 + a° = b 2 + a°andb 1 - a + a 1 . The input level can be decomposed, with offset, in the two cases, as b 1 + (a 1 + a ) = b 1 + (b 1 ) b 1 + (a + a 1 ) = b 1 + (b 1 ) „1 0* ,.1 K fo 1» 1 ,.1 N 1 (2a +a)+a =(b +a)+a (2a +a)+a = (b +a)+a 2a 1 + (b°) = 2a 1 + (a + a ) 2a° + (b 2 ) = 2a° + (a 1 + a 1 ) The two structures are shown in Figures 9.5.1a and 9.5.1b For Format 1, for which b =a + a , b =a + a , and b sa + a , the first, third, and fifth structures are empty, and the second and fourth structures are 2a 1 + a = (a + a 1 ) + a 1 and 2a° + a 1 = (a + a ) + a 1 for the first choice (Fig. 9.5.1a). Fig. 9.5.1b reduces to 2a + a = (a + a 1 ) + a and 2a 1 + a = (a 1 + a 1 ) + a . - -, a — 7 L ^ t f ) i; 1 — I k a i . s. /i 1 <> „ a u. ' w. I • ft ■rr M. CI I a 1 *- 1 l9 / \ Si Jf° * / V >» 6 5 r Id W. A .ft w b i J / V / / \ - 1 u. l rt CL t • ' j j a IF 1- / i t ) \ i < a. 1 i — t i k / \ 1 — - r 1 : i __ (* t) ih. ) _ (6 1 — ft UK t *j .5 ■ / 6< AlA Rf Si, f M rp '^ /c i r / ?P DC K i — 1 _i- j — _ _. i I — — — — - — — 1 72 Example 9.5.2 Signed digit adder with r = 4, 6 d = 4. With 6 . = 4 and w. = 1/2 6 . = 2, the digit set for the operands and sum is d = 2a + b and the transfer t is a + a , with 6. = 2, H = 1. Therefore, 6 Qut = 46 t + & 6 = 12, %ut = 6, 6 in = 5 t + 26 d = 10 and u). = 5. Thus & m *.u = 2, o> mV 4. h = 1» and the mythical input is b . The input level forms 4a 1 + f 1 = d 2 + d 2 + b 1 or 4a 1 + 2b° + b 1 = 2a 1 + 2a 1 + b° + b° + b 1 The intermediate level is 4a° + c 2 - f 1 ♦ a 1 or 4a° + 2a 1 + a = 2b° + b 1 ♦ a 1 and the output level is d 2 - a ♦ c 2 or 2a 1 + b° = 2a 1 ♦ a ♦ a The information loss charts for the three levels are shown in table 9.5.2. The results differ from those of table 9.5.1 in that the mythical input must be chosen to be b with x .. = 2, in order that a) .. = 1. This increases z to 5, but affects the operations in steps 1 and 2 by eliminating a + a = b in step 1, and replacing the carry generators of step 2 by the operations 2a°+a° = b° and 2a°+a 1 = b°. These are then format translators of the form b^ = b? and b!? = b?, where i is the format of the design. Example 9.5.3 Signed digit adder for r = 4, 6. = 6. The design is summarized in the information loss chart of table 9.5.3.1 The input level forms 4b 1 + d 2 = f 3 + f 3 or 4a 1 + 4a° + 2a 1 + b° = 2b 1 + 2b 1 + b + b and the output level is f 3 - d 2 + b 1 . 2b 1 + b 1 + a 1 + a . The transfer b is replaced by a + a to avoid unnecessary operations. 4 LEVEL X6a b a INPUT Input Myth. Input Decomposable Input 0-uJ J a +a = b 9 0. .. .0.0 2a +a = b +a 2a +a = b +a b = a +a Za'+a = b 2 + a° b 1 = aV b° - a° + a° 622 210 832 824 715 606 614 505 513 521 1 1 1 INTER- MEDIATE Input Za^a = bV 2aV = b^a 1 521 412 303 1 OUTPUT Input . 0^ b = a +a 303 311 Cost factors : x = 1 y = 4 z = 5 Mythical Table 9. 5 2 Information loss c r = 4, 6 d = 4. :hart for si gned digit ,2 n0 !° I 1 il I 1 r i ,0 Step No. 4a 4b 5 74 LEVEL INPUT Input Aa 1 - b 1 2a 1 + a° - t>V 2a' + a° = bV 2a V = b' + a° b° = a° + a° OUTPUT Input 2a° + a° = b° + a° b 1 = .V X$a 4 b a 2 b a 1 b a Step No. 840 2 2 2 2 832 2 2 I 1 2 1 1 723 2 2 I 1 2° 2 614 I 1 I 1 1° 2° 3 505 21 1° 2° 4 513 2l l 1 1° 5 513 l 1 1° 2 1 404 2l 2 1 6 420 I 1 I 1 7 Cost factors: x=l y = 3 z=4 Table 9.5.3.1 Information loss chart for signed-digit adder with r = 4, 5. = 6. 75 The design for r = 4, 6. = 6, could also be realized by replicating two copies of the binary design of Figure 9.5.1. The cost parameters would then be x = 2, y = 4, and z = 4, requiring five steps. The two examples are another illustration of a tradeoff between hardware and time. 3 The disadvantage of the design is that the digit set f requires 4 bits of storage, which is one bit more than necessary. One way of over- coming the disadvantage is to use digit set g = 4a +2a +a , in such a way that the value 4 never occurs. This can be accomplished by limiting the sum of the inputs to the upper level to 6=6, w=3, even though <5 d =7. In the example to follow the digit common to the two levels is c = 2a +a 2 1 and the transfer t is c = 2a +a . Thus for the lower level 4c 2 +c ] = g 4 +g 4 +a ] or 8a 1 +4a°+2a°+a 1 = 4a 1 +2a +a°+4a 1 +2a +a°+a 1 for which the input a is a mythical input, and AX = 3. For the upper level g 4 = cV+a 1 or Aa'^Aa = ZaW+a'+aV for which a is a mythical input, and AA = 2. 76 The design is summarized in information loss table 9.5.3.2 LEVEL X6a 8 b a 4 b a 2 b a 1 b a St N INPUT Input 707 2 2 2° 3 1 b = a+a 731 i 2 1° 1° l 1 1 2a V = bV 622 i 2 1° 1° l 1 2 2a°+a° - b° + b° 513 i 2 1° 1° l 1 3 2a 1 + a° - b 2 + a° 404 I 1 1° 1° l 1 4 OUTPUT Input 404 2 1 2 1 Myth Input 101 l 1 Decomp Input 505 2 1 3 2 b 1 = aV 521 ll I 1 I 1 5 2aV = bV 412 ll I 1 1° 6 2a 1 + a° = bV 303 I 1 1° 1° 7 Cost factors: x=0 y = z = 5 Mythical inputs a +a Table 9.5.3.2 Modified signed digit adder for radix 4. It is relatively easy to compare the output level design of Table 9.5.3.2 with a logical design. Let the input c = 2a +a be represented 2 10 4 by w and x, let c = 2a +a be represented by y and z, and let g = 4a + 2a + a be represented by s, t, and u. Details of the logical design are shown in Figure 9.5.3. Inspection of Table 9.5.3.2 indicates that the output level consists of two subtracters in cascade, whose logical equations are r = xz v m (x v z) = xz u = x€)z©m= x©z, with m the mythical input, s = wy v r (w v y) t = w©y © r 77 Substituting for r, s = wy v xz (w v y) t = (x v z) (w©y) v xz (w®y) = x(w©y) v zx (w © y) v xz (w$y). The two designs are therefore equivalent, but the structural details of Table 9.4.3.2 are not apparent in Figure 9.5.3. 71 5 L i I 1 4 2. 1 W X H 2 c x t = X Y^a 4) J. ^ 1 ! 1 I / 3 t / 1 / J* V > . (fce V Si d i / 1 I I / / i / *- .— — «* 1 1 I / I 1 • — 1 z 1 ' - \ 1 I — 1 1 / 7 / 1 1 / / 5 w X'< f* i 1 / 1 1 ( / 1 i/ X V d i - 1 / 1 L o ] a ( \Fj )tit 7. 5". 3. I • 0( 5/ c/» i. Pi rs tc , J 0/r ■ 7 Hi ( Ou 77= ^7 - L EV £L < >F 7 ^£ Z.£ ?. r, 3 t z 1 1 i i 1 i 1 I ._ i j i 79 9.5.4 Signed digit adder for radix 16, 6 d = 20. A useful digit set for redundant radix 16 arithmetic is the digit set with 6 d = 20 and u>. = 1/2 6. = 10. As in the previous example, it is desirable to minimize the storage requirements for the digit set. The digit set w = 8b + 4a + 2a + a , with the capability of 5 = 23, is employed, and the design is such that the values 11, 11, and 12 of the sum cannot occur. The signed digit adder has two levels. For the input level I 911 11 3 3 16b+r=w +w +d, where d is a mythical input. For the output level II 9.1 1 ^ 1 • 4-u- i • w = r + b + c , where c is a mythical input. For the detailed design: Operands and sum w 11 = 8b + 4a + 2a + a Transfer b = a + a Common digit r 9 = 8a° + 4a 1 + 2b 2 + b 1 Mythical input d 3 = 2a 1 + b 1 Mythical input c = 2a + a The design is presented in the information loss chart of table 9.5.4. 8 3 1 b { > iV 1 ' I -7T/ ' h j8 << s> OL b a. b a. b 7 3 / 1 I' /' I Otion f, /< W r /3 3 7 2 1 2° 3 3 /' z x h'U" a fc V, .' ! IZ z 8 z 2 - 2° e 2' i 1 hip T b \--k'* a' \z 3 6 2* 2° \ z l* 2' lb ! 1 ! 1 U7T b\-V a * «° IZ 4- 4 2 1 1° \ z 2 1 V Ic FVlL J. k'-u 7 ! y l +<3 i // 3 sr 2 L 1° I 1 Z 1 z' 2* b i -a< ' \\ 4- 3 2* 1° /' Z x /' Zk 1 » l 1 k f-A< - ( ,v *' 10 3 4* 2 1 !° /' Z z /' 3< 1 *> L ^ k'H ■ft' 10 4 2 Z 2 1° I' I 1 /' 3 b ^ •J'; fc"« | ;r y 2 4 1° /' t z /' z' i j_ i ! flV|VL In Pa- ■ a 2 1° /' T j . i_. _j Pf(\nf. U rol to 2 6 1° /' I 1 1° /' 3 Z 6" L)T P$T - j - VJ?L 1 Za + A _ 1 7 + t K % J 1° 2 Z z' 3* 6 1 1 "~ 1 L£ b - 6 + i X 8 3 2 i° I 2 - i' i° ,i 7 1 i 5 . i +a ,°+ a. 7 2 3 i° l z /' 1° . i ? Ztf+a. b'+. %° 6 / 4 i° I 1 1° r 1 1 ? i Za ( +a > r 6V 4° £~ 5* z' i° /' . i /o 4 h f. a 'i -a' 5* 1 3 /' 1° i 1 f ( // j .1 . i • i *'- r J,05J i c a\ '■Jo K$ «; /*/ eo\ ■ L t i/i T L , * X- V" f i z - s h 1tA l A. K' M no i' ^6 J5 c. V/4/ \r f 'ok. £* PI X IL ! 5 r<5 A i(Tl > - P» ;/7 ^ *pt IK *)C ^H h ~ zc ) 81 10. Theorems and Proofs 10.1 Introduction The purpose of this section is to gather in one place the theorems on which the theory of decomposition is based. In some cases, the proof is given in other sections. 10.2 Theorem 10.2 Theorem 10.2 states that a structure for addition and subtraction preserves diminished cardinality and offset. The proof follows directly from the basic properties of the operations of addition and subtraction and is given in Section 3.1 . 10.3 Theorem 10.3 Theorem 10.3 states that if the logical design is known for a structure, the logical design for the negative of that structure can easily be determined. If the arithmetic operation performed by a structure is w = x + y, the negative structure performs -w = -x - y. The proof requires consideration of two cases. If the digit sets of w, x, and y are all of type a , a , b , or b , the binary variables representing w, x, and y can be used to represent -w, -x, and -y, and the logical design expressions for the structure and its negative are identical. The second case occurs when the digit set b is used. The proof then depends on the fact that the processes of format determination and logical design are exhaustive, so that if a design for a particular format of b is given, the design for the format with l's and 1 's interchanged is also known. The details of the pro- cedure are given in section 6.2. 10.4 Theorem 10.4 Theorem 10.4: For a digit set of diminished cardinality 6 Q , there exists a unique representation of the digit set, such that each 82 binary weight of the representation has only a single digit set of either type a or type b. (These representations for the lower values of 6 Q are listed in Table 2.1 .) Proof: Let the digit set be represented initially by 6 digit sets of type a, each of weight 2 = 1. If 6 Q is odd, use of the operation b = a + a repetitively s, = 1/2 (6 Q - 1) times yields 6 x type b digit sets and 1 type a digit set. Use of the operation 2a + a = b + a sequentially 6 times yields 6 digit sets of type a of weight 2 and a single digit set of type a of weight 2 =1. If 6 is even, 6, = 1/2 (6~- 2), and a similar procedure yields 6-^ type a digit sets of weight 2 and two digits sets of type a of weight 2 . The latter may then be replaced by b = a + a. By induction on i, 6. type a digit sets of weight 2 1 can be replaced by either i i+1 an a or a b of weight 2 and 6. + , type a digit sets of weight 2 , where either 5^, = 1/2(6. - 1 ) or « i+ , = 1/2(6. - 2), for 6. odd or even. The process terminates when some 5. = 1 or 2. The representation is unique, and the proof indicates the pro- cedure for obtaining the representation if 6 is given. For example, if 6 Q = 23, 6 ] = 1/2 (23 - 1) = 11, 6 2 = 1/2(11-1) = 5, 63 = 1/2(5-1) = 2, so the digit set may be represented by 8b + 4a +2a + a. The procedures followed for the proof indicate that the information content of the unique representation is a minimum for all representations of equal cardinality. Since the carry generator is the only operation which reduces information content, the minimum information content is reached when the carry generator can no longer be used. This is precisely the procedure followed to achieve the unique representation. 83 10.5 Theorem 10.5. Fundamental Theorem of Decomposition Theorem 10.5: Any digit set of given diminished cardinality is decomposable to the unique digit set of the same diminished cardinality having the minimum information content. Proof: The proof is similar to that of the previous theorem. Given a m . m diminished cardinality z 2 6- with information content z 6^ with 6- -1, i=0 n i=0 reduce each 6., beginning with 6 Q , to either 1 or 2, corresponding to digit sets a or b. For purposes of the proof, this reduction is performed sequen- tially on digital positions of increasing significance until a digital position with 6 = is reached. The proof differs from that of Section 10.4 in two ways. First, the digit sets in a given digital position may be two or more b's with no a's. In this case, one application of a + a = b is necessary before the reductions by 2a + a = b + a can begin. (This may be necessary in more than one digital position; for example, 8a + 4b +4b + 2a + b + b reduces to 8b + 4b +2b + b). Second, some digital positions may already be reduced, with reduction necessary in digital positions of greater signi- ficance. 1-1 J i+1 It is also possible to permit 6. = 0, i < m, if z r<5 > 2 -2; 1 j=0 3 e.g., 4a + +b + a reduces to 4a + 2a + a. This condition is necessary if there is to be a sequence of consecutive integers, as required by the definition of a digit set. Theorem 10.5 is stated in this manner because decomposition to minimum information content is a design goal from a practical point of view. The objective of the addition operation, for example, is to reduce two inputs to a carry and a sum. Generation of a carry implies expansions of the input representation to more digital positions by reductions of cardinality in digital positions of lower weight. The representation of the sum is consistent 84 with that of each operand, and a minimum storage requirement for the sum is desirable. Both of these objectives are consistent with decompositions to minimum information content. It would be possible to restate Theorem 10.5 to say that any representation p, of diminished cardinality 6 can be converted to any other representation p ? of the same diminished cardinality. The proof is that both p-, and p 2 can be decomposed to the unique representation; hence, since each operation has an inverse, the conversion from the unique representation to p 2 can be accomplished by retracing the steps of decomposition of p~ in inverse order, using the inverse operation at each step. 10.6 Theorem 10.6 Theorem 10.6: The number of carry generators required for de- composition of a digit set to the unique digit set is equal to the information lost during the decomposition process. Proof: Each use of the carry generator causes a loss of 1 bit. The only other operation that affects the information content is the inverse b + a = 2a + a, which is not used for decomposition. Therefore, the infor- mation loss is equal to the number of carry generators. 10.7 Theorem 10.7 Theorem 10.7: The number of generalized half adders required for decomposition of a digit set is given by the formula y - x = AX - A3, in which y is the number of generalized half adders, x is the number of converters aa is the information loss, and A3 is the number of input digit sets of type b minus the number of output digit sets of type b. Proof: The proof is given in section 9.1. 85 10.8 The Effects of Offset. Offset may be treated in a manner similar to the treatment of diminished cardinality in theorems 10.4 and 10.5. For example the offset m . a) of a digit set is qj = Z 2 m. , which is invariant. The offset w has 1=0 associated with it a measure z go , which tends to decrease as decomposition i=0 m proceeds. The mechanism for decreasing z w • is the carry generator, by i=0 1 one of the following: 2a 1 ♦ a^b 1 +. 1 , 2a 1 + a - b 2 + a , 2a 1 .a 1 =b 2 + a\ In each case, 2 units of offset in digital position i become 1 unit of off- set in digital position i + 1. There is a unique offset representation, equivalent to the conventional binary numerical value of the offset. Unfortunately, although decomposition leads to a unique 6 representation, the corresponding representation of ^ is not unique. For example, t 10 = 8a 1 ♦ 4b° + 2a 1 + b°= 8a 1 ♦ 4b° + 2a° ♦ b 2 2 10 1 2 2 = 8a u + 4b" 1 + 2a 1 + b = 8a 1 + 4b^ + 2a u + b\ Equivalently, the following binary numbers, whose digits are 0, 1, and 2, are equal . 1010 = 1002 = 210 = 202 There is thus the possibility that offset considerations might require use of an inverse operation such as b + a = 2a + a , but it is the author's opinion that the use of this type of inverse operation can be avoided by good design. In the absence of proof, theorems 10.4 through 10.7 apply to normalized digit sets only, and are subject to modification if offset requires the operation b + a = 2a + a. 86 11.0 Limitations, Extensions, and Conclusions Examples of some early designs of binary signed-digit adders* indicate possibilities for structures that normal application of decomp- osition procedures would not reveal. For the first example, a mythical input is introduced unnecessarily by interchanging the sum and transfer between the input and intermediate levels. The input level is then 2b+a=b+b+a, where both the input and output a's are mythical. This may be decomposed by b + (2a + a) = b + (b + a) 2a + (2a + a) = 2a + (b + a) (2b) + a = (2a +2a) + a For format 2, the first carry generator is free, since a is a mythical input, so the cost is one carry generator and one half-adder. This compares favorably with the results of Section 9. The second example involves implied relationships between two or more digit sets. 1,0,1 i The output level of a signed digit adder - i -+ is shown in Figure 11.1. The input and 1,0,1 1,0,1 Figure 11.1 Structure intermediate levels are designed in such with implied relationship. a way that the two inputs cannot simultaneously be +1, nor may they simultaneously be -1, hence the output values +2 and -2 cannot occur. A third example involves formats for higher radices. An independent 3 investigation reveals that the number of formats for digit set f , using the eight states of three bits, is 6713, in the same sense that there are 9 formats for digit set b . The extension of the binary theory to radix four 3 1 1 used in section 9 involves f = 2b + b , which requires four bits, or use of g = 4a + 2a + a , in the specialized way of example 9.5.3. obviously, * See section 9.5.3. 87 further investigation of design procedures for higher radix arithmetic is needed. Another area of needed investigation is the substitution of one more complex structure for two or more simpler ones. For example, a logical design for 2a + b = b + b, and use of it as a basic structure, might simplify many signed digit structures. Similarly, combination of 4a + 2a = 2b + 2a and 2a + a = b + a into the single structure 4a + 2a + a = 2b + b + a, could be done to speed up carry propagation. What is involved here is increasing the set of fundamental structures in order to reduce hardware costs or decrease operation times. It should be a relatively simple matter to modify the manipulations of the design language and the procedures for information loss charts to accomodate additional operations. This paper presents a theory for decomposition of complex structures for addition and subtraction into a small number of relatively simple structures, whose complexity ranges up to that of a full adder. The scope of applicability is wide and examples have been given of parallel counters, multiplier arrays, and signed-digit adders. Preliminary investigation indicates that the simple theory of Section 8 is adequate for the design environment for which all inputs and outputs are in conventional binary form; that is, all digits are two-valued and no redundancy exists. Examples are given in section 9 for the opposite extreme, for which all inputs and outputs are represented redundantly as three-valued type b digit sets. For this the general theory is necessary. The general theory requires the use of the generalized half-adder and the carry generator, which can be combined together to form a full adder. In a purely redundant design environment, with all inputs and outputs three 88 valued, the lower bound of the hardware cost is n carry generators and n/2 generalized half-adders, which should be compared with a cost of n full adders for the same structure decomposed in accordance with the simple theory. The lower bound is never achieved in practice, since at least one, and for reasons of speed, more than one, converters are necessary. Each converter requires compensation by the use of an additional generalized half adder, so that the number of generalized half adders is n/2 + x, where x is the number of converters used. Examples are also given in section 9 of structures for which inputs and outputs are a mixture of two valued type a and three valued type b digit sets. It becomes evident that the cost of a structure can be determined to lie between n/2 + 1 generalized half adders plus n carry generators as a lower bound and n full adders as an upper bound. Furthermore, the initial specification of the structure can be used to determine both the layout and the cost, subject only to a limited trade- off between speed and the number of converters. There also exists a structure for assimilation from redundant to conventional form, for which all inputs are type b digit sets and all output digit sets are type a. This structure requires one carry generator per digital position, with x = y = o. 89 The design language proposed for the decomposition process is unusual in a number of ways. Two basic structures, the generalized half adder b = a + a and the carry generator 2a + a = b + a, are essential for the decomposition of complex structures. Each has an inverse, but, for good design, the use of the inverse operations should be avoided whenever possible. It appears that the use of the operation b + a = 2a + a can be avoided entirely, and that the number of uses of the converter a + a = b is small compared to the numbers for the generalized half adder and carry generator. A theoretical maximum for the number of converters seems to be one-half of the number of binary digital positions used to represent the inputs. There appears to be no place in pure mathematics for the design language for decomposition, since equality for all practical purposes is not reflexive, and some operations are preferable to others. 90 12. Bibliography 12.1 Avizienis, A., "Signed-Digit Number Representations for Fast Parallel Arithmetic," IRE Trans, on Electronic Computers, Vol. EC-10, No. 3, pp. 389-400; September, 1961. 12.2 Borovec, Richard T., "The Logical Design of a Class of Limited Carry-Borrow Propagation Adders," M.S. Thesis, University of Illinois, Urbana, Illinois, August, 1968. 12.3 Chow, Catherine Y. and Robertson, James E., "Logical Design of a Redundant Binary Adder," Proc. Fourth Symposium on Computer Arithmetic, Santa Monica, California, Oct. 25-27, 1978. 12.4 L. Dadda, "Some Schemes for Parallel Multipliers," Alta Freg., 34, pp. 349-356, 1965. 12.5 L. Dadda, "On Parallel Digital Multipliers," Alta Freg., 45, pp. 574-580, 1976. 12.6 C. C. Foster & F. D. Stockton, "Counting Responders in an Associative Memory," IEEE Trans, on Computers, C-20, pp. 1580-1583, 1971. 12.7 D. Gajski, "Parallel Compressor," IEEE Trans, on Computers, C-29, pp. 393-398, 1980. 12.8 Ozarka, Ronald M. , "The Design of Maximally Redundant Radix Four Arithmetic Structures," M.S. Thesis, University of Illinois, Urbana, Illinois, May, 1980. 12.9 Robertson, James., "Parallel Digital Arithmetic Unit Utilizing a Signed-Digit Format," U.S. Patent No. 3,462,589, August 19, 1969. 91 12.10 Rohatsch, Fredrlch A., "A Study of Transformations Applicable to the Development of Limited Carry-Borrow Propagation Adders," Ph.D. Thesis, University of Illinois, Urbana, Illinois, June 1967. 12.11 W. Stenzel et al., "A Compact High Speed Parallel Multiplication Scheme," IEEE Trans, on Computers, C-26, pp. 948-957, 197 7. 12.12 E. E. Swartzlander, "Parallel Counters," IEE Trans, on Computers, C-22, pp. 1021-1024, 1973. 12.13 C. S. Wallace, "A Suggestion for a Fast Multiplier," IEEE Trans. on E. Computers, EC-13, pp. 14-17, 1964. BIBLIOGRAPHIC DATA SHEET -R-81-1004 3. Recipient's Accession No. 4. Title and Subtitle A Systematic Approach to the Design of Structures for Arithmetic 5. Report Date Jan. 5, 1981 6. 7. Author(s) James E. Robertson 8. Performing Organization Rept. No. 9. Performing Organization Name and Address Computer Science 222 Digital Computer Laboratory Urbana, IL 61801 10. Project/Task/Work Unit No. 11. Contract /Grant No. MCS 80-00058 12. Sponsoring Organization Name and Address National Science Foundation Washington, D.C. 13. Type of Report & Period Covered 14. 15. Supplementary Notes 16. Abstracts A design tool for the decomposition of binary digital structures for addition and subtraction has been developed. A simplified theory reduces a complex structure to a collection of basic structures of one type, namely, a full adder. The simplified theory is applicable to the design of parallel counters and array multipliers. A general theory is used for decomposition to three types of basic structures, whose complexity is usually on the order of a half-adder. The general theory is applicable to redundant array multi- pliers and signed-digit adders. 17. Key Words and Document Analysis. 17a. Descriptors Addition, subtraction, binary arithmetic, decomposition. 17b. Identifiers/Open-Ended Terms 17c. COSATI Field/Group 18. Availability Statement 19. Security Class (This Report) UNCLASSIFIED 20. Security Class (This Page UNCLASSIFIED 21. No. of Pages 94 22. Price FORM NTIS-35 (10-70) USCOMM-DC 40329-P7I