LIBRARY OF THE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN 5IO.S4 t\o. 2£>7- 342 cop. 2 Digitized by the Internet Archive in 2013 http://archive.org/details/patternarticulat338boro /u- v f *3& /^a^C^j Beport No. 338 COO-10l8-ll8i+ THE PATTERN ARTICULATION UNIT OF ILLIAC III IMPLEMENTATION OF THE HOMOGENEOUS INSTRUCTION "BOOLE" June 20, 1969 by Richard T. Borovec JUL 1 7 1969 COO-1018- 118U Report No. 338 THE PATTERN ARTICULATION UNIT OF ILLIAC III: IMPLEMENTATION OF THE HOMOGENEOUS INSTRUCTION "BOOLE" 1 " hy Richard T. Borovec June 20, 1969 Department of Computer Science University of Illinois Urbana, Illinois 6l801 Supported in part by Contract AT(ll-l)-10l8 with the U.S. Atomic Energy Commission and the Advanced Research Projects Agency. INTRODUCTION It has "been shown previously that an arbitrary homogeneous Boolean function may be described to the Pattern Articulation Unit through the provisions of the instruction "BOOLE". This report des- cribes the hardware for interpreting and executing the instruction "BOOLE". The instruction formats have been defined in reference (l) and will not be repeated here. B. H. McCormick, W. J. Watson and R. T. Borovec, "The Pattern Articula- tion Unit of Illiac III: Homogeneous Boolean Functions in the Iterative Array", Department of Computer Science, University of Illinois, Urbana, Illinois, Report No. 253. -2- 2. THE STALACTITE AS A PROCESSING MODULE 2.1 General Logic Capability Each stalactite contains nine bits of storage, one bit in each of the planes M, 0, 1, ..., 1. In addition to this storage capacity, the stalactite has input and output combinatorial logic which makes elementary processing possible. The stalactite is shown functionally in Figure 1. The blocks labeled M, 0, 1, ..., 7 represent the storage cells. The control signals GNi , IC, 0C, PWi, PRi and TF are common to all stalactites in the array. The GNi control signals select horizontal neighbors (plus M) to be gated into the input OR gate. Signal IC provides selective complementation of the OR gate output. For IC = 0, the OR output is complemented; for IC = 1, the OR output is not complemented. The PWi control signals load the logic value of the OR output (complemented or not) into such storage cells as may be selected. The TF control signal designates whether true outputs or false outputs of the storage cells are to be read. TF = designates false outputs and TF = 1 designates true outputs. When the read signals, PRi, are applied, the corresponding cells are read, according to the TF control signal. The output OR gate is followed by another selective complementing circuit, controlled by the signal 0C. For 0C = 0, the OR output is complemented; for 0C = 1 the OR output is not complemented. It is important to note that a storage cell may not be loaded and read simultaneously. The general logic capability of the stalactite may be summarized by the following tables : Input Functions IC Function 0" g = -i ( GNM&M | GN0&0 | ...|GN8&8) 1 g = GNM&M | GN0&0 | . . . | GN8&8 Where the numbers 0, 1, ..., 8 refer to the corresponding horizontal neighbors -3- ■O KJ s-O - 1aI -iB n B d _> '1 PR: COMPLEMENTED VARIABLES TF = OC = 1 GN: IC = 1 PW: n -7- (9) Vertical sum, true and complemented variables (two micro-operations ) €> M IB CD A B- A B PR: COMPLEMENTED VARIABLES TF = OC = 1 GN: IC = 1 PW: M PR: M, TRUE VARIABLES TF = 1 OC = 1 GN: IC = 1 PW: n (10 ) Vertical product, true variables only (one micro-operation) A&B PR: TRUE VARIABLES TF = OC = GN: IC = 1 PW: n (11 ) Vertical product, complemented variables only (one micro- operation) -*A&— iB . PR: COMPLEMENTED VARIABLES TF = 1 OC = GN: IC = 1 PW: n -8- (12) Vertical product, true and complemented variables (two micro-operations ) T A&B&— 1C&-1D M n :=3 __^ PR: TRUE VARIABLES PR: COMPLEMENTED VARIABLES TF = o TF = i OC = 1 GN: »- OC = GN: w- IC = 1 IC = 1 PW: M PW: n 3. DESCRIPTION OF THE REGISTERS ASSOCIATED WITH THE INSTRUCTION "BOOLE" 3.1 Instruction Register (IR) : 1 2 3 k 5 6 7 8 9 10 11 12 13 Ik 15 16 Instruction Code Availability List (AL) IT bits A specific bit of the instruction register is designated by IR(k), where <_ k < 16. 3.2 Auxiliary Register (AR) ADDR TRUE VAR. COMPL. VAR. Format XaeyABC0123^ 5 6 7 8 1 2 3 k 5 6 T 3 Format Y.N L P # , N L 5 6 718 LJ 1 1 10 ill 12 13 Ik 15 16 IT 18 19 20 |2l|22J23 0P(0) I 0P(: C(0) C(l) A specific bit of the auxiliary register is designated by AR(m), where < m j< 23- 3.3 Associative Address Register (AAR) Row (i) Column 2 1 (J) T 6 5 1* 3 2 1 2k bits A specific bit of the associative address register is designated by AAR(i,j ), where < i < J and ^ j _:_ 2. -10- 3.U Status Register (SR) 8 tits A specific bit of the status register is designated by SR(i) , where <_ i <_ 7. 3.5 Stack Depth Counter (SDC) 3 bits 2 1 A specific bit of the stack depth counter is designated by SDC(j), where <_ j <_ 2. 3.6 Plane Address Register (PAR) ' 3 bits A specific bit of the plane address register is designated by PAR(j), where < j ■: 2. -11- 3.7 Error 1 flag (ERR l) Q 3.8 Error 2 flag (ERR 2) a 3.9 Error 3 flag (ERR 3) a 3.10 Error k flag (ERR h) n 3.11 Error 5 flag (ERR 5) D 1 bit 1 bit 1 bit 1 bit 1 bit -12- h. THE PUSH-DOWN STACK k.l Components of the Push-Down Stack The components of the push-down stack are the stack depth counter (SDC), the status register (SR), the associative address register (AAR), the array of planes, and the availability list (AL). These components are illustrated in Figure 2. U.2 Operation of the Push-Down Stack The push-down stack is used for processing the canonical string representation of an arbitrary homogeneous Boolean function, as described in reference (l). The storage cells of the push-down stack are planes of the array. The status register (SR) indicates which planes are actually included in the stack at any given time. SDC 2 10 AL SR AAR 2 10 ARRAY PLANE 7 6 5 h 3 2 1 Figure 2. Components of the Push-Down Stack -13- When an input to the stack is required, the availability list (All) and the status register are scanned by the plane assignment logic. The first available plane (beginning at the top of the array i.e. plane 7) which is not already being used in the stack is selected as the next stack plane. Its associative address register (AAR) cell is then tagged with the proper stack sequence designator from the stack depth counter (SDC), where the designator "0" denotes the bottom cell of the push-down stack. When a stack operator is executed, it is also necessary to assign a plane for storing the new "top cell" of the stack. This is necessary because of the restriction forbidding the simultaneous reading and loading of a plane (as discussed in the stalactite description) For example, execution of the stack operator OR, (|), requires that the following plane-wide operation be performed: (top cell) | (top cell - l) *> (top cell). The planes designated as "top cell" on the two sides of the replacement description must be different because of the restriction just mentioned. The operation of this example causes the depth of the stack to be reduced by one. The mechanization of this example may be followed by referring to Figure 3. In this illustration, planes W, X, Y and Z may be any of the planes , 1, . . . , 7- W BEFORE EXECUTION Stack Plane Designator n n-1 AFTER EXECUTION Stack Plane Designator n-1 Figure 3. Illustration Showing the Execution of the Stack Operator ( I ) -Ik- Note that planes W and X are released from stack status and plane Z is acquired when this operation is executed. k.3 The push-down stack subroutines Notation: P(X) = next plane to be used in stack n E top cell of stack n-1 E next-to-top cell of stack 1. Input subroutine SDC+1 — ■ »• AAR(X), SELECT P(X) SDC ] . . _ te. CT3^v\ 2. Complement ( i) subroutine P(n)— »P(X) SELECT P(X) 3- 0R( J ) subroutine P(n)|p(n-l)-*P(X) 0-*SR(n),SR(n-l) SELECT P(X) SDC-1 AAR(X), SDC -►SR(X) k. AND (&) subroutine SELECT P(X) P(n)&P(n-l)-*>P(X) 0-»SR(n),SR(n-l) -15- k.k List of Abbreviations and Symbols Abbreviation or Symbol AAR AAR(i.j) ADDR AL AL(i) AR AR(m) ARRAY AUX X AUX Y BOOLE C(i) C(s) CC(n) CS(mn) CSX(n) Meaning Address of plane where final result is to be stored. Associative address register. The specific bit of AAR in row(i), column( j ) . Address field of auxiliary data, format X. Availability list field of basic instruction. The AL bit associated with plane (i). Auxiliary register. Bit(m) of the AR. The collection of 32 x 32 bit plnaes used as words in the PAU. Auxiliary data, format X. Auxiliary data, format Y. Name of the PAU instruction for processing arbitrary homogeneous Boolean functions. C = 1 denotes complemented variables are present in the current elementary function. Elementary function complemented variable(i) Auxiliary data, format Y, bit C(s). Specific bit (state) of CC. State-change control signal controlling change from state (m) to state (n). Miscellaneous control signal (n). -16- Abbreviation or Symbol Meaning Error flag(i). Externally generated signal(i). Stalactite input gating signal for neighbor i. Stalactite input gating signal for self M. H = 1 denotes elementary function is a horizontal logic component. Stalactite input complement control signal. Input . A basic PAU instruction. Instruction Register. Specific bit(k) of IR. Auxiliary data, format Y, bit L(s). Auxiliary data, format Y, bit N(s). Stalactite output complement control signal, Auxiliary data, format Y, operator field(s). Plane ( i ) . Plane which is top of stack. Plane which is next-to-top of stack. Auxiliary data, format Y, bit P(s). Next storage plane to be assigned to stack. Plane addressed by PAR. P(|) =1 denotes elementary OR function. P(&) = 1 denotes elementary AND function. Plane address register. Specific bit(j) of PAR. Pattern Articulation Unit. Push-down stack. -IT- ERR(i) EXT(i) GNi GNM H IC IN INST IR IR(k) L(s) N(s) OC OP(s) P(i) P(n) P(n-l) P(s) P(x) P(z) P(|) P(&) PAR PAR(j) PAU PDS PRi PRM PWi PWM S SDC SDC(j) SDC-1 SDC-1 (j) SDC+1 SDC+1 (j) SPN(i) SPNM(i) SPX(i) SPZ ( i ) SR SR(i) SUBR TAUX T TF TI T(i) V X(n) Y(n) Stalactite plane read control for plane i Stalactite plane read control for plane M Stalactite plane write control for plane i Stalactite plane write control for plane M Stack operator sequence index. Stack depth counter. Bit (j) of SDC. Decremented contents of SDC. Bit (j) of SDC-1. Incremented contents of SDC. Bit (j) of SDC+1. Select P(i) as P(n). Select P(i) as P(n-l). Select P(i) as P(x). Select P(i) as P(z). Status register. Specific bit (i) of SR. Subroutine . Transfer AUX(X or I), (from AUX source). T = 1 denotes true variables are present in the current elementary function. Stalactite true/false control signal. Transfer INST, (from INST source). Elementary function true variable (i). V = 1 denotes elementary function Specific bit (n), format X. Specific bit (n), format Y. -18- THE "BOOLE" PROCESSING FLOW 5.1 Normal Processing The "BOOLE" processing flow is given in a flowchart, Figure h. Reference points are labeled by the symbol [nj The flow begins when an instruction is transmitted to the Instruction Register (IR) and auxiliary data is requested(^- This data is presented in format X (AUX X) and is loaded into the Auxiliary Register (AR). At the same time, the following registers are initialized (set to zero): Stack Depth Counter (SDC), Status Register (SR), and Auxiliary Address Register (AAR). There are three error conditions checked at \2l . If there are no variables listed in the elementary function, error flag 1 is set, fl7/ and control is returned to PAU Main Control j 21/ . If any variable is listed as being both true and complemented error flag 2 is set, I18I , and control is returned to PAU Main Control J2l] . If the PAU is operating in the hexagonal topology mode and more than seven neighbors are speci- fied for a horizontal function error flag 5 is set, l22| , and control is returned to PAU Main Control. If a new operand plane must be defined (as indicated by bit X (y) then the address field (ADDR) of the auxiliary data is loaded into the plane address register (PAR), | ]. Otherwise, execution passes directly to point PTI . At point GlJj "the auxiliary register (AR) bits a and 6 axe decoded to determine the proper subroutine for evaluating the given elementary function. These subroutines are given in Section 1. After executing the subroutine, control passes to f^/ . At point nn , the push-down stack (PDS) input subroutine, des- cribed in Section 3» is executed. This serves to begin the construction -19- of the PDS by assigning it one cell, that which contains the elementary function just evaluated. the operator sequence index (S) is initialized At point (set to zero) and more auxiliary data is loaded into the AE, this time in format Y (AUXY). At point(_TJ bit C(S) is tested. If it is "0" this is a string "period", and the field OP(S) is loaded into the PAR, 8 If C(S) is 'l" the OP(S) field is decoded to determine the appropriate PDS subroutine, These subroutines are described in Section 3. Thre is one forbidden code in the OP(S) field. If this code occurs, error flag 3 is set and control returns to PAU Main Control! 21 . 20 Following the execution of the appropriate PDS subroutine the string punctuation is decoded from the 0P(S) field 11 10 If the punctuation is (;), a new elementary function is to be acquired through the auxiliary data, (AUX X) , and the elementary function processing 2 proceeds as before. If the punctuation is not (;), the next operator field 0P(S) is executed, 16 In this case, is S is 1 , new auxiliary data, AUXY will be requested 6 ; otherwise the second operator 0P(l) is executed 13 In either case, the PDS processing continues as before. At point lU , following the transfer of the final plane address (A) into the PAR, A is compared to the address of the top (i.e. only) cell in the stack. If they are the same, execution is complete. Other- and execution is complete. wise the top cell of the PDS is moved to A 15 In either case control is returned to PAU Main Control 21 The condition of insufficient stack depth to evaluate the function is che cked . If sufficient storage is not available then_error flag h is set 19 and control is returned to PAU Main Control 21 . -20- 5.2 Summary of Error Flags 1. ERROR 1 - There are no variables listed for the current elementary function in the auxiliary data, format X. 2. ERROR 2 - A variable is listed as being both true and complemented for the current elementary func- tion, as defined by the auxiliary data, format X. 3. ERROR 3 - The forbidden code 110 occurs in the current stack operator as defined by the auxiliary data, format Y. h. ERROR k - Insufficient stack depth to evaluate function. 5. ERROR 5 - Illegal neighbors specified in hexagonal topology. -21- FormAEC-427 U.S. ATOMIC ENERGY COMMISSION aecwlSoi UNIVERSITY-TYPE CONTRACTOR'S RECOMMENDATION FOR DISPOSITION OF SCIENTIFIC AND TECHNICAL DOCUMENT ( See Instructions on Reverse Side ) I. AEC REPORT Jeport No gpo 2. title THE PATTERN ARTICULATION UNIT OF ILLIAC III: IMPLEMENTATION OF THE HOMOGENEOUS INSTRUCTION "BOOLE" 3. TYPE OF DOCUMENT (Check one): f~^;a. Scientific and technical report I I b. Conference paper not to be published in a journal: Title of conference Date of conference Exact location of conference. Sponsoring organization □ c. Other (Specify) 4. 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