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/O. YH- 
 £GaS 
 
 Report No. 285 
 
 /Vt 
 
 ^LA,^li 
 
 COO-1018-115^ 
 
 THE PATTERN ARTICULATION UNIT OF ILLIAC III 
 SIMULATION: PART I 
 ITERATIVE ARRAY 
 TRANSFER MEMORY 
 BOOLE CONTROL 
 
 by 
 
 September 20, 1968 
 
 Ping L. Koo 
 Richard T. Borovec 
 
COO-1018-115 1 * 
 
 Report No. 285 
 
 THE PATTERN ARTICULATION UNIT OF ILLIAC III 
 
 SIMULATION: PART I 
 
 ITERATIVE ARRAY 
 
 TRANSFER MEMORY. 
 
 BOOLE CONTROLt 
 
 by 
 
 Ping L. Koo 
 Richard T. Borovec 
 
 September 20, 1968 
 
 Department of Computer Science 
 University of Illinois 
 Urbana, Illinois 6l801 
 
 t 
 Supported in part by Contract AT(ll-l)-10l8 with the U.S. Atomic Energy 
 Commission and the Advanced Research Projects Agency. 
 
PAU Simulation 
 
 1. General Description 
 
 The PAU is simulated in three parts: control, Iterative 
 Array and Transfer Memory, all written in PL/1. 
 
 The Iterative Array is a 1024 module parallel processor, 
 and the Transfer Memory is a 48 x 1024-bit read/write memory. 
 
 In the simulation program, both the IA and TM are defined as 
 three-dimensional arrays , each element in the array being one bit long 
 (bit attribution). Since the borders of the IA function differently than 
 the interior, they will be defined separately. 
 
 The IA is defined in the simulation program as : 
 
 IA(P, Y, X) 
 P: Plane No. -1 to 7 
 X, Y: Coordinate in a plane 
 to 31 
 
 9 planes 
 
 32 bits 
 
 32 bits 
 
 The border of each plane in the IA is defined as 
 
 32 bits 
 
 NW 
 
 WB 
 
 SW 
 
 NB 
 
 SB 
 
 NE 
 
 EB 
 
 SE 
 
 EB(p) 
 SB(p) 
 WB(p) 
 NB(p) 
 NE(p) 
 SE(p) 
 SW(p) 
 NW(p) 
 
 East border (32 bits long) 
 South border 
 West border 
 North border 
 Northeast corner (l bit) 
 Southeast corner 
 Southwest corner 
 Northwest corner 
 
 32 bits 
 
Since information flows between the IA and TM, the TM is also 
 simulated as a three dimensional array with a total of 1+8 x 1021+ bits. 
 
 The TM allows information to be read or written as either 
 short words (1+8 bits) or long words (1021+ bits). 
 
 In the simulation program, the TM is defined as: 
 
 TM (P, z Z ) 
 where P: Plane No. ; to 1+7 
 
 Z , Z : Used to get bit number in a plane; 
 
 to 31 
 Bit No. = 31 Z + Z 2 
 
 1021+ 
 
 r~ 
 
 1+8- 
 
 For long word operation a 6-bit address is required and for 
 short word operation, a 10-bit address is required. This address is 
 given by (Z ± - l) * 31 + Z g . 
 
II. General Flow 
 
 The "DRIVER" may serve as a test program, which includes 
 setting up PAU orders, and the data set to be used. In PL/1 this program 
 is defined as the 'MAIN' program and execution starts here. 
 
 The "PAU Control" is a subroutine, which simulates the PAU 
 control logic. It will decode PAU orders, etc. " It may call TMSIM or 
 IASIM to perform the necessary operation. 
 
 "TMSIM" is a subroutine which simulates the Transfer Memory. 
 
 "IASIM" is a subroutine which simulates the Iterative Array. 
 
 For the purpose of communication between programs, all planes, 
 registers and gate signals must be defined as "External" variables, and 
 must appear in every program. 
 
Iterative Array Simulation 
 
 1. Name: IASIM 
 
 2. Functional Description: 
 
 This routine is used to simulate the Iterative Array. All 
 gate signals will be supplied by the 'CONTROL 1 routine, which simulates 
 the control logic of the PAU. 
 
 The Iterative Array (IA) is a 102U-module parallel processor 
 comprising nine planes of horizontal registers interconnected to provide 
 logical functions of vertically-related cells (cells having identical 
 x, y coordinates) of nearest neighbors in the x, y directions, and 
 various combinations of vertical and nearest neighbor cells. 
 
 Associated with each module, is an INBUS and OUTBUS. Therefore, 
 there are 1024 INBUSes and 102*+ OUTBUSes. 
 
 Depending on the gate signals TF (true/false select) and 0C 
 (output complement select), any one of the four functions f , f , f , f, , 
 may be formed on the OUTBUS. The OUTBUS function formed is made available 
 to the eight neighboring modules as well as to the originating module. 
 
 Depending on the gate signal IC (input complement select), 
 either function g or g~ is formed on the INBUS, and may be gated into 
 one or more of the registers. Then PLANE WRITE, TALLY, or TALLYH0 is 
 performed depending on the gate signal Z0 (pulse zero/one select), T0 
 (Tally one's select) and TZ (Tally zero's select), 
 
 3. Formal Calling Sequence: 
 
 CALL IASIM 
 
 k. Formal Parameter Description: None 
 
 5. Implicit Parameter Description: 
 
 The simulated IA and all gate signals must be defined as 
 variables with EXTERNAL attributes. All gate signals are supplied by 
 the calling programs and remain unchanged, but the contents of the simulated 
 IA will be changed. 
 
5. Implicit Parameter Description: 
 
 The simulated IA and all gate signals must be defined as 
 variables with EXTERNAL attributes. All gate signals are supplied by 
 the calling programs and remain unchanged, but the contents of the 
 simulated IA will be changed. 
 
 6. Subroutines Used: 
 
 TIMER 
 
 7. Operational Description: 
 7.1 English Text 
 
 (A) The iterative array is simulated as a 3-dimensional array: 
 IA (P, y, x), each element being one bit long, where P is plane 
 number: -1 to 7* plane -1 is the same as plane M; x, y are 
 coordinates in a plane and range from to 31. 
 
 Cells in a plane are numbered according to 32y + x; 
 INBUS and OUTBUS are numbered the same way. Therefore, the 
 8 nearest neighbors will be represented by cell numbers as : 
 
 Neighbor No. Cell No. 
 
 (self) n = n 
 
 o 
 
 1 n = n+1 
 
 2 n 2 = n+35 
 
 3 n = n+3^ 
 k n^ = n+33 
 
 5 n^ = n-1 
 
 6 n 6 = n "35 
 
 7 n = n-3U 
 
 8 n g = n-33 
 
 (B) The borders of the IA are simulated as east border (EB), 
 south border (SB), west border (WB) and north border (NB] 
 each consisting of 32 bits; and h corners (NE,SE,SW,NW) 
 each 1 bit long. 
 
(C) The following notation is used: 
 
 | = logical 0R 
 
 & = logical AND 
 
 — 1= logical N0T 
 
 P . = plane i , -1 < i < ] 
 
 P. = coordinate position (j,k) of plane i, 
 
 <_ j , k <_ 31 or cell (32j+k) of plane i 
 C(X) = contents of X, where X is a plane, or a neighbor 
 
 or an INBUS or an OUTBUS 
 GN. = Gate Neighbor i, <_ i <_ 8 
 N. = Corresponding cell number for neighbor i 
 PR. = Read out of plane i, -1 <_ i <_ 7 
 PW. = Write into plane i, -1 <_ i <_ 7 
 OUTBUS. = OUTBUS of cell i, <_ i £ 1023 
 
 INBUS. = INBUS of cell i, < i < 1023 
 
 1 — — 
 
 (D) The IA word will be supplied by the calling program (may- 
 be either the 'CONTROL' or 'DRIVER'), and is simulated 
 
 as follows 
 
 Component of 
 IA word 
 
 Name Used In 
 The Simula- 
 tion Program Attribute 
 
 Control Byte 
 
 True/False Select TF 
 
 1 Bit 
 
 Output Complement Select 
 
 0C " 
 
 Gate Neighbor M 
 
 GN-1 " 
 
 Input Complement Select 
 
 IC " 
 
 Tally One's Select 
 
 T0 
 
 Tally Zero's Select 
 
 TZ 
 
 Pulse Zero/One 
 
 Z0 " 
 
 Gate Direct Out 
 
 GD0 " 
 
 Plane Read Byte 
 
 'Gate Neighbor Byte 
 Plane Write Byte 
 
 PR Array of 9 
 
 P element (-1 to 7) 
 each 1 bit 
 
 GN Array of 9 
 
 element (0 to 8) 
 
 PW Array of 9 
 
 p element (-1 to 7) 
 
(E) The basic logical functions of the IA will be 
 simulated in the following steps : 
 
 (1) First form f function on the OUTBUS for every 
 cell (or for coordinate positions (j,k), 
 
 < j, k <_ 31): 
 
 a) If TF = 1, then form fl, else form f3; 
 
 where fl = (PR &C(P ))j(PR &C(P. . ,)) 
 
 -1 -lsJ>k o 0,j,k 
 
 i(PR l & C(P T J k )} 
 f3=(PR_ 1& C(P_ 1Jjk ))|(PR; & C(P 05 . jk ))|... 
 
 |(PR T& C(P T) . jk )) 
 
 b) If 0C=O then complement the f function 
 
 c) If GD0=1, then the function formed on the 
 OUTBUS of that cell will be f|c(lNBUS cell); 
 otherwise, f will be formed on the OUTBUS. 
 
 (2) To form g function on the INBUS of every cell: 
 
 a) Form g function; 
 where 
 
 g = (GN_ 1 &C(P_ 1 ^ jk ))|(GN o &C(0UTBUS o ))|... 
 
 | (GN Q &C(0UTBUSg)) 
 
 b) If IC = 1, then the function formed on the 
 INBUS of that cell will be g; otherwise, it 
 will be the complement of g. 
 
 (3) If Z0 = 1, then write the contents of INBUS of 
 every cell into the corresponding cell of the 
 plane whose Plane Write signal (PW) is 0. 
 
 (U) If Z0 = and T0 = 1 , then form TALLY for every 
 cell of each plane. 
 The following operation is implemented: 
 
 P. = C(INBUS „) & P. . . . |P. , - , < i < 7 
 
 r i cell l-l, j ,k' i,j,k» - — 
 
 where effectively P = 1 
 
(5) If Z0 = and T0 = 1, then form TALLYH0 for 
 every cell of each plane. 
 The following equation is implemented: 
 P. - -,(C (INBUS cell ) & hP WJ|k ) &P liJ>k ),0 <i iT 
 
 where effectively P ft = 
 
 7.2 Flow Chart: 
 
 The flow chart is attached. 
 
 The following symbols are used in the flow chart : 
 
 IA(i,j,k): coordinate position (j,k) of plane i 
 
 INBUS(N): INBUS of cell N 
 
 0UTBUS(N): 0UTBUS of cell N 
 
 F: f function 
 
 G: g function 
 
 CELL: cell number 
 
 NBR(i): corresponding cell number for neighbor i 
 
 All control signals have been defined in (D), of J.l. 
 
 Error Condition: 
 
 Not applicable, all errors will be checked in ' C0NTR0L' 
 
10 
 
 I = o 
 
 J = 
 
 NBR Q 
 1 
 
 = 
 
 
 
 1 
 
 2 
 
 = 
 
 35 
 
 3 
 
 z 
 
 34 
 
 4 
 
 = 
 
 33 
 
 5 
 
 = 
 
 -1 
 
 6 
 
 = 
 
 -35 
 
 7 
 
 = 
 
 -34 
 
 8 
 
 = 
 
 -33 
 
 CELL = 321 + J 
 
 F = PR(-I) a IA(-I,I,J)| PR(0)aiA(0,I,J )| 
 
 • • • |PR(6) a IA(6,I,J)| PR(7) a IA(7,I,J) 
 
 F = PR(-I) a IA(-I,I,J)| PR(O) a IA(0,I,J)| 
 ••• |PR(6)a IA(6,I,J)|PR(7)aiA(7,I,J) 
 
 F = F 
 
 dUTBUS (CELL) = INBUS (CELL)JF 
 
 OUTBUS (CELL) = F 
 
 J = J + I 
 
 IASIM Flowchart 
 
I = 
 
 J = 
 
 CELL = 321 + J 
 
 G = GN(-I ) 8 IA(-I , I, J ) 
 
 K = 
 
 G = G (GN(K) ft OUTBUS(CELL + NBR( K ) ) 
 
 K = K + I 
 
 G = G 
 
 INBUS(CELL) = G 
 
 J = J + I 
 
 •» 1=1 + 
 
 11 
 
 P3 
 
 IASIM Flowchart (Continued) 
 
12 
 
 I ' o 
 
 (TALLY HO) 
 
 I« 
 
 J = 
 
 j.O 
 
 CELL » 321 ♦ J 
 
 I»(0,I,J)» 1NBUS(CELL)|I*(0,I,J) 
 
 K = I 
 
 IA(K,I,J )=(1NSUS(CELL) • ZA(K-I ,1, J )) | IA( K , I, J ) 
 
 K « K +! 
 
 CELL* 321+ J 
 
 IA(7,I,J) ■ INBUSICEl 
 
 ZEZ 
 
 K ■ 6 
 
 IA(K,I,J) c INBUSICEl 
 
 K :K - I 
 
 IASIM Flowchart (Continued) 
 
13 
 
 (write ) 
 
 1 = 
 
 J = 
 
 CELL = 32 I+J 
 
 K = 
 
 IA(K, I , J ) = INBUS(CELL) 
 
 K = K + I 
 
 1=1 + 1 
 
 TIMER 
 
 IASIM Flowchart (Continued) 
 
Ill 
 
 Transfer Memory Simulation 
 
 1 . Name : TMSIM 
 
 2. Functional Description: 
 
 This routine is used to simulate the Transfer Memory (TM) of 
 the PAU. The TM is simulated as a three dimensional matrix TM(I,J,K). 
 The range of I,J,K are: 8 to 55, to 31, to 31 respectively. 
 
 The TM may be operated in Read and Write modes in two submodes : 
 
 a) Long word submode : The 1±9»L52 bits of the TM are arranged • 
 as kQ 102U bit words, represented as TM(l,*,*) in this 
 simulation. 
 
 b) Short Word Submode: The 1*91,52 bits of the TM are arranged 
 as 1021* U8-bit words called Z words. They are represented 
 as TM(*,J,K) in this simulation. The short word address 
 (Z-address)is formed by N = J*32+K. 
 
 An Encoder is also simulated in this section which is used 
 
 to form the Z address when it is not supplied by the control 
 
 signal. 
 
 All control signals are supplied by the calling program. 
 
 3. Formal Calling Sequence: 
 
 CALL TMSIM 
 
 h. Formal Parameter Description: None 
 
 5. Implicit Parameter Description: 
 
 To save execution time, the following parameters are not handled 
 by the CALL, but they are all declared as EXTERNAL variables, so they are 
 available for this routine. 
 
15 
 
 LGSH: = 1 long word submode 
 
 = short word submode (Z-word) 
 ZPAU-ZEND: = 1 Z ADDR is supplied by the calling program 
 
 = ENC0DER is used to form ZADDR. 
 MARK0P = 1 Mark the M register only but do not read or write the 
 
 contents of the memory. 
 TMG0: = 1 Start a read or write cycle 
 
 TMG0MARK: = 1 Same as TMG0 with a Mark operation included. 
 RDLD: = 1 Read 
 
 = Write 
 AADDR: A-address interpreted as 8-55 specified the address of the 
 
 long word to be operated upon. 
 ZADDR: Z-address , specified either the address of the short word to 
 be operated upon or the subscript of the M register flip-flop 
 to be set to 1. 
 SWI: Provides the short word to be loaded into memory. 
 
 6. Subroutines Used: ENC0DER, TIMER 
 
 7. Operational Description: 
 7.1 English Text 
 
 (1) All control signals as well as TM and IA must be declared as 
 external variables for the purpose of communication between 
 subroutines. 
 
 For easy debugging, the control signals, supplied by the 
 calling program, are printed out. 
 
 (2) At point [l] in the flowchart, for long word mode, TMG0 
 must be 1, otherwise an error message is printed out. 
 The A-address (AADDR ) is supplied by the calling program. 
 For READ operation, the M plane of IA (not including border) 
 is replaced by the long word of TM at address AADDR, as 
 shown at point [2]. For WRITE operation, the long word of TM 
 at address AADDR is replaced by the contents of M plane of 
 IA, as shown at point [3]. 
 
16 
 
 (3) In short word mode, if ZPAU-ZEND = 0, then ENC0DER is used 
 to form the address of the Z-word (ZADPR) to be operated 
 upon; otherwise, ZADDR is supplied by the calling program. 
 
 (h) ZADDR is interpreted as 0-1023, it is then separated into 
 two parts Z and Z , which satisfy ZADDR = 32*Z2+Z1. 
 Since TM is simulated as three dimensional matrix, Z and 
 Z correspond to the second and third subscript respectively, 
 
 (5) For TMG0 = 1 or TMGOMARK = 1. In the case of a READ opera- 
 tion, the SWI is replaced by the short word of the TM at 
 address ZADDR. For a WRITE operation, the short word of 
 the TM at address ZADDR is loaded from SWI. 
 
 (6) For MARK operation only (MARK0P = l) or TMGOMARK = 1, 
 
 the element of the M plane of the IA at coordinate (Z ,Z ) 
 is set to 1. 
 
 7.2 Flow Chart: 
 
 The flow chart is attached. 
 
 The symbols used in the flow chart are: 
 
 IA(-1,J,K): Element with coordinate (J,K) of the M plane of IA. 
 
 IA(-1,*,*): The M plane of IA. 
 
 TM(AADDR,*,*) : The long word of TM at address AADDR 
 
 TM(*,Z1, Z2): The short word of TM at address ZADDR, where 
 
 ZADDR = 32.Z1+Z2 
 LGSH: Long or short word control signal 
 RDLD: READ or WRITE control signal 
 ZP - ZE: =1 ZADDR is formed from ENCODER 
 
 = ZADDR is supplied by calling program 
 AADDR: Address of the long word to be operated on supplied by 
 
 calling program. (6-bit) 
 ZADDR: Address of 1he short word to be operated on, or the 
 
 coordinate of the element in the M plane to be set to 
 
 1. (10-bit) 
 Zl: Bit 1-5 of ZADDR 
 Z2: Bit 6-10 of ZADDR 
 
17 
 
 TMG0, TMG0MARK, MARK: Control signal 
 
 SWI(N): Nth element of short word information, array of U8 
 
 element, 1 bit each. 
 SWI(*): Entire SWI 
 
 8. Error Condition 
 
 For long word mode, TMG0 must be 1, otherwise an error message 
 will be printed, and execution of this program is terminated. 
 
 9. Internal Procedures Defined: 
 
 ENC0DER: This routine is used to search the M plane of IA. 
 Starting at coordinate (0,0), search each element in the row for the 
 first 0; if one is not found then search the second row until an element 
 with is found or the entire M plane has been examined. The coordinate 
 IA(-1,Y,X) of the 0-valued element is the ZADDR (= 32*Y+X) and S0MEMARK 
 is set to 1, if no 0-valued element is found S0MMEMARK is set to and 
 control is returned to the calling program (TMSIM). 
 
DECLARE 
 ALL EXTERNAL 
 VARIABLES 
 
 18 
 
 PRINT 0UT 
 ALL C0NTR0L 
 SIGNALS 
 
 m 
 
 -*-C TMG0= I 
 
 N 
 
 PRINT 
 
 ERR0R 
 MESSAGE 
 
 _GE) 
 
 IA(-I,*,*) 
 = TM(AADDR, 
 
 TM(AADDR,*,*) 
 =IA(-I,*,«) 
 
 TMSIM Flowchart 
 
QO 
 
 
 Zl = ZADDR 
 
 TMG flMARt K, Y fc 
 
 IA(-I,ZI,Z2) 
 
 -** 
 
 TM(«,ZI,Z2) 
 = SWIU) 
 
 JMG0MARK 
 
 N 
 
 SWI(*) 
 = TM(*,ZI,Z2) 
 
20 
 
 S0MEMARK 
 = 
 
 IY = 
 
 TMSIM Flowchart (Continued) 
 
21 
 
 B00LE Control Logic Simulation 
 
 1 . Name : B00LC0N 
 
 2. Functional Description: 
 
 This routine is used to simulate the logic control of the PAU 
 instruction B00LE. B00LE is a general PAU instruction for specifying a 
 homogeneous Boolean function. The PAU instruction consists of a 9-bit 
 Mnemonic byte and an 8-bit Availability list. The availability list 
 designates which planes of the Iterative Array may be used for inter- 
 mediate storage in evaluating the 'B00LE' function. 
 
 After decoding the instruction, the 'B00LE' control will begin 
 to request auxiliary information. In the course of processing the instruc- 
 tion, information requests will continue, and must be honored by the con- 
 trolling TP until the information required for evaluating the function 
 has been completely transmitted. The auxiliary information may be either 
 in X- format or Y- format. X- format is used when a new elementary function 
 is to be introduced, and Y-format is used to introduce secondary operators 
 The address in which the result is to be stored is given in the final 
 Y- format . 
 
 An elementary function will be defined as any function meeting 
 both of the following criteria: 
 
 (1) The domain of the function is restricted either to 
 
 a) any one plane 
 or b) the vertical column passing through bit position 0. 
 
 (2) The function is a simple Boolean sum (0R) or a simple 
 product (AND) of the individual variables. 
 
 The secondary operators will be conventional AND (&), 0R (|) and negation 
 (-""') of Boolean algebra, and they will operate upon elementary functions. 
 
22 
 
 An arbitrary homogeneous Boolean function must be written in 
 the canonical form before the 'B00LE' instruction is used. For example, 
 the function 
 
 P7 =-»(l2) & (13) | (27) & (30) 
 is written as F: [-.(12)&(13) ] ; [27]; [30] & |; 7 
 
 where F denotes the function, [ ] delimits the elementary function. 
 
 3. Formal Calling Sequence 
 
 CALL B00LC0N 
 k. Formal Parameter Description: There are no parameters to be handled 
 but all the auxiliary data in either X or Y format must be read in a LIST 
 directed form. For detail of LIST directed input see the PL/l Language 
 specifications. Simply speaking, all input items are separated by a comma 
 or blank (s). In this routine, the auxiliary data required is first in 
 X format, then a mixture of Y and X formats. Since the auxiliary data is 
 defined as a bit-string of 2^-bits (X format) or 8-bits (Y format), the 
 data must be in the following form: 'data 'B, where data is either 2k 
 or 8 digits with value or 1. 
 
 5. Implicit Parameter Description: The instruction word is supplied by 
 the calling program; the Iterative Array and the control signals for the IA 
 are used by this routine and must be declared as external variables. After 
 execution of a 'B00LE' instruction, the contents of the IA will be changed. 
 
 6. Subroutines Used: 
 
 IASIM, PNT0UT, TIMER 
 
 7. Operational Description 
 7.1 English Text 
 
 (l) All registers and counters are defined as bit string with the 
 same length as in the hardware. To save execution time, any 
 variable which is concerned with each plane in the IA will be 
 defined as an unpacked array by the proper length bit string 
 such as availability bit (AL), true variables and comple- 
 mented variables (TURE, C0MP) of the auxiliary information 
 in the X format, etc. In these cases, we can't use the 
 'DEFINED' attribute to assign bits 10-17 of the Instruction 
 
23 
 
 Register (IR) to the AL, it must be explicitly stated in 
 the program; the same holds with the Auxiliary Register 
 (AR) in either X or Y format. 
 
 (2) At point [0], the instruction word (supplied by the calling 
 program) is loaded in the Instruction Register (IR). Normally, 
 IR will be decoded to see if the instruction is a ' B00LE' 
 instruction or not. But at the present time, the instruction 
 code for ' B00LE' is undefined; therefore, it is assumed an 
 indicator named B00LE is set to 1 by the cabling program 
 
 for 'B00LE' as shown at point [l]. 
 
 (3) Then AL(N), N = to 7, is explicitly stated to be bits 10 
 to IT of IR. 
 
 The auxiliary data in X format is then requested (in this 
 simulation it is read from an external device) and loaded 
 into the Auxiliary Register (AR). Then elements of the 
 X-format: a, 6, y, ADDR, TURE(N), C0MP(N) N = to 8; are 
 taken from the AR. 
 
 (h) The Associative Address Register (AAR), Status Register (SR) 
 and Stack Depth Counter (SDC) are initially cleared. 
 
 (5) Starting at point [2], a test is made for a type 1 error. 
 If there are no variables listed for the current elementary 
 function in the auxiliary data of format X, the execution 
 of this routine will be terminated. 
 
 (6) Starting at point [3], a test is made for a type 2 error. 
 If a variable is listed as being both true and complemented 
 for the current elementary function in the auxiliary data of 
 format X, the execution of this routine will be terminated. 
 
 (7) At point [k] 9 if a - 1 (i.e. a new operand plane must be 
 defined) then ADDR of the auxiliary data format X is loaded 
 into the Plane Address Register (PAR). 
 
2k 
 
 (8) There are 12 different types of elementary functions which 
 
 will be evaluated by the stalactities in the iterative array. 
 The elementary function to be evaluated is determined by a, 
 3 and the variables listed as true or complemented: 
 
 1) o & 3 
 
 2) a & 3 
 
 3) a & 3 
 k) a & 3 
 
 Horizontal sum (0R) 
 Vertical sum (0R) 
 Horizontal product (AND) 
 Vertical sum (AND) 
 
 For each of the k types listed above, there may be either 
 variables only, complemented variables only or both true 
 and complemented variables. 
 
 At point [5], the control signals which are common for all 
 12 types of elementary functions T0, TZ, GD0, Z0, IC, GN(-l) 
 and PR, PW will be set, and the push-down-stack input 
 routine and select plane X(the plane to be used as inter- 
 mediate storage to hold the elementary function just evaluated) 
 routine will be called. 
 
 Then a and 3 are used to determine the appropriate subroutine 
 for evaluating the given elementary function, as shown at 
 point [6j. For debugging purposes (before and after) 
 the evaluation of the given elementary), the contents of 
 some planes are printed out by using the routine 'PNT0UT 1 . 
 
 (9) At point [7] , the push-down-stack sequence index (S) is 
 initially set to 0, the auxiliary data in Y format is 
 requested and loaded into the.AR. 0P(O), YC(0), 0P(l) and 
 YC(l) are taken from the AR. 
 (10) At point [8], YC(S) is tested. If it is '0*, it is a 
 
 string 'period', the final plane address A is found (as at 
 point [10]) and then the field 0P(S) is loaded into the PAR 
 (as at point [ll]). The address (A) is compared with the 
 
25 
 
 . address of the top cell in the stack (PAR). If they are 
 the same, execution is complete. Otherwise, the top cell 
 of the PDS is moved to the location (A) by calling the 
 routine 'PDS-TO-A' , and execution is completed. 
 
 (11) If YC(S) is '1', as at point [9], the 0P(S) field is 
 decoded to determine the appropriate PDS routine, as started 
 at point [ll]. If the forbidden code '110' occurs, error 
 flag 3 is set, and execution is terminated. 
 
 (12) Following the execution of the PDS routine, the punctuation 
 is decoded at point [13] • If the punctuation is ' ;' a new 
 elementary function is required in auxiliary data format 
 
 X, at point [lU]; and the elementary function processing 
 proceeds as before, starting at step (5)- 
 
 (13) If the punctuation is not ';' as at point [15]» the next 
 operator field 0P(S) is executed. In this case, if S = 1, 
 new auxiliary data in Y format will be requested and step 
 (9) is repeated. If S = 0, the second operator 0P(l) is 
 executed and control returns to step (ll). 
 
 This procedure continues until YC(S) is '0'. 
 
 (lH) The interpretation of auxiliary data in Y format will be 
 listed below; YC(S) is 1 bit long, 0P(S) 3-bit s long. 
 YC(S) 0: stop (period) 
 
 1: continue 
 0P(S) If YC(S) = 1 
 
 NIP Meaning 
 
 I 
 
 l» 
 
 & 
 
 &; 
 
 Forbidden 
 
 T-P Yr(&\ = D (AV(<1) la in+Pr-T.-y^+pH a <5 D-7 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 1 
 
 
 
 
 
 1 
 
 
 
 1 
 
 
 
 
 
 1 
 
 
 
 1 
 
 1 
 
 1 
 
 
 
 1 
 
 1 
 
 1 
 
26 
 
 7.2 Flow Chart 
 
 The flow chart is attached. 
 
 The symbols used in the flow chart are: 
 
 INST: Instruction word ( 17-bit) 
 
 IR: Instruction Register (17-bit) 
 
 C0DE: Memonic byte (9-bit) 
 
 AL(N): Availability list, N = to 7, 1 bit each. 
 
 B00LE: 1 bit indicator, (= 1 means the instruction is 'B00LE 1 ) 
 
 AUXY: Auxiliary data in X format (2k bit) 
 
 ALPHA: a (bit 1 of AUXX) 
 
 BETA 
 GAMA 
 ADDR 
 
 ture(n; 
 
 6 (bit 2 of AUXX) 
 
 Y (bit 3 of AUXX) 
 
 If Y = 1 ADDR is the plane number of the new operand plane, 
 
 if Y = this field is ignored. 
 
 N = to 8; 1 bit each, a list of true variables. If 
 TURE(N) = 1 then plane N is defined as true variable. 
 
 C0MP(N) : N = to 8, 1 bit each, a list of complemented variables 
 
 AUXY: Auxiliary data in Y format (8-bit) 
 
 0P(N): N = 0, 1; 3 bit each, as defined in AUXY 
 
 YC(N): N = 0,1; 1 bit each; as defined in AUXY 
 
 AR: Auxiliary Register (2^-bit) 
 
 AAR(N): N = to 7; 3-bit each, the Associate Address Register 
 
 SR(N): N = to 7, 1 bit each, the Status Register. 
 
 SDC: Stack-Depth-Counter (3-bit) 
 
 PAR: Plane Address Register (3-bit) 
 
 A: Final Plane Address (3-bit) 
 
 S: Push-down-stack sequence index ( 1-bit) 
 
 ERR1, ERR2, ERR3 : Error flags ( 1-bit each) 
 
 T: =1 means there are some true variables in AUXX 
 = " " " no " 
 
 C: =1 means there are some complemented variables in AUXX 
 
 = 
 
 no 
 
27 
 
 TF: True/false select 
 
 0C: Output complement select 
 
 IC: Input complement select 
 
 T0: TALLY ONE select 
 
 T2: TALLYH0 select 
 
 Z0: Pulse zero/one select 
 
 GD0: Gate direct out select 
 
 GN(N): N = -1 to 8, gate neighbor select 
 
 PR(N): N = -1 to 7, plane read select 
 
 PW(N): N = -1 to 7» plane write select 
 
 X: Plane number of the plane used as intermediate storage 
 
 NO: Top of the PDS 
 
 Nl: Next to top of the PDS 
 
 PN0UT(N): N = -1 to 7, 1 bit each, a list of the plane whose 
 
 contents are to be printed out. 
 N, L, P: Bit 1, 2, 3 of 0P(S) respectively. S may be either 
 
 or 1. (l bit each). 
 
 8. Error Condition: 
 
 There are 3 types of errors. If any one of them occurs, execution 
 will be terminated. 
 
 Type 1: There are no true variables and no complemented variables 
 
 in AUXX. 
 Type 2: One variable is defined as both true and complemented 
 
 variables in AUXX. 
 Type 3: The forbidden code for 0P(S) - '110' occurs in AUXY. 
 
 9- Internal Procedures Defined: 
 
 The subroutines for elementary function, PDS routines, select 
 X, NO, Nl are trivial and they will be described below, but no flow chart 
 is attached. 
 
28 
 
 i) Elementary Functions: 
 
 There are 12 elementary functions , 8 of them involve only 
 variables of one kind (true or complemented, but not mixed) and can be 
 evaluated by executing a single micro-operation in the IA. Four of them 
 involve both kinds of variables and require two consecutive micro-operations, 
 In these k cases , the M-plane is the intermediate plane used to store the 
 partial results. 
 
 After the elementary function has been evaluated, it must be 
 stored. The selection of the plane to store the result is done by calling 
 the routine PX to assign the plane X. The contents of plane X will be 
 printed out. Only the micro-operation(s) for each function will be des- 
 cribed below: 
 
 (1) 0R-H-T: Horizontal sum, true variables only. 
 Set: TF, 0C, DR(PAR) , PW(X) = 1; 
 
 GN = TURE 
 
 Then call IASIM to evaluate the function. 
 
 (2) 0R-H-C: Horizontal sum, complemented variables only 
 Set: TF, 0G = 0; 
 
 PR(PAR), PW(X) = 1; 
 GN = C0MP; 
 then call IASIM to evaluate the function. 
 
 (3) 0R-H-TC: Horizontal sum, both true and complemented 
 variables. 
 
 Set: TF = 0; 
 
 0C, PR(PAR), PW(-l) = 1 
 
 GN = C0MP 
 then call IASIM to evaluate the partial result 
 then set TF = 1, PW(X) = 1 
 
 GN = M, TURE 
 then call IASIM to evaluate the result. 
 
 {k) AND-H-T: Horizontal product, true variables only 
 Set: TF, 0C = 
 
29 
 
 PR(PAR), PW(X) = 1 
 
 GN = TURE 
 
 Then call IASIM to evaluate the function 
 
 (5) AND-H-C: Horizontal product, complemented variables 
 only- 
 Set: 0C = 
 
 TF, PR(PAR), PW(X) = 1 
 
 GN = C0MP 
 
 Then call IASIM to evaluate the function. 
 
 (6) AND-H-TC: Horizontal product, both true and complemented 
 variables. 
 
 Set: 0C = 
 
 TF, PR (PAR), PW(-l) = 1 
 
 GN = C0MP 
 
 Then call IASIM to evaluate partial result 
 
 Then set TF = 
 
 PW(X) = 1 
 GN = M, TURE 
 Then call IASIM to evaluate the result. 
 
 (7) 0R-V-T: Vertical sum, true variables only 
 Set: TF, 0C, PW(X) = 1 
 
 GN = 
 
 PR = TURE 
 
 Then call IASIM to evaluate the function 
 
 (8) 0R-V-C: Vertical sum, complemented variables only 
 Set: TF, GN = 
 
 0C, PW(X) = 1 
 
 PR = C0MP 
 
 Then call IASIM to evaluate the function 
 
30 
 
 (9) 0R-V-TC: Vertical product, both true and complemented 
 variables . 
 Set: TF, GN = 
 
 0C, PW(-l) = 1, PR = C0MP 
 and call IASIM to evaluate the partial result 
 then set TF, PW(X) = 1 
 
 PR = M, TURE 
 and call IASIM to evaluate the final result 
 
 (10) AND-V-T: Vertical product, true variable only 
 Set: TF, 0C, GN = 
 
 PW(X) = 1 
 PR = TURE 
 and call IASIM to evaluate the function. 
 
 (11) AND-V-C: Vertical product, complemented variables only 
 Set: TF, PW(X) = 1 
 
 0C, GN = 
 PR = C0MP 
 and call IASIM to evaluate the function 
 
 (12) AND-V-TC: Vertical product, both true and complemented 
 variables 
 
 Set TF, PW(-l) = 1 
 
 0C, GN = 
 
 PR = C0MP 
 and call IASIM to evaluate the partial result, 
 then set: TF = 0, PW(X) = 1 
 
 PR = M, TURE 
 and call IASIM to evaluate the final result 
 
 ii) Assignment of Intermediate Storage Plane 
 The calling sequence of this routine is 
 
 CALL PX(X); where X is the plane number of the assigned plane, 
 The availability list (AL) and the status register (SR) are 
 searched at the same time (from plane ? to 0). If SR of 
 
31 
 
 plane X is and AL of plane X is 1, then plane X is 
 assigned as the intermediate storage plane. 
 
 iii) Find the top of the push down stack. The calling sequence 
 of this routine is: 
 
 CALL PN (NO); where NO is the number of plane which is the 
 top of the stack. For a plane whose status register is 1, 
 and the contents of its AAR equals the stack-depth counter 
 (SDC), then that plane is the top of the stack and the 
 plane number is put in NO. 
 
 iv) Find the next-to-top of the push-down stack. The calling 
 sequence of this routine is: 
 
 CALL PNl(Nl); where Nl is the plane number of the plane 
 which is next-to-top of the stack. The plane that is next 
 to the top of the stack is the plane whose Status Register 
 (SR) is 1 and whose AAR equals the contents of SDC minus one, 
 
 v) Push Down Stack Routine: 
 
 (1) PDS-IN: Input routine 
 
 First select the intermediate storage plane by calling 
 PX(X). Then set SR(X) to 1, and load AAR(X) and SDC 
 with the contents of SDC plus one. 
 
 (2) PDS-N0T: Complement Routine 
 
 First select the intermediate storage plane 'X' and 
 find the top of the stack; NO: Then set the proper 
 control signals in IASIM (Control byte = '01010010', 
 PR = NO, GN = '100000000' and PW = X) to load the 
 complement of the contents of plane NO into plane X 
 (P(X) = P(N0)). Finally, set SR(X) = 1, SR(N0) = 
 and load the contents of SDC into ARR(X). 
 
32 
 
 (3) PDS-0R: 0R subroutine 
 
 First select the intermediate storage plane 'X' , then 
 find the top of the stack 'NO' and next to top of 
 stack 'Nl'. Then set the proper control signals 
 and call IASIM to perform P(X) = P(NO)|p(Nl). 
 Finally set SR(NO) = SR(nI) = 0, SR(X) = 1, and 
 load AAR(X), SDC with the contents of SDC minus one. 
 The control signals are: 
 
 Control byte = '10000010'; PR = NO, Nl; GN = '100000000'; 
 PW = X. 
 (U) PDS-AND: AND subroutine 
 
 First select the intermediate storage plane 'X' , then 
 find the top of the stack 'NO' and the next to top of 
 'Nl'. Then by set the proper control signals and 
 call IASIM to perform P(X) = P(N0) & P(Nl). Finally 
 set SR(N0) = SR(N1) = 0, SR(X) = 1 and load AAR(X) 
 and SDC with the contents of SDC minus one. The 
 control signals are: Control byte = '00010010'; 
 PR = NO, Nl; GN = '10000000'; and PW = X. 
 vi) Move the top cell of PDS to the final plane A. The calling 
 sequence of this routine is: 
 CALL PDS-T0-A. 
 
 This routine is used to move the contents of plane A to the 
 location at PAR by setting the proper control signal and 
 calling IASIM to perform C(PAR) = C(A). The control 
 signals are: Control byte = '11010010'; PR = A; GN = '100000000'; 
 and PW = PAR. 
 
33 
 
 
 AL(I)=IR t in 
 1 + 10 
 
 
 
 
 I =0, 7 
 
 
 
 1 
 
 ' 
 
 
 
 f 
 
 READ IN 
 
 
 
 AUXX 
 
 
 
 < 
 
 ' 
 
 
 
 AR = AUXX 
 
 
 a = AR, 
 
 
 £ =AR 2 
 
 
 y =ar 3 
 
 
 AODR = AR4-7 
 
 
 1 
 
 r 
 
 
 TURE(I)=AR I+7 
 
 
 I = 0,1, ... 8 
 
 
 1 
 
 1 
 
 
 C0MP(I) =AR X+16 
 
 
 ■ I =0,1, ... 8 
 
 
 
 ' 
 
 r 
 
 fa 
 
 SDC = 000 
 SR(*) = b' 
 AAR(«)= 'O' 
 
 m 
 
 <^D 
 
 ERRI = 
 T =C= 
 
 1=0 
 
 1=1+1 
 
 LED 
 
 T = I 
 
 C = I 
 
 BOOLE Control Flowchart 
 
3h 
 
 1=1 + 1 * 
 
 PRINT 
 
 ERR0R I 
 
 MESSAGE 
 
 ERR2=0 
 
 1 = 
 
 PRINT 
 ERR0R 2 
 MESSAGE 
 
 PAR = ADDR 
 
 T0 = TZ = DG| 
 = GN(-I ) = 
 
 Z0 = IC = I 
 
 PR(») = PW(») 
 » 
 
 PX(X) 
 
 NPdUT(*) = 
 NP0UT(PAR) = I 
 
 - C¥0 
 
 <5D 
 
 — K .^^V- ) 
 
 ANP-Y 
 3 
 
 BOOLE Control Flowchart (Continued) 
 
35 
 
 ( *^ ) 
 
 C5D 
 
 GzD 
 
 BOOLE Control Flowchart (Continued) 
 
36 
 
 c5d 
 
 0P(O)= AR,_3 
 YC(0)= AR 4 
 0P(l) = AR 5 _ 7 
 YC(I) = AR e 
 
 <s 
 
 N = 0P(S), 
 L =0P(S). 
 P =0P(S), 
 
 PRINT 
 -»| ERR0R 3 
 MESSAGE 
 
 BOOLE Control Flowchart (Continued) 
 
f SEMIC0L ) 
 
 
 AR = AUXX 
 
 
 1 
 
 i 
 
 a ■ 
 
 : AR, 
 
 $ 
 
 = AR a 
 
 y 
 
 = AR 3 
 
 AOOR 
 
 = AR 4 . 7 
 
 I 
 
 TURE(I) = AR I+7 
 
 1=0,1, ... 8 
 
 C0MP(I) = AR I + |6 
 1 = 0,1, ... 8 
 
 CSD 
 
 C5D 
 
 37 
 
 @ 
 
 1=0 
 
 a = r 
 
 i=i + i 
 
 PAR = P(S) 
 
 (ID 
 
 PDS-T0- A 
 
 J 
 
 TIMER 
 
 BOOLE Control Flowchart (Continued) 
 
38 
 
 Auxiliary Routines 
 
 1. Name: PNT0UT 
 
 2. Functional Description: 
 
 This routine is used to print the contents of some or all 
 planes of the Iterative Array(lA). The plane number (-l(M) to 7) is 
 printed and the contents of ihe plane (not including border) is 
 printed as a 32 x 32 matrix, each element is a bit. 
 
 3. Formal Calling Sequence: 
 CALL PNT0UT (PLANE) 
 
 k. Formal Parameter Description: 
 k.l Input Parameter: 
 
 PLANE: An unpacked array of 9 elements, each 1 bit whose 
 subscript range is -1 to 7- This array is used to 
 indicate which plane(s) are to be printed out. 
 The corresponding elements in PLANE are set to 
 1, otherwise set to 0. 
 
 U.2 Output Parameter: None 
 
 5. Implicit Parameter Description: 
 
 The Iterative Array (IA) is not passed as parameters, but 
 is declared as EXTERNAL variables, thus its contents are available 
 for this routine. IA remains unchanged. 
 
 6. Subroutines Used: None 
 
 7- Operational Description: 
 7.1 English Text 
 
 Each element of PLANE will be examined; if that element 
 is set to 1, the contents of that plane will be printed out 
 as a 32 x 32 matrix. This process continues until all 
 planes have been examined. 
 
39 
 
 7.2 Flow Chart 
 
 The flow chart is attached. 
 
 The symbols used in the flow chart are: 
 
 PLANER: N = -1 to 7, PLANE(N) = 1 means the 
 
 contents of the Nth plane is to be printed 
 
 out. 
 I, J: Temporary counter 
 NPLANE: Plane number 
 IA(M,N,*): Nth row of plane M of the Iterative Array 
 
 8. Error Condition: none 
 
 ii) TIMER: This routine is used to read the internal real-time clock 
 of the IBM 360/75 computer and print out the time in the form 
 HH.MM.SS.TTT, where H stands for hour, M for minute, S for second 
 and T for micro-second. 
 
 The calling sequence is 
 
 CALL TIMER 
 
(pNT0UT J 
 
 ko 
 
 I = -I 
 
 1=1+1 
 
 NPLANE = I 
 
 PRINT 
 NPLANE 
 
 J = 
 
 PRINT 
 J,IA(NPLANE,J,*) 
 
 J = J+ I 
 
 PNTOUT Flowchart 
 
1*1 
 
 How to Use the Simulator 
 
 i) The execution of the simulator 
 
 Iterative Array, Transfer Memory, B00LE and all the auxiliary 
 routines are written as external procedures in PL/1. 
 
 A driver program with the attribute 'OPTI0N (MAIN)' (in PL/l) 
 is required in order to use the simulator. The driver program may be 
 either a simple test program to test one or more of the routines mentioned 
 previously or the driver may be a simulated TP. 
 
 To write a driver (main) program, the only thing that has to be 
 remembered is that all the variables which are declared as External in any 
 of the subroutines directly or indirectly called by the Driver Program, 
 must be declared in the main program in exactly the same form as in the 
 subprogram. 
 
 Following is an example of a driver program: TESTIA, which is used 
 to test the Iterative Array (IASIM). 
 
 A simple flow chart is attached. 
 
 (1) At point [l] , this program is defined to be a main program, 
 (with the statement TESTIA: PROCEDURE OPTIONS (MAIN)) 
 
 (2) At point [2], all external variables declared in IASIM declared 
 in exactly the same form (See IASIM program for detail). 
 
 (3) At point [3], the initial contents of some planes must be set up, 
 N is the number of planes to be set up. 
 
 For each plane, first read in the plane number (NPLANE), then 
 read in 102*+ bits arranged as a 32 x 32 matrix. 
 
 {h) At point [h], any valid combination of control byte, PR(plane 
 read select), GN (gate neighbor), and PW(plane write select) 
 can be read in and IASIM may be called to perform the proper 
 function. 
 
1*2 
 
 For the purpose of debugging, the contents of some planes may- 
 be printed out. PIN and P0UT are both unpacked arrays with 
 subscripts ranging from -1 to 7, (plane M to plane 7) s each 
 element is one bit; 1 means that the plane is to be printed 
 out, means skip printing of that plane. PIN is a list of 
 planes to be printed before the execution IASIM, P0UT is a 
 bit of planes to be printed after the execution of IASIM. 
 The routine PNT0UT with PIN and/or P0UT as parameters is 
 used to print out the contents of IA. 
 
 (5) The set up of data is dependent on the format used in the 
 TESTIA program. 
 
DECLARE THIS 
 PROGRAM 
 
 AS A MAIN 
 PROGRAM 
 
 I 
 
 DECLARE ALL 
 
 EXTERNAL 
 VARIABLES AS 
 IN IASIM 
 
 m 
 
 READ IN 
 N 
 
 I 
 
 I = 
 
 READ IN 
 NPLANE 
 
 READ IN 
 THE CONTENTS 
 
 OF PLANE 
 NPLANE AS 
 32 x 32 
 MATRIX 
 
 *t"*- 
 
 B 
 
 READ IN 
 CONTROL BYTE, 
 PR, GN, PW 
 
 READ IN 
 PIN(I) 
 I=-l to 7 
 
 READ IN 
 P0UT(I) 
 I = -I to 7 
 
 PNTJ0UT 
 (PIN ) 
 
 IASIM 
 
 PNT0UT 
 (P0UT) 
 
 k-i 
 
 Flowchart of Sample Main Program 
 
1+1* 
 
 ii)' Program Deck Set Up 
 
 a) Assume all programs are in object deck 
 ID Card 
 
 // EXEC LKG0PL1 (optional parameters) 
 // LKED.SYSIN DD * 
 
 All Object Decks 
 
 / * 
 
 // G0.SYSIN DD * 
 
 Data Deck 
 
 / * 
 
 b) Some programs in source decks (such as Driver Program) and some 
 in Object Decks 
 
 ID Card 
 
 // EXEC PL1 
 
 //PL1.SYSIN DD * 
 
 Source Deck of 
 One Program 
 
 Repeat as many source 
 programs as needed 
 
 / * 
 
 // EXEC LKG0PL1 
 // LKED.SYSIN DD * 
 
 All Object Decks 
 
 / * 
 //G0.SYSIN 
 
 DD * 
 
 Data Deck 
 
 / * 
 
U5 
 
 c) All object decks are on Disk. 
 
 It is important that only one main program can be involved for 
 
 one DSNAME, 
 
 ID Card 
 
 // EXEC LKG0PL1 (optional PARM) 
 
 // LKED.SYSLIB DD DSNAME=SYS1.PL1LIB,DISP=0LD 
 
 DD DSNAME=USER.Pll42.ILLIAC3, PAU 
 
 DISP=(0LD,KEEP) 
 
 // LKED.SYSIN DD * 
 INCLUDE ( ) 
 
 name of the routines including the name of the 
 main program. 
 ENTRY IHENTRY 
 
 / * 
 
 //G0.SYSIN DD * 
 
 Data Deck 
 
 / * 
 
 d) To add new object decks to disk or replace old object decks on 
 disk 
 
 ID Card 
 
 // EXEC LKEDPL1 (optional PARM) 
 //LKED.SYSLM0D DD DSNAME=USER . Plll+2 . ILLIAC3.PAU, 
 UNIT=DISK 5 V0LUME=SER=UIDCS3 
 SPACE=(TRK, (1*0,10,10) ), DISP=(0LD, KEEP) 
 // LKED.SYSIN DD * 
 
 Object Deck as many object decks as needed 
 NAME XXXX(R) where XXXX is the name of that object deck. 
 / * 
 
s 
 
'% 
 
 '■:■:. 
 
 
 
H