a I B R.AR.Y OF THE, U N IVERS'ITY Of ILLINOIS The person charging this material is re- sponsible for its return on or before the Latest Date stamped below. Theft, mutilation and underlining of books are reasons for disciplinary action and may result in dismissal from the University. UNIVERSITY OF ILLINOIS LIBRARY AT URBANA-CHAMPAIGN AU - 9 4 **0 4 JSE OlSfLV 1982 L16L— O-1096 Digitized by the Internet Archive in 2013 http://archive.org/details/multivibratortri202watt tU0^\sV\ Report No. 202 M2B m6 MULTIVIBRATOR TRIGGERING REQUIREMENTS by Walter John Wattman April 15, 1966 Report No. 202 MULTIVIBRATOR TRIGGERING REQUIREMENTS* by Walter John Wattman April 15, 1966 Department of Computer Science University of Illinois Urbana, Illinois This work was submitted in partial fulfillment of the requirements for the degree of Master of Science in Electrical Engineering, April, 1966, ACKNOWLEDGMENT The author wishes to thank Professor T. A.Murrell for his guidance and counciling during the research phase of this paper and for his suggestions and proofreading during the writing phase. The fine work of the staff of the Department of Computer Science in preparing the figures and typing the manuscript is also appreciated. -in- TABLE OF CONTENTS Page 1. INTRODUCTION 1 2. SLOW DC TRIGGERING 3 3. FAST DC TRIGGERING 10 k. FAST AC TRIGGERING 17 -IV- 1 . INTRODUCTION The basic concept in switching circuitry is that of a discrete change of state. Two states are considered in transistor switching circuitry, the ON state and the OFF state. In saturated switching circuits, the ON state is marked by a very low collector to emitter voltage and a relatively large collector current, while the OFF state is marked by a relatively high collector to emitter voltage and a very small collector current . The selection of component values and supply voltages which allow this change of state is called the "dc design procedure." The dc design procedure may also provide for the optimization of the circuit with respect to such quantities as available output power and power drain. A worst case design analysis is one which takes into account the maximum variation of each supply voltage and component value. Each performance property (cut-off voltage, required H^-,* etc.) is examined in turn, assuming that in each case the most unfavorable combination of tolerance swings for that property will occur. The sensitivity of circuit performance to normal variations in transistor and component parameters makes the use of such an analysis mandatory if reliable circuits are to be designed. Worst case dc design procedures do not always guarantee proper transient operation of a bistable circuit. In order for the circuit to be useful the designer must be able to reliably predict conditions which are sufficient to cause a state transition. That is, the designer needs the capability of specifying the characteristics of those triggering signals which will always cause transition and of those which will never cause transition. The problem may be further complicated by the requirement that the transition occur within a specified time interval. -1- -2- The object of this investigation is to provide a scheme for the worst case analysis of the triggering requirements of saturated transistor circuitry. The circuit configuration to be considered is that of a standard bistable multivibrator, or flipflop, employing base triggering of the ON transistor. The treatment is divided into three parts : slow dc coupled triggering, fast dc coupled triggering, and fast ac coupled triggering. Conclusions reached in the third part apply equally well to a monostable, or one-shot, multivibrator. 2. SLOW DC TRIGGERING When triggering a multivibrator with a dc coupled step, AU(t), there is only one question which needs to be answered. Namely: how large must the magnitude of A be to insure that a state transition occur? Figure 2.1 is the circuit of a flipflop which has been simplified by removing the trigger steering networks and the speed-up capacitors in the base-collector coupling networks. During transition this circuit is unstable, a condition which exists until currents are limited by the non- linearities of the transistor saturation and/or cut-off. The circuit requirements sufficient to sustain this instability may be placed in evidence in the following manner. Assume that at time t, t < 0, Q is ON. Apply a voltage step AU(t) to terminal T of Figure 2.1, where A is large enough to cause transition. Then for t > 0, but before limiting takes place, both Q and Q_ are active. During this instability the volt-ampere charac- tistics which the circuit presents to the coupling resistor, R , must represent a negative resistance. Referring to Figure 2.2, let Q and Q have common emitter forward current transfer ratios of li-,™-, and H^^p respectively. The node equation representation of the circuit of Figure 2.2 is V - V ^El Z bl = \^ ' 1 2 ' X V. - V V. - V ij t _ __i ££. , _Z - p 2 FE2 b2 " R^ R^ GC CC Figure 2.1 Multivibrator Circuit O V, cc CC Figure 2.2 Circuit for Calculation of dv/di -5- 1 bb 1 1 4 I, , + — ~ + "bl R h Rn R 2.3 3 J b2 + C = X 2.4 V 2 - V 3 + v 2.5 Noting that V. and V are constant (because of forward biased base-emitter junctions), taking differentials, and solving for the resistance characteristic gives dv di TT = R, H 1 - "h FE1 TE2 R 3 R + X R 2 2.6 which when combined with the restraint for negative resistance di 2.7 gives HL ■V FE1 TE2 R > r- 1 + 1 2.8 -6- as a condition for instability. With the result of Eq. 2.8 it is worthwhile to examine the transition process more carefully. For discussion purposes let a ramp voltage B(t) = btu(t) 2.9 where b is small, be applied to terminal T of Figure 2.1. At time t, t < 0, let Q be ON and Q be OFF. The following terms may be defined: I = the quiescent base current, t < I, , - the base current which will just cause saturation blsat ° I , = the quiescent collector current, t < clq I (t) - the trigger current where 1 i clq "blsat - H FE1 2.10 and in general blq blsat Voltage V is held constant by the forward biased base-emitter junction of Q and since Q is cut off it follows that v 1 - V X R3 = V^f = C ° nstant 2 ' 12 V - V I , = — = constant 2.13 ni n. -7- btu(t) - V hi™ = hl q Rj i 2 ' U I,,(t) is decreasing with time, therefore there exists some time t, , bl 1' t > 0, such that For time greater than t.. , I ,_ (t) is no longer great enough to maintain Q, in saturation and hence I n (t) becomes a function of I, , (t) 1 cl bl y*) " "fei hi^' l > *i 2 ' 16 Voltages V p (t) and V (t) are given by R, I .(t) +--J* v 6 cl v ' R_ + R 7 cc V 2 (t) = 2 — -I , t > t x 2.17 1 - R 5+ R ? V bb R 7 + V 2 (t) R S v 3 (t) ' ^ + P 7 1 > 4>t l 2 - 18 and are also decreasing functions of time. There exists some time t , t > t , such that V (t ) will be low enough to forward bias the base- emitter junction of Q . This occurs when W = V BE20 N 2 - 19 -8- Since t > t , Q is in its linear range and IL_, is high, say "rai " 10 2 - 20 For practical circuits R 3 ^ < 19 2.21 R 2 and hence Eq. 2.8 implies that a sufficient condition to insure regeneration is ^F- ^E2 In practice this condition is met at virtually the time when Q starts to conduct. Making use of Eqs . 2.9, 2.1^, and 2.l6, the voltage at the trigger point at time t can be expressed as : B R U blq H^ Reasonable circuit design demands that I n (t^) be less than the saturation cl 2 value, but somewhat greater than zero, or: I . > I _(tj > 2.25 clq cl 2 -9- By making use of Eqs. 2.17, 2.18, and 2.19, I i (^p) can ^ e expressed as WV ■ V. BE2on R 5 R 6 - V. bb r r 6 +r t - R 5 R 6 v cc 2.26 Aside from the value of V^^ , which changes little from one BE2on transistor to another, the value of I nC^p) is controlled by the circuit design, i.e., the proper choice of R , R,-, R , V , and V Equations 2.2^- and 2.25 indicate that the required trigger current is less than the quiescent base current, the difference being the quantity I (t )/H_,, . Equation 2.26 shows that I ,(t p ) is fixed by external circuitry, but the influence of H is imposed by the transistor. For very large Hp^, Lim I, = L . t blq ^El^ 2.27 and it can be concluded that as H™, increases, the required trigger current increases, but that it is bounded by an upper limit, the quiescent base current. 3. FAST DC TRIGGERING It has been shown in Part 2 of this report that a trigger current pulse with a magnitude equal to the magnitude of the quiescent base current is sufficient to insure a state transition in the circuit configuration detailed in Figure 2.1. However, this does not convey any information about the propagation time of the pulse through the circuit. That is, the circuit does not switch in zero time after the trigger exceeds the threshold level. Referring to Figure 3-l> "the following terms are defined: T = storage time, the elapsed time between the application of s I U(t) and a ten per cent change in the collector voltage, V (seconds X 10" ) T = transition time, the elapsed time between a ten per cent change and a 90 per cent change in the collector voltage, V (seconds x 10 ) = quiescent base current, t < (amperes X 10 ) = quiescent collector current, t < (amperes X 10 ) = normalized trigger current (amperes X 10 ) V I cq C(T ) = normalized charge, the charge necessary to cause a ten per cent change in the collector voltage, V , at time t = T (coulombs x 10"^) s where the following relations hold P = -r~-r 3-1 ■10- -11- T C(T ) = / P dy = P T 3.2 A group of transistors was selected for high and low E™ from several different lots totaling a few hundred. Thus in one sense the components represented the best and the worst of a particular type. The circuit of Figure 3-1 was used and the following data was taken in an attempt to place in evidence the factors which determine T . Figure 3-2 is a plot of C(T ) with 1,1,, and V held constant, for the best s cq bq cc transistor, TR , and the worst transistor, TR P « The C characteristics of the remaining transistors fell between those of TR and TRp. From Eq. 3*2 it is seen that in general C(T ) p = -y*- 3-3 s and that curves of constant P in Figure 3*2 will be straight lines passing through the origin with slope P. The value of P for any of these lines can be read directly by noting that at T = 1, P = C(l). The intersection s of a line of constant P and the C characteristic of a particular transistor yields the storage time of that transistor for that value of P. It is clear that as P approaches unity, the intersection becomes less well defined and T increases greatly. 2N3638's manufactured by Fairchild. ■12- CC Figure 3-1 Test Circuit f or C (T ) s 0.5 2.5 T (seconds x 10 ) s Figure 3-2 C Characteristics for TR-^ and TR 2 . ■13- T 2 o H X ra 1 § 1 o O I bq = l.Oiria >Vcc - 20 -10.7 5.^ a c 9-9 b J I I I 0.5 1.0 1.5 2.0 2.5 T (seconds x 10" ) a Figure 3*3 C Characteristic Variations ON I o X o r-i o l o En J L a,c V = 2 - 0ma I \cc cq\ - 20 -10.7 5-4 a c 9-9 b 0.5 1.0 1.5 2.0 2.5 T (seconds x 10 ) s Figure 3-^ C Characteristic Variations -14- The variation of the C characteristics as a function of V , cc I , and I was investigated and the data is summarized in Figures 3-3 cq bq and 3.4. These figures indicate that the C characteristic of a given transistor is relatively constant with respect to a two-to-one change in V ,1 , or I . Relatively constant is taken to mean that the cc cq bq described variation is less than the variation occuring within a population of transistors as displayed in Figure 3-2. In view of the supporting information indicating that the C characteristics are constant over some specified operating range it is reasonable to return to Figure 3-2 and establish a design line, DL ; which will be taken to represent the worst case transistor over the operating range. Choosing the design line to be linear in T , it must satisfy the equation C(T ) = a + b T 3.4 s s where for the design line in Figure 3*2 -9 -3 a = 0.5 X 10 coulomb; b = 0.9 X 10 amperes. 3-5 Combining Eq. 3-2 and 3-^ gives T s P dy = a + b T 3-6 s -15- Performing the integration and solving for P as a function of T yields s the worst case value of P, P . . mm P . = fr + b 3-7 min T u s Figure 3«5 is a plot of equation 3«T« Since switching will always occur for P > 1, as shown in Part 2, the curves of Figure 3*5 can be used to find the value of P required to guarantee that the storage time does not exceed some maximum value, T . An order of magnitude estimate for the s transition time, T , is T^ = T . 3.8 t s J 3-0 -16- I o 2.0 X co 1, is not sufficient to insure that the transistor will become cut off. If the trigger current is decreasing too quickly, it will permit the transistor to fall back into saturation without ever having reached the cut-off state. This means that there is a possibility that in a bistable circuit such as that of Figure 2.1, V (t) would not decrease enough to forward bias Q and initiate regeneration. Some provision must be made to insure that Q will actually cut off. Let the normalized trigger current be given by Eq. 4.1 and the circuit configuration be that of Figure 3«1« F° r a fixed g, there exists some minimum value of P, P . , which will drive the transistor into the nn cut-off region. With each pair (P . , g) there is associated a time T min c equal to the time the transistor enters the cut-off region. The relation- ship is P • exp(-gT ) = 1 4.5 mm c which follows from the fact that as the transistor approaches cut-off, I (t) approaches zero and that prior to cut off V is nearly constant Measured values of P . exp(-gT ) ranged from 0.99 to 1.07. Similar mm c reasoning leads to a reformulation of Eq. 4.5 as P exp(-g T ) = 1 4.6 ^ °max c -20- Where g is the maximum value of g for a fixed P which will permit the max transistor to be driven into the cut-off region. It is apparent that if one could find a functional relationship between two of P, g, and T , then specifying one would determine the other two. Data was taken relating l/g and T for TR and TR and is presented in Figure h.?>. From this figure it is possible to choose a design line, DL , which is taken to represent the transistor over the operating range. The equation of DL was chosen to be T = 2.0 x 10" sec. + i- . h.l c og Solving Eq. h.^ } with the left member equated to 1.1 for safety, and Eq. k.7 for P . as a function of l/g gives mm P . = 1.1 exp mm 2 1 k.Q A curve displaying the relationship of Eq. ^.8 is presented in Figure h.k along with experimental data for TR, and TR p . Lim P . =1.1 exp(0.125) = 1.25 k.9 _ mm v g->0 Equation k.Q predicts that for g = 0, the minimum value of P . which will D ; mm insure that the transistor enters the cut-off region is 1.25- This is contrary to the value of 1.0 predicted in Part 3 of this report, and indicates that the model may be overly pessimistic for small values of g. -21- i o a o o 0) 3-0 2.0 1.0 bq K = 2 bq TR X a b TR 2 c d 12 16 l/g (seconds x 10 ) 20 i O H X to o o (U co H 15 10 Figure 4.3 Cut-off Time as a function of the Trigger Current Time Constant. — bq K = 2 bq TR a b TR o c d e Theoretical Worst Case 0.5 1.0 P . (amperes x 10 mm Figure k.h Minimum Normalized Pulse Current as a Function of the Trigger Current Time Constant. -22- Figure 4.5 is a modification of Figure 4.1 which incorporates Eq. 4.8 as a constraint. For a given trigger current time constant, l/g, Figure 4.5 presents those values of normalized trigger current, P, which assure that the transistor will enter the cut-off region. In addition, Figure 4.5 places a maximum value on the storage time, T . In summary, Figure 4.4 is the most useful of the curves. It indicates that if P, the ratio of the trigger current to the worst case quiescent base current, equals 1.5* then the trigger current time constant, / -6 l/g, should be at least 10 x 10 seconds. Increasing P to 2.0 permits -6 a decrease in the time constant to 4 x 10 seconds. If P is less than 1.5, a very large time constant is called for, while if P is greater than 2.0 a small increase in the time constant will permit a large reduction in P. It thus appears that 1.5 < P < 2.0 is a reasonable design target. Over this range the time constant can be represented by: l/g = 28 - 12 P seconds X 10" , 1.5 < P < 2.0 4.10 ■23- 3-0 2.0 o e i.o CD cc5 PM Design Limit I I I I I 0.5 1.0 1.5 2.0 2.5 T (seconds X 10" ) s Figure 4.5 Normalized Trigger Current as a Function of T and s