1 I B R.AR.Y 
 
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 Of ILLINOIS 
 
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Digitized by the Internet Archive 
 
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 http://archive.org/details/performancechara152yama 
 
pio. 84 
 
 X L G ~T DIGITAL COMPUTER LABORATORY 
 
 KC 152, UNIVERSITY OF ILLINOIS 
 
 C °P ^ URBANA, ILLINOIS 
 
 REPORT NO„ 152 
 
 PERFORMANCE CHARACTERISTICS OF FAST LOGIC FOR ILLIAC III: 
 BASIC NAND AND NOR CIRCUITS 
 
 by 
 Shigeharu Yamada 
 
 September 18, 1963 
 
 
 This work was supported in part Toy the 
 
 Atomic Energy Commission 
 
 under Contract No, AT ( 11-1 )-10l8 
 
1. GENERAL ASPECTS 
 
 For the basic logic circuit of the computer, many possible circuit 
 configurations giving 15 mc to 20 mc operation, could be proposed . For instance, 
 nonsaturated current-steering logic, or again, conventional saturated transistor 
 diode logic with a selection of diode, resistance, or capacitance resistance 
 coupling could be used. That is, the critical speed range of 10 mc to 20 mc 
 can be accomplished either by saturated or low-level unsaturated transistor 
 circuitry o 
 
 From the standpoint of economy, saturated logic circuitry is cheaper, 
 simpler and also more stable in the presence of noise and supply voltage 
 variations, However, to overcome the storage delay of saturated logic, we must 
 sacrifice some logical gain; this disadvantage can be minimized by the use of a 
 transistor with a controlled storage time and by proper circuit design. For 
 example the silicon transistor 2N23&9 is one device particularly well suited to 
 saturated logic Using this transistor with highspeed switching diodes, we can 
 expect a propagation delay of less than 20 nsec per stage of logic. 
 
 From the standpoint of circuit performance, the NAND circuit is prefer- 
 able (for silicon devices). Reasons include: 
 
 1. All output stages from one preceding stage are independent 
 for the NAND, but not independent for the NOR. 
 
 2. Voltage characteristics of the level-shifting diodes, 
 particularly those connected to the same input, must 
 be more uniform in the NOR circuit. 
 
 3. In the NAND circuit, fanout with a specified propagation 
 delay is limited mainly by the amount of parasitic 
 capacitance; but in the NOR circuit, both by capacitances 
 and by I . 
 
 k, For the NAND, propagation delay is relatively independent 
 of the number of fanouts if capacitance is kept small and 
 the circuit designed properly. This results from the 
 small turn-on time variation with the number of fanouts 
 and the fast turn-off characteristics of the NAND circuit. 
 
 1 
 
 See Appendix B. 
 
 -1- 
 
1 
 
 The short turn-on time is a result of speed compensation 
 of the transistor characteristics by means of the 
 
 dh FE 
 
 > 
 
 for I in the range of 10 ma to kO ma. 
 
 5o From the point of view of gate driver applications^ the 
 RAND gate driver is superior both in signal quality and 
 power consumption„ 
 
 These features have been investigated in the experiment report below 
 
 See Appendix A. 
 
2. THE NOISE PROBLEM 
 
 The noise problem is different for the NAND and the NOR circuit. 
 Logic noise (spikes) which can disturb the logic operation of the circuit in 
 the following situations : 
 
 (a) NOR 
 
 (b ) NAND 
 
 Figure 1 
 
 V + V - V 
 
 BES DS D 
 
 Signal Input 
 of T ? 
 
 Figure 2 
 
 -3- 
 
Allowable maximum slow noise signal V. t/ \ of NAND circuit is 
 
 N(max) 
 
 V'max) = V CL " < V BE(sat) + V DS " V f 2 " 1 ' 
 
 and that of NOR circuit is given by 
 
 V N(max) = V BE(sat) + V DS + V D " V CE(sat) (2o2) 
 
 Here subscript "D" designates the logic diode,, ,! DS" the level-shifting diode; 
 and conventional transistor subscripts will be used throughout o 
 
 For high-frequency noise., the input circuit transfer function of the 
 NAND circuit (Fig. 3 ) is approximated by the following equation; 
 
 2 2 
 
 p ~ r cVb 
 
 (1 + P-C D E C )[1 + pC D (r DS + r B )] < 2 ^ 
 
 (nonclamped case) 
 
 where 
 
 r = ac resistance of level- shifting diode in the conducting 
 
 Do 
 
 region 
 
 r = ac-base resistance of the transistor in the conducting 
 region 
 
 CL = logic diode junction capacitance 
 R = collector load resistance 
 
 p = Laplace transform frequency operator 
 
 For the clamped case^ capacitance of the leAAel- shifting diode and 
 equivalent capacitance of the base contribute very little : 
 
 2 ? 
 
 p r n C TY r K 
 
 (2.4) 
 
 1 + p( V r DS + V 
 
 (clamped case) 
 
+12 +6 
 
 2N2369 
 
 (a) NAND 
 
 (b) NOR 
 
 Figure 3 
 
 Here r is the ac resistance of the clamping diode in the conducting region. 
 
 Therefore r is very small » The clamping diode is very important in decreasing 
 
 noise. A small margin for noise will be assigned for V^,- •. in the design, 
 
 BE (sat) 
 
 The NOP circuit is designed with an eye for turn-off speed to give 
 
 logic and level shifting diode disconnection when T is in the off state (see 
 
 Fig= 3)= Therefore the transfer equation is given by 
 
 * R B r C C D C 
 1 + R B pC 
 
 (2.5) 
 
 where 
 
 resultant capacitance of the logic diode and level-shifting 
 diode 
 
 «B 
 
 base bias resistance 
 
 OV 
 CE 
 
 -yr— at the designated I value » This value is roughly equal 
 C 
 
 to twice r 
 
 D 
 
The noise transfer equation is of the same form as in the clamped 
 
 NAND circuit, but r , B- are greater than r , r „ Therefore, logic noise in 
 
 C B OL b 
 
 the NOR circuit can be expected to be somewhat greater than noise in the NAND 
 circuit . 
 
 For an npn silicon transistor, the positive NAND logic circuit is 
 preferable to the NOR circuit. In some cases, for instance, for a decoder the 
 NOR circuit is more economical . Consequently some NAND circuits can have NOR 
 circuit loads, and some NOR circuits can have NAND circuit loads. Actually the 
 collector clamping diode is not necessary in the NOR circuit, if the load is 
 always a NOR circuit, but when the load contains a NAND circuit, the clamping 
 diode of the NOR circuit increases circuit speed and decreases noise in the 
 following NAND circuit . For this reason the basic NOP circuit has a collector 
 clamping diode as does the NAND circuit . 
 
 In this report the performance characteristics of the basic logic 
 circuits are reported with test data taken from prototype printed-circuit boards 
 Design and operating speed consideration are given in the two appendices . In 
 high-speed operation, the printed-circuit board is as important as the design 
 of the circuit as is the. parameter specification of the transistor . 
 
3» BASIC PERFORMANCE CHARACTERISTICS 
 
 The basic characteristics of the circuit in Figs . 3a and 3h are shown 
 in Figs. ka. and Vb and Figs. 5a and 5b respectively. 
 
 Figure k shows the dc operating range, and Fig. 5 shows the basic 
 speed data. Data in Figs, k and 5 were not taken from a circuit on a test 
 printed-circuit board but rather from a separately-fabricated circuit having no 
 f anout . 
 
 Figure 5 shows the effect of the capacitive feedback between collector 
 and base, and the effect of the output capacitance. These results provide a 
 reference point to discuss the performance of the circuit on the printed board 
 used for test purposes (see below). 
 
 Figure 6 shows the effect of the wiring on the board. The output 
 capacitance causes a slow turn-off time, but does not affect the turn-on time. 
 The negative feedback through collector-to-base capacitance slows down both 
 turn-on and turn-off speed. The coupling between collector and base conductors, 
 if they are long, must be watched carefully. Too much coupling here causes the 
 propagation delay to become too large. In the NAND circuit propagation delay 
 depends more upon turn-on speed than the turn-off speeds 
 
 Figure 7 shows the effect of the fanout on both turn-on and turn-off 
 time. When the number of fanouts is increased, output capacitance increases 
 linearly. 
 
 Therefore, turn-off time increases in direct proportion to the number 
 of fanouts, Turn-on time does not depend much on the number of fanouts but in 
 a properly designed circuit, turn-off time doesn't contribute to the propagation 
 delay. On the other hand, turn-on time contributes to the delay but when we 
 select the transistor to have the characteristics of 
 
 3T>° 
 
 C 
 
 as explained before, in the region of important range of I , turn-on time does 
 not change appreciably until the number of fanout reaches about ten. On the 
 
 IT" 
 
 "See Appendix 2. 
 
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 SWITCHING CHARACTERISTICS vs V cc 
 
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 -\ 
 
 NO FAN OUT 
 
 +4 
 
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 (d) 
 
 BASIC SWITCHING CHARACTERISTICS 
 
 4 
 
 FIGURE 4. 
 
11 
 
 (a) 10 nsec/div 
 
 t 10 nsec 
 on 
 
 (b) 10 nsec/div 
 
 3 pf added between 
 base and collector 
 
 (c) 10 nsec/div 
 
 t __ 11 nsec 
 off 
 
 (d) 10 nsec/div 
 5 pf added to 
 collector 
 
 Figure 5° Basic NAND, isolated fabrication 
 
 UNIVERSITY OF 
 ILLINOIS UBRARY 
 
12 
 
 (a) 
 
 (b) 
 
 Figure 6, Basic NAND. Same circuit as Fig. 5> 
 but fabricated on a printed-circuit 
 board. 
 
13 
 
 (a) t waveform with to 
 
 on 
 
 6 fanout., R = 1.1 K 
 
 (b ) t wavef orm with to 
 v on 
 
 6 fanout _, R = 5^0 ohms 
 
 (c) t ^ waveform with 
 off 
 
 to 6 fanout, R = 1.1 K, 
 with clamp 
 
 (a) 
 
 t _„ waveform with 
 off 
 
 to 6 fanout,, R = 560 ohms, 
 with clamp 
 
 Figure 7 
 
14 
 
 contrary, in the NOR circuit, delay depends more on the turn-off time, and 
 turn-off time increases directly proportional to the number of f anout . 
 
 Figure 8 shows the propagation delay versus fanout for both the NAND 
 and the NOR circuit. 
 
 V 
 cc 
 
 Figure 9 shows how propagation delay depends on the values of R and 
 
 Figure 10 shows how propagation delay varies with supply voltage 
 
15 
 
 (a) 
 
 NOR 
 
 FAN OUT 
 
 Q 
 
 O 
 
 »». 
 
 K 
 
 o 
 Q: 
 
 a 
 
 17 
 
 16 
 IS 
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 10 
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 / cc = + /2 
 
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 'a =~ 
 
 6 
 
 
 
 
 
 
 
 
 M 
 NAND 
 
 5 6 
 
 FAN OUT 
 
 Ts 
 
 •©-HD 
 
 <§) 
 
 7^ 
 
 'or 
 
 7qi *~ ^or _ PROPAGATION 
 
 Tin 
 
 DELAY 
 
 PROPAGATION DELAY VERSUS FAN OUT 
 
 FIGURE 8. 
 
16 
 
 G 
 O 
 
 •H 
 -P 
 
 oi 
 
 bD 
 d 
 ft 
 
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 13 
 11 
 
 R c - 560fi 
 
 fanout 
 1 fanout 
 
 1.1K 
 
 V = V 
 1 CL 
 
 +10 
 
 +12 
 Volts 
 
 +1+ 
 
 cc 
 
 Figure 9= Propagation delay as a function of V 
 
 CC 
 
17 
 
 -10 
 
 s 
 
 o 
 > 
 
 (volts ) 
 
 Figure 10 . Equal propagation delay- 
 locus of the NAND circuit 
 
4. COUPLING BETWEEN THE ADJACENT CIRCUITS ON THE SAME BOARD 
 
 A dense arrangement of parallel circuits on one board can result in 
 large intercircuit couplings This coupling cannot be neglected, as it is 
 sometimes more detrimental than the logic noise through diode capacitance „ 
 
 Coupling can be calculated as follows : 
 
 / C(x)v(x)dx 
 
 — j(x)V(x)dx i = noise current in base circuit 
 
 
 
 Figure 11 shows the data on the adjacent circuit coupling. By this 
 measurement, the equivalent coupling in the test boards is about 3 pf = If the 
 voltage on an adjacent collector changes at the rate of 2 v in 10 nsec, and 
 assuming 3 pf equivalent capacitance between base and adjacent collector, this 
 noise current can reach 0,6 ma. Therefore, to guarantee saturated operation at 
 low temperature (iw, =20) with a maximum fanout of 6, we must provide approxi- 
 mately 2 ma for L through the level-shifting diode (see Fig, 12 in Appendix A) 
 
 As explained in section 1, logic noise can be kept small if the 
 collector is clamped in the NAND circuit. 
 
 -18- 
 
19 
 
 Adjacent channel 
 collector wire 
 
 Off 
 
 20 nsec/div 
 2o5 v/div 
 
 (a) Adjacent channel coupling 
 
 (Equivalent capacit is 3 pf < 
 Minimum separation of the 
 two wires is 3/64"; average 
 separation is approximately 
 l/8" along l/2" length,) 
 
 00 
 
 Coupling 
 
 between open pin 
 
 J 
 
 
 Distance 
 
 8 
 10 
 
 J-8 
 
 2/l6" 
 
 J-10 
 
 5/l6" 
 
 L 
 
 J-L 
 
 5/16" 
 
 14 
 
 J-l4 
 
 15/l6" 
 
 R 
 
 J-R 
 
 15/16" 
 
 22 
 
 J-22 
 
 2-3/16" 
 
 
 20 nsec/div 
 2.5 v/div 
 
 Figure 11 
 
AFPENDLX A; WORST-CASE EQUILIBRIUM CONDITIONS 
 
 NAND and NOR circuit design under worst-case equilibrium conditions 
 is given here. To get an exact solution under worst-case conditions is very 
 difficult because of the intrinsic nonlinearity of the semiconductor devices. 
 We are unable to derive a straightforward solution, especially if the circuit 
 has a level-shifting diode. 
 
 We are concerned with a general-purpose circuit which will be used 
 for all logic stages without adjustment or compensation. Assuming a silicon 
 diode and silicon transistor logic circuit, the fan- in problem will be neglected 
 from the point of equilibrium equation. Henceforth, all transistor characteristics 
 used for numerical evaluation are those of the 2N23£>9.> a silicon planar epitaxial 
 transistor. Logic diode characteristics are those of the FD100, a diffused 
 silicon planar diode. 
 
 Table 1 shows the configuration for worst-case operation i M is the 
 number of fan- ins, N is the number of fanouts, and transistors T , T Q are as 
 shown in Fie. 12. 
 
 Table 1. Configurations for Worst-Case Operation 
 
 T off 
 
 N - 1 outputs; M - 1 inputs 
 are all reverse biased and 
 carry maximum leakage 
 current 
 
 T on 
 
 Lowest Temperature 
 
 NAND i T on 
 
 N - 1 outputs are forward 
 biased and carry maximum 
 toward current 
 
 M - 1 inputs are reverse 
 biased, maximum current 
 flow in T 
 
 T p off 
 
 Highest Temperature 
 
 T off 
 
 N - 1 outputs carry maximum | T on Lowest Temperature 
 forward current 
 
 M - 1 are reverse biased 
 
 NOR T -i on ' N - 1 outputs carry minimum j T off j Highest Temperature 
 t current 
 
 ' M - 1 inputs carry maximum 
 ■ current 
 
 T. on 
 
 I of T, is maximum 
 c 1 
 
 T„ on 
 
 -20- 
 
V, 
 
 21 
 
 «, > T i 
 
 cc CL 
 
 M - 1 < 
 
 cc CL 
 
 Figure 12, Configuration for worst-case operation 
 
 Figures 13 through l6 show how the transistor characteristics vary 
 
 with temperature. As can be seen from these figures, V decreases with 
 
 BE 
 
 increasing temperature, while V is not linear for variation of temperature . 
 
 CL 
 
 Also the diode knee voltage decreases with increasing temperature, 
 The equations of the equilibrium at low temperature are: 
 
 - 
 
 h: 
 
 \2-h- 
 
 \ - (V BE(satj + *DS> 
 
 F, 
 
 (A.l) 
 
 ^ " Hfe 
 
 (A.2) 
 
 \2 
 
 V / x + V 
 BE(sat) 2 
 
 F 
 
 B 
 
 (A. 3) 
 
22 
 
 M a 
 
 CBO 
 
 IOO 
 
 10 
 
 1.0 
 0.5 
 
 
 
 
 
 
 
 
 
 
 
 
 r 
 
 ZNZ 
 
 369 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 0.1 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 O 20 40 60 SO IOO IZO 140 
 TEMPERA TORE (• C) 
 
 TEMPERATURE DEPENDENCE 
 OF Icbo 
 FIGURE 13. 
 
 ma 
 
 2N2369 
 
 T = /00°C 
 
 O o.z 0.4 o.6 o.a i.o y 
 
 BE 
 
 I B vs. V BE AT 100° C. 
 FIGURE 14. 
 
 2N2.3€9 
 
 -15 O 25 50 IOO 
 
 TEMPERA TURE (°C) 
 
 TEMPERATURE DEPENDENCE 
 OF V BES 
 FIGURE 15. 
 
 -/SO 2.5 50 IOO 
 
 TEMPERATURE (" c) 
 
 TEMPERATURE DEPENDENCE 
 OF V CES 
 FIGURE 16. 
 
23 
 
 Leakage current of the FD100 at -15 C and at a reverse voltage of 50 volts is 
 only 13 na and at 100 C about 3 [±&° Therefore even at the highest temperature, 
 leakage current can be neglected- -even when the fanout is 10, 
 
 The above equations are combined as: 
 
 -1 " ^ V BE(sat) + V DS^ Z C V BE(sa t) + V 2 , . , , 
 i '- = - — + ■ > — -^ (A. 4) 
 
 \ ^FE ^B 
 
 Also where I in Eq. (A M) corresponds to the low temperature condition we must 
 have : 
 
 V - R 
 — cc 
 
 L_ > V + V / \ + V 
 CT3XS DS BE(sat) D 
 
 At high temperature for worst-case condition, T is on/ T is off. In 
 
 this case maximum 1^ and minimum L „ must guarantee the maximum V^^^o Therefore 
 
 2 b2 BEO 
 
 the equations are: 
 
 R B 
 
 2 1 -D R -D R -D 
 
 (A. 6) 
 
 These are combined to yield 
 
 — i — = \ \ Id ^ + CB0 
 
 Now, I in Eq<, {h*k) } is given by 
 
 c 
 
 I c = (H - 1)\ + -SS ^at) + (Ao8) 
 
2k 
 
 Temperature dependence of l nTir . is shown in Fig, 13 . From this, I ni3n is 3 ua 
 -O, 
 
 at 120 C. L in Eq. (Aj) is a function of 
 
 h = V V BE0 + ^DS " V CE(sat)'V 
 
 and I , I in Eq= (A. 8). (These correspond to low temperature.) 
 
 J D = V V BE0 + V DS - VsaO'V 
 
 V DS " ^ + P » V DS 
 
 ^DS " (1 " p)V DS 
 
 V„ - (1 + 1)V„ 
 
 V = ( 1 - Tl )v 
 
 -D v ' D 
 
 Here parameters p and t] designated admissible component variation, V„ Q and V_ 
 
 JJo JJ 
 
 are threshold voltage of the level-shifting diode and logic diode respectively 3 
 and also vary with temperature- For the FD100 V„ increases eight percent at 
 -15 C and decreasing 17 percent at +100 C. For the TI51 V increases ten 
 
 JJo 
 
 percent at -15 C and decreases 20 percent at +100 Co Therefore we can write 
 (introducing average values V and V ): 
 
 JJ JJo 
 V Dg = (1 + P)V DS (1 + 0.1) at -15°C 
 
 (1 + p)V Dg (l - 0.2) at +100°C 
 
 V DS = (1 - P)V DS (1 - 0.2) at +100°C 
 
 V = (1 - P)V (1 + 0.1) at -15°C 
 
 -DS v ^ ' DS 
 
25 
 
 V D = (1 + Tl)V (1 - 0.17) at +100°C 
 
 V D = (1 - n)V D (l + 0.08) at -15°C (A. 9) 
 
 For the NOR circuity the worst-case conditions are: 
 
 L C V BE(sat) + V B 
 
 h hl + h,2 h FE + R B < A - 10 > 
 
 ^CC " ^CEX + < N " »h + ^ + ^^^ + ^ C " ? BE(sat) + \ + \ S 
 
 (A.ll) 
 
 I is given when both T and T„ are on at low temperature by 
 
 - = CC -CE(sat) - 
 C R p DR 
 
 Here I is the reverse current of logic diode, I of the FD100 is again 
 DR DB 
 
 10 ua at 100 C. Therefore this current can be neglected when the number of 
 fanout does not exceed ten, 
 
 fnr-p thp unT-t;+-r , at;p onnHiti nn npfiirs uh^n r 
 
 For high temperature the worst- case condition occurs when T n is on, 
 
 T 2 off, 
 
 \ + *cbo • he - ^f^ < A - 12 > 
 
 R B 
 
 V CE( S at) " ( ^D + V * V BE0 < A - 13) 
 
 Now I occurs when all N - 1 outputs carry I „ (This corresponds to the case 
 where all M - 1 inputs to T p are ? 'h") 
 
 In both NAND and NOR a certain amount of noise margin must be provided, 
 
 In the case of the NAND circuit, the noise margin should be included in the 
 
 V^,- \, and for the NOR included in the V.^-. 
 rSili^saty BhiU 
 
26 
 
 To solve the above equations, an iteration method is needed,, but 
 iteration is not practical except by a digital computer calculation. However 
 a suitable choice of intermediate variables V and I will make an approximate 
 calculation possible. 
 
 From the standpoint of logic speed, V should be small because of 
 the delay characteristics of the NAND circuit fabricated by the 2N2369, A lower 
 limit of V in the NAND circuit is given by 
 
 Do 
 
 v / \ + v - v = v 
 
 CE(sat) -D BEO -DS 
 
 at 100 Co Therefore the average value is: 
 
 V 
 
 DS 
 
 V CE(sat) + < X - ipyi + O-OS) - V BE0 
 " ~ (1 - p)(l - 0,2) " 
 
 Tentatively, we have chosen the FD100 (logic) and T.I51 (level shifting in NAND) 
 diodes; forward characteristics are given in Table 2, 
 
 Table 2, Diode Forward Characteristics 
 
 
 50 ua 
 
 100 ua 
 
 500 ua 
 
 1 ma 
 
 2 ma 
 
 5 ma 
 
 
 v DS (TI51) 
 
 .k 
 
 ,425 
 
 .^53 
 
 ^533 
 
 • 571 
 
 ,621+ 
 
 volts 
 
 V (FD100) 
 
 A55 
 
 M 
 
 • 57 
 
 ,60 
 
 = 63 
 
 ,70 
 
 volts 
 
 Substitute these values and ^ = p = 0,2 into the equation for V~ a | we get 
 
 JJo' 
 
 Min V DS - 
 
 
 
 
 
 
 0.77 
 
 f ° r V BE0 = 
 
 = 0,3 
 
 CE(sat) 
 
 = 0,3 
 
 1,3= 500 ua 
 
 0,81 
 
 f ° r V BE0 = 
 
 = 0,3 
 
 CE(sat) 
 
 = •0.3 
 
 X DS = X ^ 
 
 0,85 
 
 f ° r V BE0 = 
 
 = 0,3 
 
 V / N ; 
 
 CE(sat) 
 
 ~- 0,3 
 
 t ds= 2 ma 
 
27 
 
 Therefore to guarantee operation at 100 C under the 20-percent variation in the 
 forward voltage drop of the level-shifting diode, we require two silicon diodes 
 in series for level shifting. 
 
 Due to variations in temperature and diode characteristics, I and 
 I are related as follows : 
 
 4) 
 
 (in Eq. (A. 8)) = I D (in Eq. (A. 7)) (l - 0.17)(l - 0.08) 
 
 I D (in Eq, (A. 8)) - I_ D (in Eq, (A. 7)) (l + Tl)(l - p)(l - 0.17)(l - 0.08) 
 
 Therefore I is now expressed as: 
 
 V - V / x 
 I c = (N-l)(l + T])(l-p)l D (l-0.17)(l-0.08) + -^ =CEisat2 + ^ (l _ Ool7)(l _ Oo0 8) 
 
 For the NOR circuit, similar relations hold, hut it would be redundant 
 to described all of them. Numerical calculations are given only for the NAND 
 circuit for the same reason, 
 
 The 2N2369 has the following static characteristics: 
 
 BE (sat) 
 
 ^FE 
 
 V 
 BEO 
 
 at -15 C 
 
 at -15 C 
 
 0,9 volts 
 20 
 
 at +100 C +0,3 volts 
 
 -CE(sat) 
 
 CE(sat) 
 
 at -15°C 0,2 volts (I = 10 ma ~ ^0 ma) 
 
 at +100 C 0,3 volts (L = 10 ma ~ 40 ma) 
 
 "CB0 
 
 at +100 C 3 ua 
 
 V° c 
 
 for the FD100 -1,8 
 
 mv 
 
 The solution of the equations for the given variation of components, 
 voltage, and temperature range is determined for the given values of the 
 intermediate variables, 1 , N, I , V . For the calculations, variation of diode 
 
 D Do 
 
28 
 
 characteristics is assumed to be + 20 percent; resistance variation is 5 percent; 
 
 and the temperature range is -15 C to +100 C. In the numerical calculations,, 
 
 V^^^ at +100 C was taken as volt, and V / \ at -15 C was taken as +1„0 volts 
 BliO tit, \ s at ) 
 
 From Eqso (A. k), (A. 7), (A. 9), (A.l4), we get the solution shown 
 
 in Fig. 17= 
 
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APPENDIX B: SWITCHING WAVEFORMS 
 
 Switching performance of the transistors (2N2369) themselves are very 
 uniform. But when fabricated into logic circuits (because of the nonlinear 
 transients and difficulty of solving the resulting equations) it is difficult 
 to estimate the switching waveform. However even approximate waveform considera- 
 tions can give much help in the design of the circuit. An approximate description 
 of the waveform will be given in this Appendix. Switching speed of the circuit 
 in most networks is also limited by coupling between conductors , parasitic 
 capacitance and inductance. 
 
 Turn-on Waveform 
 
 The turn-on waveform of the circuit with fanout is principally composed 
 of two parts , as shown in Fig. 18. 
 
 Increasing the number of fanouts gives only a small change in turn-on 
 
 dh FE 
 time because of the nonlinearity of tu, ^ T > and the small output 
 
 c 
 resistance of the transistor. For both NAND and NOR, after the input diode of 
 
 the next stage changes, build-up speed of the present stage generally decreases. 
 
 The capacitive coupling between base and collector acts as an 
 integrator; therefore, even if the transistor has infinite speed, the build-up 
 time constant is PCR,,. 
 
 Turn-off Waveform 
 
 The typical waveform, shown in Fig. 18, is more complicated than the 
 turn-on waveform. For the first period of turn-off, the waveform is approximated 
 by 
 
 r(t)V 
 
 cc 
 
 R + r(t) 
 
 r(t) 
 
 R n 
 
 c v ' L 1 J 
 
 if r(t)C « 1 (B.l) 
 
 Here r(t) is the output resistance transient characteristic. In this period, 
 the effect of load capacitance is negligible because the transistor is still in 
 the active region. 
 
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32 
 
 Passing through this period, turn-off characteristics are determined 
 "by the load capacitance and load resistance (for NAND, also by bias resistance) 
 The waveform here is approximated by (until the disconnection of the next stage 
 input diode ) : 
 
 t 
 
 R C\ 
 e ) for NAND (B.2) 
 
 / R r c\ 
 
 V f 1 - e ) for NOR (Bo 3) 
 
 After disconnection of the next stage input diode,, the waveform is: 
 
 for NAND (B.*0 
 
 until clamping sets in. The cutoff clamping level is determined by the clamping 
 
 diode in the NAND, and by the V , * in the NOR, 
 
 jDiii ^ s at / 
 
 From the above behavior, to reduce propagation delay, the conducting 
 
 level should be chosen to occur in the range of r(t)C « 1. If designed 
 
 according to this criterion, propagation delay does not depend upon the number 
 
 of f anouts . 
 
 For the NOR circuit, however, to specify the conducting level as 
 described above would decrease the high-frequency noise margin . Therefore this 
 design cannot be applied . For the NOR circuit, the turn-off waveform, to be 
 compared with the NAND waveform, is also shown in Fig, 18. The waveform, after 
 the input diode of the stage (NOR) reaches conduction, is the charging curve 
 of the level-shifting diode capacitance. Therefore the time constant depends on 
 the negative base bias level. When this negative level is low, the charging 
 time constant is smaller and the conducting level of the input diode is higher-- 
 if the next turn-on signal arrives fast. This situation can be easily under- 
 stood by referring to the base waveform in Fig, 18. The main difference in the 
 turn-off characteristics of the NAND and the NOR comes from the change in 
 conduction of the level-shifting diode in the base circuit. The higher conduction 
 
33 
 
 level always results in more delay for propagation. Therefore we must take 
 into account the above situation when determining the negative "bias voltage. 
 
 Noise Margin 
 
 Noise margins of the NAND and NOR are also indicated in Fig. 18. This 
 margin has different values for slow noise than for the fast noise. 
 
 For slow noise, the margin is equal to the difference between the 
 
 clamp level and the conducting level for the NAND, and equal to the difference 
 
 between V , \ and conducting level for the NOR. For high-frequency noise, 
 Oil) y sat ) 
 
 this margin is referred to V OTn/ , \ in the NAND, and to V^-- in the NOR. Noise 
 D -BE(satJ ' BEO 
 
 can sometimes cause considerable delay until the waveform, recovers to the correct 
 value. This is the one disadvantage of saturated operation. 
 
 The delay per logic function is shown also in Fig. 18. This delay 
 is more sensitive to fanout for the NOR than for the NAND because the delay 
 depends mostly upon turn-on for the NAND circuit and upon turn-off for the NOR 
 circuit .