LIBRARY OF THE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN 510.84 vio.559-56i- CO)D. ^ C, Digitized by the Internet Archive in 2013 http://archive.org/details/semantrixsemanti559mudg c, r jHtjJ UIUCDCS-R-T3-559 1/ COO-1U69-0217 if SEMA.WTRIX: A Semantic ally Guided Digital Electronic Machine "by Trevor Nigel Mudge February 1973 tH& UBBAR^ OF THE MAR < lb ' 3 DEPARTMENT OF COMPUTER SCIENCE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN URBANA, ILLINOIS UIUCDCS-R-73-559 SEMANTRIX: A Seraantically Guided Digital Electronic Machine* by Trevor Nigel Mudge February 1973 DEPARTMENT OF COMPUTER SCIENCE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN URBANA, ILLINOIS 6l801 Supported in part by the Department of Computer Science and the Atomic Energy Commission under contract US AEC AT(ll-l)lUb9, and submitted in partial fulfillment of the requirements of the Graduate College for the Degree of Master of Science in Computer Science. C$ (Q . 2^ ACKNOWLEDGMENT 111 The author would like to take this opportunity to thank his advisor, Professor S. Ray, for his guidance and Professor W. J. Poppelhaum for the opportunity to work in his Research Group. The work described in chapter k is largely the effort of Dennis Kodimer, as was the construction of the electromechanical system outlined in chapter 5. The author would like to thank him for a convivial collaboration, Finally a word of thanks goes to the 2 typists who typed the report; Ms Barbara Bunting and Ms Janet van Weringh. <; V,***.'. IV TABLE OF CONTENTS Page 1. INTRODUCTION 1 1.1 Overview of Semantrix ■ 1 1.2 Applications to Cognitive Systems 1 1.2.1 Organization of WM for the Landscape Synthesis Problem 3 1.3 The WM Concept 6 2. A SYSTEMS DESCRIPTION OF SEMANTRIX 10 2.1 The Control Logic 10 2.2 The Hand-Arm Limb 11 2.3 The Cube Locating System lk 3. A LOGICAL DESCRIPTION OF SEMANTRIX 20 3.1 The Instruction Set 22 3.1.1 Type 1 Instructions 22 3.1.2 Typ e 2 Instructions 23 3.1.3 Type 3 Instructions 2U 3.1.4 Type k Instructions 2k 3.2 The Input Format 25 3*2.1 Extended Mnemonics 26 3.3 The Control Logic 26 3.3.1 The System Clock 3^ 3.3.2 The Bit Sequencing Logic 36 3.3.3 The SROM 39 3.3.4 ^ le Bit-Wise Sequential Detectors 1+0 3.3.5 The Character-Wise Sequential Detectors 1+3 3.3.6 The Error Routine Actuator 1+8 3.3.7 MA and Mode Logic 1+9 3.3.8 Channel One 51 3.3.9 Channel Two 6l 3.3.10 Channels Three and Four 66 3.3.11 Channel Five 68 3.3.12 Channels Six and Seven , 71 "*4 1% Page h. SPECIAL CIRCUITS: THEIR DESIGN AND OPERATION . . . 77 U.l The Threshold Circuits . . . „ „ „ . . 77 k.2 The Cube's Receiver /Transmitter 80 U.3 The Power Transmitter „ 8U 5. THE ELECTROMECHANICAL LIMB 88 5ol Generating the X-Y Motion 88 5.2 The Hand's Motion , . , . , 92 6. CONCLUSION 93 LIST OF REFERENCES 9^ APPENDIX A The Clock Operation 95 APPENDIX B The Contents of the SROM 98 1. INTRODUCTION 1.1 An Overview of Semantrix Semantrix is a digital machine, whose domain of activity (or world) is a rectangular plane or table top. (See Figure 1.1.1 for a diagram of the machine). Its activity in the plane can he instructed from either a teletype or a digital computer. Semantrix and a teletype can form a stand alone system. However, to make full use of the machine, a digital computer should be used as a controller. Semantrix can thus be viewed as a special piece of I/O equipment. The machine's capabilities in its two dimensional world are: 1. The ability to compute the position of any one of up to 6U small cubes that can be placed in the rectangle. Each cube has a numerical label associated with it. It is thus possible to instruct the machine to compute the position of cube N(Ne {0, ..., 63}) by just handing the number N to the machine. The reply is a 6 octit number. This represents a unique inter- section on a quadruled grid which partitions the table top. The controller (human or electronic) can also use the label to create an associative memory which can be used to store information con- cerning a particular block (e.g. color, record of movements, etc.). 2. The ability to move any particular cube to a prescribed point on the table top. This is achieved electro-mechanically. 1«2 Applications to Cognitive Systems An immediate application for Semantrix is to test the viability of certain cognitive maps, or world models (WM). The map would be stored •H U -P B (X! O o5 H H M Pi •H in the digital computer which controls Semantrix. Thus by referring to the map the computer can direct Semantrix to synthesize a particular example of the general class of things which are supposedly modelled by the cognitive map, For reasons that will be outlined in Section 1.3 an interesting problem is the synthesis of landscape pictures. To test a WM which attempts to model a landscape picture, colored cubes are used, and under the control of the computer Semantrix synthesizes a mosiac landscape picture. Two basic attributes are associated with each cube. One is position on the table top. This can be computed by Semantrix. The second is color. This must be input to the computer prior to an attempted synthesis. It takes the form of a table of information mapping the cube number onto the colors. Typically it might be as follows: Color Red Green Blue White Brown 1.2.1 Organization of WM for the Landscape Synthesis Problem At its highest level the WM embodies relationship data, or context- interdependency data between a set of hypothesis which describe lower level regions of the model landscape. The context-interdependency data reflects constraints known to exist normally in the "real world". (See list 1 for examples. ) Cube number a: (2, , 25) (26, ., U9) (50, ., 58) (59, m m ., 6U) SKY SUN SKY CLOUD SKY WATER FIELD HOUSE FIELD ROAD ROCK FIELD RELATIONS INCLUDES ADJACENT-ABOVE 1 — 1 — -1 .5 .5 .5 .5 -J. -.5 .5 -.5 BINARY INTERDEPENDENCE RELATIONS of the form (H ) (RELATION ) (H ) . Values from -1 to 1 range from "strongly denied" through "uncertain" to "strongly affirmed"; "-" means "value is redundant" since the relation is superceded "by another (e. g. "includes" supercedes "adjacency" in some cases above ) . List 1. Examples of Context Interdependency A straightforward example of a strong constraint is that of "SKY includes SUN". Hence creating two regions of mosaic, one of which was labelled SUN and the other SKY, would be done such that the SUN was contained in the SKY. An example of a weak constraint is "SKY adjacent-above WATER", meaning that if the hypothesis pair (SKY, WATER) have been created, then it is desirable to place SKY adjacent to and above WATER. However, this is not necessary, and it may not be given precedence if it causes conflict to occur in another step of the synthesis. At this point it may seem that the goal of the synthesis may be expressed in purely deterministic terms, that is to maximize the sum of the binary interdependency relations in the mosaic. This is not quite the case, as it would imply an optimum landscape. Clearly this is in some sense unrealistic, as there are many scenes that could be called landscapes, many of which may even have joint membership in other categories of pictorial scenes. The goal of the synthesizer is better expressed in nondeterministic terms by saying that, after a large number of syntheses, it would be expected that some scenes would occur frequently, some less fre- quently and some of the possible 6h\ permutations of the 6k cubes, never at alio At a lower level in the WM, information about all the possible regions, that can be hypothesized, exists. This information is in the form of a list of all the possible major regions thought to be found in a landscape and all the possible subregions that are thought to occur within those major regions. (See List 2). OPEN REGIONS INCLUDED REGIONS 1. SKY SUN, CLOUD 2. WATER BOAT, ISLAND 3. FIELD HOUSE, TREE, ROAD h. ROCK 5. OVERCAST SKY BLUE PATCHES 6. ICE-SNOW HOUSE, TREE, ROAD 7. SAND ROCK, HOUSE List 2. Regions At the lowest level in the WM the regions are described in terms of the cubeso That is the color of the cubes and the bounds on the number of cubes constituting any particular type of region, By specifying the number of cubes in a region, the cubes positions on the quadruled rectangle are indirectly specified. Hence this model is based solely upon two physical attributes of the cubes. One is color, the other is position in the rectangle. Since there are only a finite number of meaningful statements that can be generated about landscapes "based on two attributes, more sophisticated models "would be based on a greater number of physical attributes. Hence the building blocks in such a synthesis would also have to be more sophisticated, than the cubes use in Semantrix. With this in mind a more sophisticated model can be constructed by incorporating inconceivable factors. E.g. Information concerning the climate that is to be associated with the synthesized scene could be incor- porated. This would prejudice the synthesizing process, so that specifying an artic climate would increase the frequency of scenes having large white regions in them. 1„3 The WM Concept Chapter 1 will be concluded with a brief introduction to the WM concept. The WM concept is an attempt to incorporate into a cognitive system a prescribed data structure (called the cognitive map) that will enable the cognitive system to exhibit intelligent behaviour. A general system theoretic model for a cognitive system is shown in Figure 1.3.1 The cognitive system partitions into two parts. A model of the stimuli's world (the WM) and a cognitive algorithm which interprets the stimulus under the control of the model. Together they are called a "cognitive memory", since they perform static data storage together with dynamic recognition of stimuli. The output of the cognitive memory after it has been excited by a particular stimulus is the interpretation. This may be characterized as a type of algorithmic association of features of the stimulus to features of the map. "Understanding" would be a bolder descriptions Preprocessed Stimulus Cognitive Memory i_i Interpretation Figure 1.3.1 General Cognitive System 8 Semantrix is an attempt to test the fidelity of the type of pre- scribed data structure (i.e. a WM) that might be used in such a cognitive system. In the past it was generally accepted that the WM could be generated by the now classical techniques of learning theory. These are a collection of statistical techniques for learning distributions from paradigms, that have long been known to people interested in signal processing classification and statistical estimation. In many cases it was found that the model learnt by such methods was in some sense adequate. However in many other cases this approach broke down. As an example take the identification of a particular electronic network, say a flip-flop. The input to the system can be a circuit schematic. Under control of the WM the cognitive system must identify those drawings which represent flip-flops. Distinguishing circuit components using a WM which is learnt from a training set is quite feasible. Identifying configurations of these components which are flip-flops can only be accomplished if the WM incorporates some prescribed syntatic description of a flip-flop, which uses the circuit elements as terminal symbols. Another example where statistical models prove inadequate, is modelling natural scenes. The constituents - colore regions in the case of Semantrix - are easily discernable, but to be effective the WM must embody the semantic structure of such a class of scenes; in other words, reflect the constraints of our universe. The shortcomings of the statistical approach can be overcome, if the constraints can be identified and incorporated into a WM. Work on natural scenes using Semantrix is an attempt to identify the semantic constraints and incorporate them into a WM; hence the acronym Semantri: The notion of a WM is relatively new to the study of artificial cognition. Two of the most recent papers to discuss this concept in depth are given in References 1 and k. 10 2. A SYSTEMS DESCRIPTION OF SEMANTRIX In this section a general description of Semantrix is presented, at a system theoretical level. The details of the implementation are deferred until later sections. The system divides into three separate subsystems (see Figure 2.1). 1. The control logic. 2. The electromechanical hand-arm system for manipulating the cubes. 3. The cube locating system. 2 1 The Control Logic The control logic interprets commands input through its single bilateral data channel. The design and operation of the control logic is discussed in detail in Section 3. Here it is sufficient to remark that the commands interpreted by the control logic can result in three types of response. The first of these is the response to a command which is syntatically incorrect. This results in an error message being output along the bilateral data channel. The second of these is the response to a command to move the hand-arm limb in one of its four independent motions. When a command to move the limb has been interpreted and then achieved, a completion message is output along the bilateral data channel. The last type of response is a command to locate a specific cube (specified by number) on the quadruled grid that partitions the table top. A six octit number which uniquely specifies the grid square over which the cube'.s center rests, is output along the bilateral data channel. C 11 2.2 The Hand-Arm Limb The four independent motions of the hand-arm limb are shown in Q Figure 2.2.1. The hand can be moved to any one of 2 positions in the x- Q direction and any one of 2 positions in the y-direction. The rectangular table top is 36 inches square (see Figure 1.1.1 ), so this represents a linear precision of: 36 _ 9 " _ 5 2 9 128 6k That is, the motion of the hand conforms to a quadruled grid having a grid spacing of 5/6V in both x and y directions. To eliminate positional error the x and y motions are achieved by using a "torque proportional to error" closed loop servomechanism. The block diagram for this subsystem is shown in Figure 2.2.2. The detailed discussion of the subsystem is left until Section k. However, a few remarks will be made in passing. First, the des- cription of the servomechanism derives from the type of motor used. This generates a torque, proportional to the driving voltage. The driving voltage is a measure of the difference between the actual position of the hand and the desired position of the hand; it thus represents a measure of error from the hand's desired position. Hence the phrase "torque proportional to error". Second, the input to the servomechanism is in digital form (the contents of a 9-bit register), which has to be converted to analog form to be compatible with the servomechanism. The conversion is done by a standard D/A converter, which introduces a possible +0.05% of FS error. FS in this case corresponds to 80 inches. Therefore, the error is given by: + — ^— x 80 = 1 x 5 ". - ioooo x ou "? 2 6T ; 12 f Bilateral j Data Channel Control Logic J ' r i Hand- Arm Subsystem Cube Locator Figure 2.1 System Block Diagram Arm X-Motion Hand V-Moti f 2 Positio on < Raised ns v^ F- Motion 2 Positions Open /Closed z Rectangular Table Top Figure 2.2.1 Motions of the Hand-Arm Limb Lowered Fingers 13 9-Bit Coord Reg < Q CD i O s en ■H cu ■p Cm O bO ctf Q ^) o o H pq CM C\J (M QJ to ■H Hi- Ik that is, half the grid pitch. This is acceptable, as will he seen in later analyses. The other source of error in the x and y positions is introduced by the error detector (see Figure 2.2.2), which is realized by an operational amplifier. Here the null position is the main concern. For correct operation the offset voltage should be zero. This can be achieved by using an operational] amplifier with an offset-voltage null capability. The electromechanical hand has two more motions, the F-moticn and the V-motion. Both of these are transition motions between two stable posi- tions. The F-motion refers to the motion of the mechanical fingers on the hand (see Figure 2.2.1). These have two stable positions: "open" and "closed". This motion enables the hand to grasp the cubes on the table top. The V-motionl refers to the vertical motion of the hand's subassembly, containing the fingers! The two stable positions are "raised" and "lowered". Once the cube has been grasped by the hand's fingers, this motion enables the hand to raise it clear of other cubes that might be lying on the table. By initiating motion in the x and y directions the cube may then be transported across the table top. 2. 3 The Cube Locating System The cube locating system is depicted in Figure 2.3.1. The 6k cubes available to Semantrix are uniquely identified by a 2 octit number on the range 00q - TTn. To locate a particular cube its number is input to the con- trol logic through the bilateral data channel, together with the appropriate instruction (see Section 3.1 for instruction formats). The instruction is interpreted by the control logic, and as a result the 2 octit number is handed to the locating system, together with a start signal. The start signal enables the power transmitter (see Figure 2.3.1 (a)), which begins radiating 15 electromagnetic energy from an inductor. The inductor is formed from a single loop of copper which runs beneath the perimeter of the table top. It also forms, together with some capacitors, the tank circuit of the power transmitter, the details of which are discussed in Section h. The energy is radiated for 1 mS, then the transmitter, automatically shuts off. The cubes contain a receiving coil which, in effect, forms a loosely coupled transformer with the loop of the transmitter. Capacitors in each cube store the energy they receive during the lmS radiation period; then subsequent to this period, they discharge their stored energy at a pre- determined time. The discharge is through another inductor which is wound on a cylindrical ferrite core (see Figure 2.3.1 (b)). This results in a pulse of electromagnetic flux coaxial with the ferrite core. The detailed design of the electronics in the cubes is discussed in Section U. However, it should be noted that the cubes are passive; that is, they have no local power supply but derive all their operating power from the power transmitter. The pulse of magnetic flux produced by each block is normal to the table top and is detected by a matrix of conductors which is just under the surface of the table top (see Figure 2.3.1 (c)). The construction of the matrix is shown in Figure 2.3.1 (d). There are two sets of 89 loops, which are etched onto opposite sides of a printed circuit board, at right angles to one another. The loops are open at one end so that a small potential difference is induced between the ends of any loop if the flux through the loop changes. This induced voltage is sensed by a threshold circuit (see Section U for details of the threshold circuits). The table top is partitioned into a matrix of 89 x 89 O.V square cells or quadruled grid, by the orthgonal loops. Hence, the flux 16 H to ili n 6 £ i L EEEETD ] \ * s < £ <-> ■C ? 3 2 £ Z T3 3 «l II Q c s > CO W> C •H 13 o QJ O u Eh CM 0) bQ IT change produced when each cube releases its stored energy will he sensed as having occurred in one of the 89 x 89 square cells (assuming of course, that the cube is on the table top). Two threshold circuits, one from the x group and one from the y group, are thus activated when each cube releases its stored energy. There are 89 threshold circuits in both the x and y group. The 89 output lines of each group are encoded into 7 bits of Gray code by a diode matrix. Thus the position on the quadruled grid of the center of each cube is encoded into two 7 bit Gray code numbers; one representing the x coordinate, the other the y coordinate. In order to distinguish the cubes, the point in time when they release their stored energy is made unique. This time out, between the termina- tion of power transmission and the release of the stored energy in a cube, is governed by an RC time constant. Each cube has a different time constant which is chosen so that its time out is related to its code number N (0 < N < 63) by the following equation: T OUT = (N * 128 + 6U)wS (Recall that each cube has associated with it a unique two octit number on the range 00q - 77n = N ) . The time period after the power transmission can be regarded as being divided into 6k time slots of 128yS each (see Figure 2.3.1 (a)). Cube N will then be expected to reply in the (N + l)~ such time slot. As implemented, the instruction to locate a block will request the coordinates of a specific cube, N. In response to this the control logic enables the inputs to the buffer register, which receives the two 7 bit coordinates, during the N time slot only. Hence the coordinate buffers contain either two 7 bit Gray code numbers, representing the position of cube N on the table 18 top, or, if the cute is not on the table top, 0. The control logic output the contents of this buffer in a prescribed format (see Section 3) through the bilateral data channel. Since there are 6h time slots the T for cube N = 63, the worst case, should be within +0.8% of its normal value over the normal operating temperature range. T i- s a linear function of the F.C time constant, so it is necessary to use resistors and capacitors with the above degree of tempera- ture stability to form each cubes time out generator. This is not a very difficult or expensive specification to satisfy. In fact, this worst case analysis is only true for K = 63; the tolerance progressively loosens as N decreases. For N = 0, the tolerance is +100%. Two more points should be mentioned before concluding the section. The first concerns the use of Gray code to encode the x and y positions. It is possible that two adjacent loops in either the x or y direc- tion may detect the same cube's reply. Hence two input lines on one of the 89-to-T line encodes would be activated at once. The result would be as follows: consider two adjacent input lines that would normally encode as A = a 6 a 5 a 1+ a 3 a 2 a 1 a and B = b 6 b 5 b^b 3 b 2 b 1 b Q When they are activated simultaneously the resultant encoding, C, is given by the bit-wise logical OR of A and B. C = C 6 c 5 % C 3 C 2 c l c O where .c. = a. V b. i = 0, .. . , 6 ill ' . ' If A and B are in Gray code, then C = A, or C = B, since adjacent Gray codes differ in one bit only. Had A and B been in a normal binary sequences the abci would not be true. Consider: 19 Normal Gray JT. — 000] 000 OOQilOO B = 0000111 0000100 C - OOOlll'l C 001100 then By using the Gray code approach the loss in precision of the cube's center is held, at +0.V ; . The fingers of the hand are designed to accommodate this degree of uncertainly. The second point to "be mentioned concerns the precision of the hand's motion. To place cubes adjacent to one another requires high precision in the motion of the hand. Between centers tvo adjacent cubes are 2" apart. The hand moves in increments of 5/6U," therefore, it is possible to place tvo cubes within l/32 M of each other. This tolerance also allows for the uncertainly in the hand's motion. 20 3. A LOGICAL DESCRIPTION OF SEMANTRIX In this section the design and operation of the control logic is described. Semantrix is intended for use in a logical system, such as the one shown in Figure 3.1. The system comprises: 1. Semantrix (S) 2. A teletype (T) 3. A data processor (D) As was mentioned in the introduction, Semantrix can form a stand alone system with just the teletype. This is achieved, in a system such as the one shown in Figure 3.1, "by moving the switch to the D position, thus putting the system into direct mode. However, this should only he regarded as a test mode, in which the logicality of Semantrix control logic may he tested. In order to operate the machine in the type of experiments outlined in the introduction, the switch must be moved to position R, putting the system into remote mode. In this mode the data processor instructs the control logic of Semantrix, and the teletype is used to initiate the I/O subroutines in the data processor, which handle the data flow to and from Semantrix. Furthermore, the storage ability of the data processor provides a residence for any model or cognitive map. The complete assemblage forms a cognitive system, as described in the introduction. The double pole single throw switch which connects Semantrix to the data processor or directly to the teletype also switches different clock gener? tors into the clock bus of the control logic. In direct mode a 110Hz clock C 21 £ S S , *-^ o o *■ E < 2 * Q_ 5 K — c5 i i i k < — Q -C w* o ^_ — o ^ a> CO -^ Q £ .. 2 S JC o h- '-g r J J* © © ! r J .E o >Y 1 i if) ^ ^ - o ® en o a> Q_ -D o ® s jQ 3 2 o £ Q h- \ f Q) >< Q. *k» >* h- "5 C co 2 iS E > en 05 CO a5 -P n5 e 00 •H drives the clock "bus. This is compatible with the 110 Baud data rate of the teletype. In remote mode as fast a clock as is compatible with the data pro- cessor should be used. 3.1 The Instruction Set Before the control logic is examined in detail, it is necessary to give the instruction set that is interpreted by Semantrix. All instructions enter the bilateral data channel of the control logic in serial form, each character being in standard teletype format (see Section 3^3 for details). Replies generated by Semantrix are output serially along the bilateral data channel, also with each character in standard teletype format. For the pur- pose of discussing the instruction set it is sufficient to consider that the instructions are input through a teletype, and that the replies are received by a teletype. When this is not in fact the case i.e. when Semantrix is connected to a data processor, the same format is preserved, but the data rate is considerably increased; the data processor is programmed to have the I/O characteristics of a teletype. The bilateral data channel is the normal type used to communicate with the ASR33 Teletype, and is sometimes referred to as a half -duplex channel. There are four types of instruction that can be input into Semantrix, discounting incorrect ones. 3.1.1 Type 1 Instructions These instructions are used to request the coordinates of any block. Send: N mn Rt The letter N followed by two octal digits m and n is typed in through the teletype, together with the non-printing character "carriage return" (Rt). Recall 23 that each of the 6h cubes are specified by a unique number mn which lies on the range 00q - TTo. A reply- is generated by Semantrix, which produces the following result at the teletype. Receive: Lf x g X X Q Y^Yq Rt Lf |Lf E Rt Lf The non-printing character "line feed" (Lf) is sent from Semantrix to the teletype followed by a six octit number which uniquely determines the cube's position on the quadruled grid. Recall that the grid partitions the table top into 89 x 89 squares; hence x x x or y p y,y n lie in on the range OOln - 131r>. In the case where a cube is not on the table top x x x and y 9 y,y = OOOn. The non-printing characters Rt and Lf terminate the reply, causing the teletype's carriage to be returned to its left most position on a new line. If there is a transmission error between the teletype and Semantrix, or if the instruction input through the teletype is syntatically incorrect a standard error message "Lf E Rt Lf" is generated by Semantrix and received by the teletype. The allowed formats that the instruction "N nm Rt" can have without being rejected by the control logic and causing an error message to be output is discussed in Section 3.2. 3.1.2 Type 2 Instructions These instructions are used to move the hand-arm limb across the table top. It was seen in 2.2 that the x and y motions were subdivided into incre- mental motions of 1/2 9 of FS. Hence to specify a point to which the hand should 2\ move the two 9 bit numbers must be used. For convenience octal notation is used which means a six octit number must be input to Semantrix. The instruction has the following form: Send: C ^ 2 \^ Q y 2 y i y Rt A C is typed in followed by a six octit number; which is on the range: OOOOOOg - TTTTTTg. A non- printing carriage return delimits the message. Two possible replies result. Receive: LF E Rt LF | Lf Bell The first of these denotes a syntax error as before. The second is nonprinting, and causes the teletype's bell to ring, indicating the instruction has been executed by the control logic. 3.1.3 Type 3 Instructions These instructions are used to lower and raise the hand. Send: L E Rt|R E Rt The first instruction lowers the hand, the second raises it. The possible replies are the same as for type 2 instructions, and they have the same meaning. 3.1.U Type jl Instructions These instructions are used to open and close the hand's fingers. Send: E Rt|E 1 Rt The first instructions opens the fingers, the second closes them. Once again, the possible replies are the same as for Type 2 instructions, and they have the same meaning. 25 3.2 The Input Format The k types of instructions can he input through a teletype in various types of format. With certain limitations the strings of characters which represent instructions can be interspersed with any sequence of blanks and other characters. The following is an acceptable type 1 instruction: *N*3*2*Rt where * can be the null string or any string of teletype characters. The only restriction on the stars is that they do not contain another allowed input sequence. Formally, this limitation can be described in a recursive fashion. If v i v ? • • * w r W r+1 "" v Rt is an allowed input sequence and Then the input sequence _ W = w. w. . . . w 1 r 12 r W = w w ... w r+1 n r+1 r+2 n w.w . . . w A w _,_. . . . w Rt 12 r r r+1 n is allowed iff the set of sequences given by tW X A X W X Rt} — ww . .. w A w . . . w Rt J- r r r+I n 12 r r r+1 n are not. Where the * operation denotes the set of all subsets with order pre- served. E.g. if A = {a, b, c} * A = { a, b, c, ab, ac, be, abc} whereas if A = {b, a, c} A = {a, b, c, ba, be, ac, bac} The X operation denotes the Cartesian product. 26 For example, if N329Rt were input it would be accepted and would be taken to be the same as N 32 Rt . But N 32 EO Rt would cause an error mes- sage to be printed out, because N 32 Rt and E Rt are both allowable. The don't-care assignment of the stars allows an extended mnemonic facility and a flexible input format. 3.2.1 Extended Mnemonics The following are examples of the extended mnemonic facility made available by the flexible input format. Type Essential Extended 1. N 36 Rt NUM 36 Rt 2. C li+2 613 RT COORD lU2 6l3 Rt 3. L E Rt|RE Rt LOWER Rt | RAISE Rt h. E Rt|El Rt OPEN Rt | CLOSE 1 Rt 3. 3 The Control Logi c Having discussed the set of instructions together with their allowed formats, the organization of the control logic that interperets them can be described. Figure 3.3.1 is a block diagram of the control logic, depicting the signal flow between the component parts of the logic. All logic is imple- mented in Texas Instruments SN7^ series TTL. The design guides and a discus- sion of the circuit limitations are to be found in References 3 and 5. The heart of the control logic is the 11 bit by l6 word sequential read only memory (SROM). In each of the l6 words an 11 bit character in stan- dard teletype (TTY) format is stored. For details of the SROM contents see 27 o -H bO o o Sh ■P o o -p o S 5 Jh bfl cd •H n o o H PQ H on m 1 •H 28 o r-l -O -a t>0 O o o i- o x: O o Q L__ qo X) 10 jQ -O X) X) X) H ■H o (Li a> CO •p o M Cm O Cm Ql OJ 0) M b0 •H > in +■ > O CD U ~v- o tr 3 a. c c/) O o r m o a> +_ O QQ _l en •4— c o o .»_ c -1 V Q. 3 -*- CT 3 QJ o CO 3 CD a. •*- ■*— O 3 o o o — x: o o U n OJ >> x: 29 Appendix B. The standard TTY format can "be described "by the following bit string: 0XXXXXXX111 where the 7 X's are an ASCII character. Each word in the memory is output in a bit-wise serial fashion, under the control of the bit sequencing circuitry, which is basically a modulo-11 counter and decoder. The counter counts clock pulses from the system clock. The waveforms are shown in Figure 3.3.2; note the glitch that occurs after the count 10 pulse from the decoder. This is used to reset this and other counters in the system. The output of each individual memory location can be inhibited by suitable signals from the MA (memory address) and Mode logic. The Mode logic is in essence a flipflop which indicates whether or not the control logic is in the receive mode or the transmit mode. When the system is in the receive mode none of the memory outputs are inhibited and the action of the bit sequencing logic is to output all 16 characters from the SROM simultane- ously. This facility is used to identify input TTY characters. The falling edge that begins every TTY character simultaneously starts the bit sequencing circuitry and symchronizes the clock (see Figure 3.3.2). The character is broadcase to an array of l6 bit-wise character detectors where it is compared simultaneously to each of the l6 characters output from the SROM in a serial bit-wise manner. In this way input characters are classified. In order to interpret input instructions, it is necessary to be able to identify certain strings of characters. This is achieved by using 30 - h character-wise detectors SMI, SM2 , SM3 and SMU (see Figure 3.3.1). There are h types of instructions (see Section 3.1); SMI detects type 1 instruc- tions, SM2 type 2, etc. In the instance of a string of characters not being identified "by any of the h character-vise detectors, the machine is put into transmit mode and an error message is transmitted down the bilateral data channel. This corresponds to a message being syntatically incorrect. Once a character-wise detector has accepted an input message as an allowed instruction, certain action must be taken; e.g. move the limb, locate cube number N, etc. This is done in the following fashion. Each character-wise detector has slaved to it an interpretive channel which oper- ates asynchronously to it (see Figure 3.3.1). When a message has been accepted by a character-wise detector, it sets the channel flag of the channel which is slaved to it and passes prescribed informtion to the channel for interpretation and eventual use at the output end of the channel (the output end might drive the limb's motors, etc.). The channels also return completion signals, when the action required by the input message has been effected. When a channel flag is set it inhibits any input through the bilateral data channel by means of a set of OR gates in the interface circuitry. The completion signals reset the channel flags, place the machine in the transmit mode and initiate the out- put of a reply message along the bilateral data channel to the TTY or data processor. The retransmission of TTY characters along the bilateral data channel also makes use of the SROM. Naturally the only characters that can be retransmitted are those contained the SROM. When a channel requires to 31 output a string of characters, it sends an appropriate signal to the MA and Mode logic, which sets the machine into the transmit mode, thus enabling the output path of the bilateral data channel. It simultaneously inhibits, through the memory address logic, all the outputs of the SROM except that of the first character in the required string and initiates the counting sequence in the hit sequencing logic. The first character of the reply message is thus output. The count 11 glitch generated by the bit sequencer is used to reset the mode of the machine to receive. The mode remains unchanged until the nect asynchronous signal comes from the channel request- ing the output of the next character in the reply message. When the error routine is initiated due to a disallowed input string, all the channel flags must be reset together with the character-wise detectors, some of which may have been in the middle of accepting the input string. Furthermore, when one character-wise detector has accepted a string it must reset itself and the other three character-wise detectors, since the other detectors may be in a state of partial acceptance. The error routine generates its reply in the same fashion as the channels and is complete with a flag so it can be regarded as being pseudo-asynchronous. Figure 3.3.3 shows the asynchronous flow or signals from the main logic to a channel. There are four channels which communicate with the main logic in an asynchronous fashion. These are: channel l, which is responsible for cube location; channel 2, which controls the x-y motion of the hand; channel 3, which controls the up/down motion of the hand, and finally, channel b, which controls the open/close action of the hand's fingers. All of them communicate with external devices which are time independent of the control 32 CD O o > ••— CD ^_ Q zs Q. o ^~ r 3 v~ o CD ... X c LU c CD D > aj 41 -p CJ -P (1) pq CO H aJ C bO H •H O a rH h r ri ~ w al 2 o o a •H o W H o ■G i-l O £ 3 !>> •H [0 (Ti < 2 (U ^ H 00 C 33 logic's clock. (E.g. channel 1 is dependent on the timing requirements of the power transmitter.) The reply message is not generated directly by each of the channels 2 through k, since it is the same for each, namely Lf Bell. This task is delegated to channel 5, which upon the receipt of an appropriate pulse from any one of channels 2 through h will cause the retransmission of the above non- printing characters. Channel 6 is the pseudoasynchronous channel which generates the error message Lf E Rt Lf. Once again the output of the char- acters Rt Lf is not done directly by channel 6 since this pair of characters also terminates the channel 1 output message. Hence it is more economical in terms of logic to delegate the retransmission of Rt Lf to another channel, in this case channel 7 which is activated by a suitable pulse from either channel 1 or channel 6 (see Figure 3.3.1). Several points should be noted. First, the SROM has a dual role. In the receive mode it is used in the sequential bit-wise analysis of incoming TTY characters to the control logic. In the transmit mode it is used as a normal ROM to access data (in this case TTY characters) that is to be serially output. The second point to note is that the machine readily decomposes into a series of submachines. There is the SROM with the MA and Mode logic. Then there are the bit-wise analysers. Finally there are four submachines (SMI, SM2, SM3, and SMU) and their dependent channels, which perform the character- wise analysis and interpretation. This simple decomposition of the control logic makes debugging easier through replication of design techniques and also speeds the basic system design. The third point to notice is that the use of asynchronous channels permits the use of any speed of clock in the main logic. Each channel is slaved to the time of operation of the external device 3U that it controls, but since information is exchanged between the main logic and the channels asynchronously, the main logic is time independent of the external devices. It is, however, dependent upon the data rate used on the bilateral data channel. If a TTY is at the other end this is llObaud; if a computer is at the other end the data rate should be con- siderably higher. The last point to notice is that the system clock is synchronized by the falling edge which begins each input character. Hence the clock need only maintain its synchronism for 11 clock cycles (the number of bits in a TTY character). This relaxes the requirements on clock frequency drift. A drift of +2% is acceptable. To complete the description of the system logic, a detailed dis- cussion of some of the various boxes shown in Figure 3.3.1 follows, beginning with the system clock. The logic convention used in logic diagrams is mil-std-8o6b. 3.3.1 The System Clock The logic diagram of the clock board is shown in Figure 3.3.1,1. Two clocks are on the board. One operates at a frequency of 110Hz to be compatible with the TTY, the other at a frequency compatible with the data processor used to control Semantrix. The state of the flip-flop (FF) determines which clock drives the clock bus, and it is set by the Remote/ Direct mode switch discussed in Section 3. SN7U1+0 NAND buffers are used to drive the clock bus. The operation of the clock itself, which is built up from standard TTL SNTP's is quite and is dealt with in Appendix A. 35 ifl 4 VW O o H O >> W 0) EH H H oo o 0) •H P4 36 3.3.2 The Bit Sequencing Logic This is diagrammed in Figure 3.3.2.1. A k stage ripple counter (the SN7U93) is used to count the clock pulses, and a U-to-l6 line demulti- plexer is used to decode the output of the counter. Using a ripple counter can lead to hazards in any combinatorial logic driven "by the counter, because of transition states that the counter can cycle through in going from one state to another. To illustrate this point consider the following state of the counters FF's: D C B A 11 Upon receipt of a clock pulse to FF A the next state should be: D C B A 10 In fact the following cycle occurs: D C B A Transient, unstable states In other words, unwanted output pulses occur on the count one and count zero lines of the decoder. In the control logic six count lines are utilized: count 1, count 2, count 3, count 9, count 10, and count 11. It can be seem from the state transition diagram for the ripple counter in Figure 3.3.2.2, that 9, 10, and 11 never occur as unstable states; hence, no undesirable 37 ® +5V SN7400 [\P)>- ck^o-^o |~SN7493 "I D > L. c > B > A > SN74154 012 34567 89 10 11 J \ L^Sync H / To C Clock i> To Buffer Amp. D Count Lines Clear-To k — ►Bit-Wise Detectors System Figure 3.3.2.1 The Bit Sequencing Logic 38 u -P O o tu H Ph P* •H « ,d -P Is o «a0 cd •H P d o •H -P EH 0» Id ■P cvi CM on on u S) •H P>4 39 pulses occur on the count 9, 10 and 11 lines. The same can he said of 1 and 3, hut not our count 2 in however, count 1, 2, 3 are all used, with the system clock as a strohe, so that occurrences of count 2 pulses due to unstahle transition states are masked. The transition of particular interest is that between count 3 and count k t when the count 2 state occurs in transi- tion. Here the counter cycles through count 2 and count "before settling at the stable state, count h (see Figure 3.3.2.2). The FF's change state on the falling edge of the incoming clock pulses; hence, the unstable count 2 state above will not be concurrent with a clock pulse (unless the system clock is run at a rate near to the maximum speed of operation of the SN series logic). Hence its output is masked, since pulses on the count 2 line of the decoder are strobed by the clock at their point of application. There is another reason for strobing the count 1, 2 and 3 outputs of the decoder, besides eliminating the effect of the count 2 unstable state, and that is connected with aligning the input of data to channels 1, 2, 3 and U. It is discussed in Section 3.3.1+ an a Section 3.3.8. 3.3.3 The SROM This is constructed from l6 SNT^150 multiplexors (see Figure 3.3.3.1). The operation of the SN7U15O multiplexor can be described by the Boolean equation: W = s"(ABCD E Q + ABCD E + ABCD E + ... + ABCD E ) An eleven bit TTY character is hard wired into E E E ... E and the bit sequencing is done by applying the modulo-11 counting sequence to the A, B, C and D inputs of each multiplexor. Bits E through E are not used so they are left floating. Each character may be accessed by starting the bit 1+0 sequencing counter and bringing the strobe line low. The l6 strobe lines are used in memory addressing, and are controlled by the MA and Mode logic. To store the TTY character "l" shown in Figure 3.3.3.2 the follow- ing permanent connections are made: E Q = H E k = H Eq = L E = L E 5 = L E 9 = L E 2 = H E 6 = L E io = L E 3 = H E = H 7 E ll - : 15 Where H = high, or +5 volts. L = low, or volts. The output is also shown in Figure 3.3.3.2 (with S = L). Notice that the channel to the TTY normally requires a high input in the absence of a character transmission. This is achieved by the interface logic. The control logic, in its idle state, is in the receive mode, which inhibits any input to the interface logic. In the absence of an input the interface logic establishes the normally high output required by the TTY. This masks the fact that the inhibited input to the interface logic from the SROM is normally low in the idle state. The contents of the SROM are listed in Appendix B. 3.3.1+ The Bit-Wise Sequential Detectors They are shown in Figure 3.3.^.1. Their operation is straight- forward. They are all cleared prior to each input by a clear pulse from the bit sequencing logic. The data character is broadcast to each detector in a bit serial fashion. Each detector compares the data character with 1+1 Hard Wired Data Inputs Data Select r k t N Ee E 9 Em En E 12 E« E M Eis A B b 7 c E 6 E 5 E« E 3 E 2 Ei Eo S W D D Hard Wired Data Inputs a> -O o 3 Q. o o o O Figure 3.3.3.1 The SN7U150 Multiplexor i_n r~Lr TTY Character "l" Output of SN74150 n_ru" t L yiere Since E =L Figure 3.3.3.2 SROM Contents U2 + 5V-4 r w > w, > From SROM =X> ►Tr ► T, W 15 > • Tj = l =^No Match *T 15 Figure 3.3.^.1 Bit-Wise Sequential Detectors U3 one from the SROM which is also input to the detector in a hit serial fashion,, The comparison is achieved by the exclusive OR gate. A mismatch causes the FF to he set. The FF is strobed by the system clock to ensure alignment bet- ween the data bits and those from the SROM character. The point about align- ment is important as will be seen from Figure 3.3.2. The time slots of the bits output from the SROM are displaced hack in time with respect to those of the data character, due to the action of the bit sequencing logic. To compare bit h. in the input data character with bit b. in an SROM location, the com- parison must be made during the clock pulse, as this is the only time the two slots overlap. 3.3.5 The Character-Wise Sequential Detectors These are designated SMI, SM2 , SM3 and SMU as was noted previously. Their implementation is shown in Figure 3.3.5.1, 2, 3 and k. All four operate in essentially the same way. Basically, they contain a counter which counts the occurrence of certain characters appearing as input data, only at certain times. For example, in SMI, when the counter is in state 00, only the occurrence of a character N as input data will increment the counter. The occurrence of an N is indicated by the output T of the bit-wise detectors remaining low until the count 9 pulse occurs. In states 01 and 10 only the occurrence of number characters (0 through 7) will increment the counter » Finally in state 11 only the occurrence of a Rt character increments the counter. The occurrence of a Rt character in state 11 causes a output pulse on the SMI line concurrent with the count 9 pulse of the sequencing logic. This signifies that SMI has detected a type 1 instruction. If characters are input out of sequence they are ignored by the character-wise detectors; if the characters are not contained in the SROM kk + 5V + 5V SN74107 < Clear Line 1C SN74155 2C 16 2 " 4Llnf 2G 1Y3 1Y2 1Y1 lY(f + +5V »SM1 T 7 T 6 T 5 T4T 3 T 2 Tx T (0,1) Figure 3, 3 » 5.1 SMI U5 SM2«- SN7432 ▲ A c # + 5V ▲ J Q K C ^L 7) H SN7427 6 AA- ov A 16 +5V ▲ +5V J y SN74107 J Q 2C 1C SN74155 3-8 Line 1Y3 1Y2 1Y1 1YO 2Y3 2Y2 2Y1 2YO ttlj b~ -* Clear Line SN7408 CNT9 -+ Rt Figure 3.3.5.2 SM2 1+6 SN7408 CLEAR LINE OSM3 <3CNT9T_T < Rt [low level] Figure 3.3.5.3 SM3 UT SN7432 SN7427 <, CLEAR 1 LINE -O SM4 ■- 3> SN7408 3, >- O 2 3 >- o !d SN7402 3> "J^o^ER^lJ" 3^ Figure 3.3.6.1 (a) Error Routine Actuator SMI >- SM2 >- ERR >- SM3 >- ~| r To Cleor Line of •J Chor-Wise Oets. Figure 3.3.6.1 (b) Character-Wise Clear Generat or 51 A negative pulse on any one of Tx through Tx. sets the FF into transmit mode. The S. are brought high, inhibiting the SROM outputs, and the line (OP) is brought high, enabling the output of the interface gating. The line x is brought low, which starts the clock be setting the sync FF in the bit sequencing logic (see Figure 3.3.2.1). A cycle of eleven clock pulses is generated. The mode FF is reset by the negative count 9 pulse. During the cycle of eleven clock pulses a character may be trans- mitted along the bilateral data channel. The character is selected by bringing the appropriate address line low, when the mode FF is set to the transmit mode. For example, to transmit an E, line E (see Figure 3.3.7.1) is brought low. In the case of the numbers through 7, their binary repre- sentation is input into a 3-to-8 line decoder (the SN7^155) and the G line is brought low. In order to inhibit inputs to the control logic which come through the bilateral data channel during the transmission phase, a series of OR gates are connected to the input line in the interface gating (see Figure 3.3.7.2). These are controlled by the channels. When a channel is generat- ing a reply message to be output through the interface, it sets one of the 0R_. high, which inhibits the input data from the bilateral data channel. 3.3.8 Channel One This channel is responsible for generating a specified cube's coordinates. Figure 3.3.8.1 shows the N register which accepts the two octit number specifying the cube to be located. The bits b , b and b of characters two and three of type 1 instructions are shifted into the N register. This is achieved by shifting the two h bit shift registers with 52 G *1> # 2>- *3>- ED- BellO- Ltj> Lf 2 > Lf 3 > Lf, > RtO* Rx 2 >- Rx.O- SN74155 D z> CNT 9 ON Rxj "[_ SN7408 i=0 •3D- ;=0 =0 POINT A 6 SN7440 QQQ ->s f -OS, -os. -os. ->s 4 -os. -os, -os 7 -OSc ■OSu -os, -OS 15 Tx MODE V A A A A A A S 8 ,St,Sii.Si2 TxjTkz Tx 3 Tx 4 Tx 5 Tx 6 "j Figure 3.3.7.1 MA and Mode Logic 53 220ft 5470ft 1/4W 2N3642 390ft S 680ft 1/4W kTkl kl kl 6 3> SN7432 Input Data 6 AAAA AAAA AAAA AAAA A A R2 A A A rs W W, W 2 W, W 4 W 9 W 6 W 7 W 9 W 9 W I0 W,| W I2 W I3 W I4 W IS 0R1 0R3 0R4 v , ; Outputs from SROM Figure 3.3.T.2 Interface Gating 5k System CK ► CNT1 ► CNT2 ► CNT3 ► SMl(lYl) ► SN7404 SMK1Y2) * T>0 < Data Input The N Register R-Shift Clock SN7495 Figure 3.3.8.1 The N Register 55 the count l, count 2 and count 3 pulses from the bit sequencing "board. The condition that these hits come first from the second character and then from the third input character is achieved first by enabling the set of shift pulses to one of the k bit shift registers with the SMI (lYl) logic level, which is low only when the second character is input, and they by enabling the set of shift pulses to the other h bit shift register with the SMI (1Y2) logic level, which is low only when the third character is input (see SMI, Section 3.3.5). The system clock is used to strobe the input data to the N register; this is to achieve the correct alignment in time. It will be seen from Figure 3.3.2 that the time slots generated by the bit sequencing logic are displaced back in time with respect to those of the input data characters. Only during the clock pulses do they align. Upon the receipt of a Type 1 instruction the N register will contain the six bit representation of the two octit number specifying the cube. This is so because the bits b , b and b of the TTY numeric characters through 7 are the binary encoding of those characters (b = LSB). The channel flag is set by the SMI pulse if a Type 1 instruction is detected and the power transmitter is pulsed for lmS. The logic that accomplishes this is shown in Figure 3.3.8.2. Setting the flag also inhibits the input through the interface gating, by bringing line OR high. If the instruction is not Type 1 the channel flag will not be set and thus, the con- tents of the N register will be ignored. 56 Clear > E Clear > 0R1 Power Transmitter SMI > P Line > XTAL Clock Figure 3.3.8.2 Channel One Logic 57 When the power transmitter has completed its transmission, the signal on the P line causes counters A and B to be loaded. Counter A is loaded with 1000000 and counter B with (N N, N N N N ) , the binary code representing the cube that is to be detected. As soon as the counters are loaded the OR gate controlling the crystal controlled clock signal is enabled and the counters begin to count down. When counter B reaches two's complement one (i.e. 11111111 ) , the line Q is brought high for one period of the crystal controlled clock. This enables the coordinate buffers dur- ing the (NJJJJ L +l) time slot after the cessation of the power transmission. A time slot is one period of the crystal controlled clock. -th If the N cube is in play, it will reply during this time slot; hence, its coordinates will be entered into the coordinate buffer. If the N cube is not in play, the coordinate buffer will contain all zeroes. A time slot of 128ys was intended (see Figure 2.3.1); thus the crystal controlled clock must have a frequency of: 1000 kHz * 7.5 kHz 128 In the Section 2.3 an analysis on the tolerance of the RC time constant used in the cubes was carried out. A bound of +0.8$ on RC was established. This analysis assumed the time slots were equal. This is not true. However, by using a crystal controlled clock the worst case cumulative error after 63 time slots can be kept as low as +6k x 10" time slots/°C without any difficulty. Over a U0°C operating range this represents 58 T*-, <> REPLY t>- £r & 16 OV 1—26 2C 1C SN7415S 3-8 LINE 1Y3 1Y2 1Y1 1YO ZY3 2Y2 2Y1 2YO ■-D* RtLt ACTUATOR £* t>- Or t> t> -O- -OLf! -C> 1 -O 2 -t> 3 -t> 4 -t> 5 -O 6 -O G Figure 3.3.8.3 Channel One Reply C, 59 -k +2.5 x 10 time slots i.e. +0.0025$ This is negligible in comparison to +0.8% and may "be ignored in the analysis to tolerance RC. When counter A reaches two's complement one a reply signal is gen- erated which initiates the transmission of the reply message down the bilateral data channel. One time period later, when A reaches two's complement two, the cyrstal controlled crystal clock's signal to counters A and B is inhibited and counting ceases. The logic to generate channel one's reply message is shown in Figure 3.3.8.3. The reply pulse clears the 3 bit ripple counter and enables the 3-8 line decoder by bringing the decoder's strobe, 1G, low. A negative pulse is simultaneously sent down the Tx line. This sets the MA and Mode Logic to transmit mode, which starts the system clock on an eleven pulse cycle. Since the memory address line Lf is initially low, the non-printing character Lf is output. The mode FF is reset by the count 9 pulse, and the count 11 glitch which occurs immediately after the Lf transmission increments the ripple counter, and sends a negative pulse down the Tx line to set the mode FF to transmit mode once more. This time line 1 is brought low, and a 3 bit number in the coordinate buffer (see Figure 3.3.8.U) is input to the MA and Mode logic's 3-8 line decoder (see Figure 3.3.7.1). This results in the TTY numeric corresponding to the 3 bit number being output. This action is repeated five times so that all the six octits which uniquely describe the cube's position on the table top are output. The 3-8 line decoder in the MA and Mode Logic will not address the TTY numerics in the SR0M unless it is 60 Line P Q T L ? ? T T T T T ? 60666000666HHH SN7408 Coordmote Buffers DDODDD .1 <► U SN7486 #3 #2 *i Figure 3.3.8.U Gating Between Buffers and MA Logic 6l enabled by bringing line G low. During the transmission of the six octits this line is held low by the NAND decoder in the channel one reply logic. Figure 3.3. 8, h shows the gating between the coordinate buffers and the MA and Mode Logic. The buffers contain the coordinates in Gray code (see Section 2.3). This is converted into binary by the exclusive-OR gates shown in Figure 3.3.8.H. After outputting a cube's coordinates the channel one reply logic sets channel seven to go. Channel seven outputs the two non-printing char- acters Rl Lf which completes the operation of channel one. Channel seven is also responsible for clearing the channel one flag after it has transmitted Rt Lf. The transition cycles that occur in the ripple counter used in the reply logic are not critical. They will cause incorrect addressing of characters in the SROM, but only for a brief period during the time it takes to output a character's first bit b . For all TTY characters b = 0; hence, incorrect addressing during bit b. is unimportant. 3.3.9 Channel Two This channel is responsible for moving the hand-arm limb to the coordinates requested by the Type 2 instructions. Figure 3.3.9.1 shows the six h bit shift registers that accepts bits b , b and b of each numeric in the six octit number of the Type 2 instructions. The six octit number specifies the coordinates to which the hand-arm must be moved. The correct entry of bits b , b and b into the shift registers is achieved by shifting the h bit shift registers with the count 1, count 2 62 Data IP >- System Ck. >- CNT1 > CNT2 >- CNT3 >■ SM2(2Y1) >- SN2(2Y2) >■ SN2(2Y3) >- SN2(2Y0) >- SN2(1Y1) >- SM2(1Y2) > > SN7410 SN7404 t>— =O^I> £>— =0=0 0-^0=0 SN7408 i>^^o=o o— =O^D 0-^=0^0 R-Shift Clock Figure 3.3.9.1 The k Bit Shift Registers 63 and count 3 pulses from the bit sequencing "board. The condition that these "bits come first from the second character, then from the third character, etc., is achieved first by enabling the set of shifting pulses to the first of the h bit shift registers with the SM2(2Yl) logic level, which is low only when the second character is input, and then by enabling the set of shift pulses to the second k bit shift register with the SM2(2Y2) logic level, which is low only when the third character is input, etc. (see Figure 3.3.9-1). As in channel one the system clock is used as a data alignment strobe. Should the input characters prove to be in an input sequence that is not a Type 2 instruction, the channel two flag will not be set; hence the incorrect data in the shift register will not be used. Upon the receipt of a Type 2 instruction the six k bit shift registers in Figure 3.3.9.1 will contain the 18 bit representation of the six octit number specifying the point on the table top over which the hand- arm should position itself. (Each shift register contains 3 of the 18 bits in its three least significant bit positions). The channel flag is set by the SM2 pulse if a Type 2 instruction is detected and a positive pulse SM2* is generated by the logic shown in Figure 3.3.9.2. This transfers the 18 bit coordinate description from the shift registers to the transfer buffer shown in Figure 3.3-9.3. The trans- fer buffer can be regarded as two 9 bit buffers, ore containing the x-coordinate and the other the y-coordinate. Each of these, after D/A conversion, form the input to the hand servomechanism and to the arm servomechanism, as depicted in Figure 2.2.2. When both the error voltages driving the servomechanisms are within one Ge diode drop of ground, the one-shot in the logic of Figure 3.3.9.2 is 6U Channel 2 CH2 Flag OR, rrS <3 3>i SN7432 3^ 470 £1 1N4148 (Si) ~ -< ECLEAR ■< CLEAR < SM2 < EFLAG Figure 3.3.9.2 Channel Two 65 OV ♦ 10V SM2' > f- x,(2) > x,(l) > x 2 (0) > Xi(2) > X, (1) > x, (0) > MO) > Y (2) > v (l) > Y (0) > 10 Turn 5*fl 0.1% HELIPOT » *« Error Signal to Drive Arm HELIPOT Actuated By Hand -Arm Position (Set Fig 2.2.2) Error Signal to D'ive Hand Figure 3.3.9.3 The Transfer Buffer and Servomechanism Drivers 66 ; triggered and channel five (transmit Lf Bell) is actuated, indicating the completion of operations for channel two. 3.3.10 Channels Three and Four The operation of channels three and four are logically similar. Channel three is responsible for the raise/lower motion of the hand, and channel four controls the open/close aetion. Channel 3 is shown in Figures 3.3.10.1 and 3.3.10.2. The bits b , b and b of the first accepted character are input to the h bit shift register. This is achieved by shifting the shift register with the count 1, count 2 and count 3 pulses from the bit sequencing board. As in channels one and two the system clock is used as a data alignment strobe. The condi- tion that these bits come from the first input character is assured by enabling the whole set of shifting pulses with the SM3(lY0) logic level which is low only when the first character is input (see SM3, Section 3.3.5). Should the first input character prove to be in a sequence that is not a Type 3 instruction the channel three flag will not be set (it is set by the SM3 pulse; see Figure 3.3.10.2); hence the incorrect data in the shift register will not be used. The data in the register indicates whether a raise or lower action is to be carried out. An L indicates lower and an R a raise action. The TTY characters for L and R begin as follows: b o b i b 2 b 3 L: 1 R: L°_ 1 ~*v — These three bits are shifted into the register, with b occupying the low order position. Hence a 1 bit in Q indicates L and a 1 bit in Q B indicates R (see Figure 3.3.10.1). 61 Data Input >■ System Ck. >- CNT 1 > CNT 2 > CNT 3 >- SM3(1Y0) >- SN7410 SN7404 £~ 43 SN7495 4> Serial Input Qa R-Shlft Clock ->L ->R Channel 3 ( Raise/Lower) Dato Input >- System Ck. >- CNT1 > CNT2 > CNT3 >■ SM4(1Y1) >■ g D>~4l> t)- Striol Input R-Shift Clock Ob Oc o £~ ->1 ->0 Channel 4 (Open /Close) Figure 3.3.10.1 Channels Three and Four 68 : The remainder of the channel logic (see Figure 3.3.10.2) effects the action required and generates the reply message. The channel flag is set by SM3, bringing the OR line high, which inhibits inputs through the interface. The count 10 pulse sets either the UP FF or the DOWN FF depending on "whether an R or an L has been received. The outputs of these FF's are compared with a FF which indicates the current status of the hand (i.e. either raised or lowered). This FF is set by status micro-switches which detect the hand's position. The comparison between the desired state, as indicated by the UP or DOWN FF's, and the actual state is achieved by two AND gates, whose outputs control the raise/lower motor in the hand. When the desired state has been reached, channel 5 (output Lf Bell) is set to go, and the UP and DOWN FF's are cleared. Channel k is shown in Figures 3.3.10.1 and 3.3.10.3. The opera- tion is identical to channel 3. The input which determines whether to open or close the fingers is the second character of a Type k instruction. Hence, in channel k the shifting is only enabled when the SM^(lYl) logic level is low (see SMU, Section 3.3.5). Receiving a "l" character indicates the fingers should be closed, and a "0" character indicates they should be opened. These two characters differ in the b bits; hence, the simple decoder, 3.3.11 Channel Five This channel causes the output of the two non-printing characters Lf Bell. It is actuated by a negative pulse from either channel 2, channel 3 or channel h. The logic diagram for the channel is shown in Figure 3.3.11.1. 69 0R3<- CH3 FLAGO- LOW CNT 10 t>- U R O- L >- -C>UP -C>0OWN "LT -> ACTUATE Lt BELL Figure 3* 3.10.2 Channel Three Raise/Lower Actuator TO 0R4O- FLAG■ IT >■ 1 t>- <3 OPEN D rJS- 1 ,^-J CLOSE <3 CHANNEL 4 FLAG <£ ■< SM4 t ^^ -O OPEN -O CLOSE IT -> ACTUAT LtBEL Figure 3.3.10.3 Channel Four Open/Close Actuator 71 The channel FF is set by the actuating pilse from channel 2, 3 or k. The mode FF in the MA and Mode logic is set to transmit mode by a. negative pulse on the Tx line. The Lf line is brought low and a Lf character is output. The count 11 glitch toggles the JKFF and resets the mode FF to transmit This time the Bell line is brought low and a Bell character is output. The count 9 pulse that occurs when the sequencing logic outputs the Bell character from the SROM resets the channel FF and clears the flags for channel 2, 3 and k. The transmission is complete. 3.3.12 Channels Six and Seven Channel 6 is responsible for outputting the first part of the error message, Lf E, and then actuating channel 7 which is responsible for output- ting the last part, Rt Lf. Channel 7 is also actuated by channel 1, which requires Rt Lf to be output to terminate its transmission. The logic diagrams for channel 6 and 7 are shown in Figure 3.3.12.1 and 3.3.12.2. Their operation is similar to channel 5. However, channel 6 employs a slave flag which is not reset until channel 7 has completed its operations. This maintains line OR high so that input through the interface gating is inhibited during the transmission of the Rt Lf characters by channel 7. None of the other OR. will be high at this time, because channel 6 resets the channel flags for channels 1,2, 3 and h, by outputting a posi- tive pulse on the ECLEAR line. This is cbne at the same time that it actuates channel 7. The four channel flags above control the levels of OR , OR , OR and OR, . In the case when channel 1 actuates channel 7, OR is held by channel 1 so that input through the interface gating is inhibited. 72 Tx 2 <- ACTUATE FM CH2C- CH3>- CH4t>- "POWER ON"- CLEAR ^ CNT110- CLEAR CH2 CH3.CH4, FLAGS CNT9 >■ O CHANNEL FF pL>-| =€>• < a A Lf BELL GENERATOR o c J Q C K Q BELL Ltj Figure 3.3.11.1 Channel Five C 73 This is the Controlling Flag Used to Avoid Hazords. ERR >- 'Power On" Clear E or CH6 Flag Error Message Generator CNT11> Tx, E Clear « For CH2.CH2 CH3.CH1.CH4 CNT9 > Slave Flag > OR5 < Clear Figure 3.3.1L.1 Channel 6 lh FM CHI Reply > FMCH6 > "Power On" Clear CNT11> Clear CHI Flag <-°T_ J " Clear Slave Flag CH6 CNT9 >- Rt. Lf. Generator j 3° — >Tx4 Rt Lf 2 Figure 3.3.12.2 Channel Seven C 75 Notice the EFLAG line in channel 6. When this is low the actions of all the four major channels are inhibited until the error message is transmitted, after which the ECLEAR line is pulse positive to reset the flags of channel 1,2,3 and h. This is useful during a cold start. If the channel 6 flag can he forced to set when a "power on" situation occurs and the channel 5 flag and channel 7 flag can he forced to reset when a "power on" situation occurs, a cold start would always he characterized by the flags of channels 1, 2, 3 and k being cleared followed by an error message being output. The generation of a "power on" state is achieved by using the cir- cuit shown in Figure 3.3.12.3. 76 + 5V + 15V 10k& -,-lOOpF ; 2N3642 "Power On" * Clear Line Relay (Single Pole Double Throw) i 6 ► +5V Figure 3.3.12.3 "Power On" State Gene rax or 77 k. SPECIAL CIRCUITS: THEIR DESIGN AND OPERATION In this section the design and operation of three types of special circuits used in Semantrix are discussed. They represent the only non-digital circuitry in the machine, and are all employed in cube location. In order of presentation they are: 1. The threshold circuits. 2. The cube's receiver/transmitter. 3. The power transmitter. U.l The Threshold Circuits There are two arrays of 89 threshold circuits in Semantrix. One array detects the x-coordinate, the other the y-coordinate (see Figure 2.3.1). Each circuit detects a differential voltage induced across the loop that it services. The circuit schematic is shown in Figure U.l.l. A differential voltage pulse of a few mV at the inputs appears at the output amplified lOOOx. However, an a.c. path between points A and B enables the output pulse to regenerate, since it is fed into the + input of the op-amp, resulting in further amplification until the op-amp saturates. The diode clips the negative going part of the regenerating pulse, giving a "square-up" 0V-15v pulse on the output. The diode also performs the thres- holding action. For regeneration to occur the differential voltage pulse, amplified lOOOx, must forward bias the diode. This can only be accomplished if the amplified pulse is more positive than the d.c. voltage at B. A bias network can be adjusted to time the threshold bias on all the circuits simultaneously (see Figure U„1.2). It should be adjusted to reject the ambiant noise input pulses which are less than 5mV. 78 CD "O c ° O & •~ ii o c •— c ° E o o o o -J O 0) - 1 s 3 Q. a> a) o a cl a. en ou ^ 2 (CM 3 O t= VW j|i -p •H O •H O TJ H O m 0) Sn EH o -p a3 B o •H r 19 CO c T3 < O O CD O v -xx xx ° c en IN ^ CT> rO ^ to > o» (J > 2 o to x: .t: IT) r-H + ■A^r Hi' cj or o <£ ^ 00 C\J > 10 00 1 ■w — |n >5 tv* in CD +1 *" £ to Ql «" O 2 ■— 1 O _J <\J CO L. to 0) -0 CO CO CD or < < CO U CD X) O o cu p ca o -p o cu p 0) p 0) p O P a CD s CD CM 0) •H En 80 Figure U.1.2 also shows the level changers that convert the 15v pulse to one suitable for driving TTL logic loads. k.2 The Cubes' Receiver /Transmitter A cube receives the energy from the power transmitter, through its receiving coil. This energy is stored electrically in two O.OhjyF capacitors (see Figure U .2.1) . The cube's transmitter operates "by utilizing this stored energy. The manner in which energy can he obtained from the store is regulated hy a 1N962B Zener diode. The cube transmits a pulse of magnetic energy hy releasing the charge stored in the two Q.0U7uF capacitors through a coil L (the transmit- ting coil). The release of the charge is controlled hy two transistors, Q2 and Q3, which function together like an SCR. When the point A is Drought near enough to ground Q2 turns on, which turns on Q3. Turning Q3 on causes Q2 to he turned on harder i.e. a regenerative process is established. This gives a very rapid turn-on, which enhances the di/dt through the transmitting coil, and hence the differential voltage input to the threshold detectors. The SCR formed by Q2 and Q3 is fired when Ql turns on. This is achieved in a controlled fashion by the RC charging network. Figure U . 22 shows the expon- ential charging ramp for the RC network. The RC charging network does not begin charging positive until the power transmitter has stopped. This is due to the action of the three diodes connecting points B and C. These form a short circuit when the induced voltage at C swings negative, holding one side of the capacitor at A to -(V-3d) volts until the power transmitter stops C If) o ro 81 >> u •p •H O •H X Eh 0) C\J so •H u. Q- o IT) 82 I > o CD o *- c/> O (/) £ if) "O c CD o s— CD ^_ n CD £ c O T3 ro > T 83 and the inducted voltage at C goes to ground. The three diodes are then reversed biased and point B is essentially disconnected from point C. It can then start charging positive. The voltage V is the peak voltage induced in the receiving coil of a cube and is not necessarily the same for each cube, nor is it the same for a particular cube at different points on the table top. The forward bias voltage drop of a pn-junction is denoted by d volts, and this is taken to be the same for all pn-junctions. In general d is a function, and in particular d = d(Temp.). Since the RC charging network does not begin charging positive until the power transmitter has stopped, the time out to firing for every cube begins at the same instant. Furthermore, since each cube is identified by the time slot it replies in (see Figure 2.3.1(a)), cubes can be distin- guished simply by choosing a unique value of the time constant RC for each cube. The time out to firing, T can be computed as follows (see Figure U.2.1): Initial voltage at B due to the induced a.c. signal at C = -(V-3d) Final voltage at B = Voltage due to charged stored on the 0.0UT M F capacitor C = V-d i Ql turns on when its base = d volts. Hence the equation for the time out to fire is given by: Qk (2V-Ud)(l-e" t/RC ) - (V-3d) = d (2V-l+a)(l-e" t/RC ) = V-2a 2 (i- e - t/RC ) =1 -t/RC 1 T OUT 2 RC In 2 Two points of interest arise from the above calculation. The first is that by using three aioaes to connect points B and C the aioae arops cancel out, eliminating temperature effects. The secona is that the value of T is inaepenaent of V a highly inconsistant quantity. U.3 The Power Transmitter The circuit schematic for the power transmitter is shown in Figure U.3.1. The circuit is basically a Colpitts oscillator, which is switched on for a preaeterminea perioa of time by a monstable one-shot. The inauctor in the tank circuit of the oscillator is formea from a 1/2" x l" copper bar, which has been maae into a UO" square loop. This is laid round the edge of the table top flush with the surface. The magnetic field generated by the oscillating current in the loop is the medium of communica- tion with the cubes. This field is perpendicular to the table top. The Colpitts oscillator is formed from transistor Q6 and the tank circuit. The inductance of the loop is about 25yH, which gives the oscillatoi an operating frequency of about U80kHz. The voltage swing on the collector of Q6 approaches twice the power supply i.e. 200 volts; hence Q6 must have a high v CB q- Furthermore, because the tank circuit has a very low Q, large bursts of current must be input through Q6 during each cycle, to sustain oscillations. Therefore, Q6 must have a high I PMAV . The 2N^2U0 device used for Q6 satisfies these requirements, having V = 300 volts and I_„._ = 6A. 0B0 CMAX 85 in r-t 10 P^U—^v-^gV JU £ > m o d 8 ^-i oj ro * m o o o o o -p -p •H e u En Sh &H on o 0) §> •H 86 Transistor Q5 provides a constant current source to bias Q6. It also provides a means to turn off the transmitter. By bringing the base of QU to ground, QU and Q5 are turned off. The emitter of Q6 is then returned to +5 volts through the 330ft resistor. This means Q6 is turned off since V =0 volts. Turning off Q6 is turned off since V„„ = volts. Turning BE •D-k off Q6 breaks the closed loop of the oscillator and the oscillations cease. (Quite rapidly too, since Q is so low). To commence transmission to a 5 volt pulse in input at the start terminal. This turns on Ql and trips the one-shot formed by Q2 and Q3. The on time of the one-shot determines the duration of the oscillations. The on time is given by: t 0N = RC in l.T Now C = luF Therefore t = R x 0.53 mS Where R is in kilo-ohms. The duration of oscillation that is required is about lmS. Hence a resistance of about 2kft is required. This can be got by adjusting the lOkfi variable resistor. The power dissipation of Q6 demands that the oscillator be kept to a 10$ duty cycle; thus it is important that noise on the +5 volt power line caused by pick-up from the oscillator or anything else does not retrigger the one-shot. For this reason three capacitors decouple the +5 volt supply on the board containing the oscillator. One is a 500mF electrolytic, which copes with low frequency noise. Due to its construction, at high frequency 87 it no longer "behaves as a capacitor, but as an inductor. For this reason a 2.2mF ceramic capacitor is also used. Finally, it too has a high frequency safeguard which is a 200pF ceramic capacitor. 88 5. THE ELECTROMECHANICAL LIMB In this section the design of the electromechanical hand-arm limb is discussed. Although this subsystem was not the responsibility of the author a brief description has been included for completeness. The major part of the limb design is connected -with generating the x-y motion. 5.1 Generating the X-Y Motion Both of these motions use a torque proportional to error servo- mechanism. An ideal torque proportional to error servo is diagrammed in Figure 5. 1.1. The error is defined as the difference between the required output (i.e. input 6.) and actual output . The system inertia is J referred to the output and the system is damped by means of a viscous damping torque F per unit angular velocity. Now the torque from the motor is T = K£ m Retarding torque due to damping de o T f = F d^ Resultant torque T to produce acceleration is given by T = T - T m f ■ K(9 i - e o ) - F 3ir But by Newton's second law T a J 2. dt 89 POWER Output Shaft (Rigid) Light Damping Paddle K Amplifier Controller Motor (Output Element) Hand Wheel Input Shaft (Rigid) Error Detector Feedback Loop Mass (Load) Figure 5.1.1. Proportional to Error Servo Time t Figure 5»1»2 Response to Step Input I ▲ 90 W= 00 w -> Figure 5.1.3 The Nyguist Plot for the Limbs Servbmechanisms 91 Therefore J — ~ + F + KB = K9 dt dt Which is the differential equation describing the ideal system. In so far as this ideal analysis models the actual system, the main point of interest is the response of the system to a step input. There are three possible types of response: 1. Underdamped. 2. Critically damped. 3. Overdamped. The solution to the system differential equation in case 1 is: / 2 -1 -at A r a ] n r ^\ ] j / 1 + — J sinfw t + tan — } J ' = 9. [1 - e / (1 + [ — J siniw t + tan — > i w r a r And is depicted in Figure 5.1.2. F 01 " 2J k w = ► — - r J F 2 And Two confliciting constraints arise at this point. On one hand, it is desir- able to have an underdamped (or critically damped) system, so that the response time of the system is not unduly large. This requires w to be real; that is 2/JK~> F On the other hand, to minimize the settling time, a should be large; that is, F >> J The actual system was shown in Figure 2.2.2. To identify the quantities J and F entails considerable measurement and calculation, and for a two off system, is not worthwhile. It is sufficient to know that increasing 92 F increases the settling time, and increasing J increases the under damping. K is given in manufacturers specifications. Both motors used were high per- formance d.c. motors manufactured by Micro Switch. The limb was powered by a model 6VM1-1 and the hand, which moves on the limb, by a model 3VM1-1. The open loop transfer function for the system is given by: Where K 1 = K/F T = J/F A plot of this on an Argand diagram gives the Nyquist plot. This is shown in figure 5.1.3. Since the plot never encloses the (-1, 0) point, no matter what the values of T and K are, the system is unconditionally stable - a very desirable feature. For a complete discussion of stability and servo- mechanism see Reference 2. 5c 2 The Hand's Motions As well as the y-motion along the arm the hand has two other motions ' associated with it, as was seen when the instruction set was discussed in Section 3.1= These are raise/lower and open/close. The raise/lower motion is effected by a small d.c. motor running on open loop. Sets of control switches turn the motor off when the raised position or the lowered position has been reached. The directions of the motor are also determined by these switches. (See Section 3.3.10 for a dis- cussion of these switches). The open/close motion of the hand's fingers is achieved in a similar fashion. The hand has two opposed fingers. These pick up the cubes by grasping a small protruding length of dowel which is to be found on the top of each cube. 93 6 . CONCLUSION This report describes the design of a special purpose piece of computer peripheral equipment called Semantrix. ■ The emphasis of this report has been on the system logic, this being the major responsibility of the author . 9U LIST OF REFERENCES 1. Ambler, A. P., Barrow, H. G. and Burstall, R. M. : Some Techniques for Recognizing Structure in Pictures . International Conference on Frontiers of Pattern Recognition, Honolulu, Hawaii, January 1971- 2. Atkinson, P. : Feedback Control Theory for Engineers . Heineman Educa- tional Books. London, 1968. 3« Morris, R. L. and Miller, J. R. : Designing with TTL Integrated Circuits . Texas Instruments Electronics Series, McGraw-Hill. 1971. k. Preparata, F. and Ray, S.: An Approach to Artifical Nonsymbolic Cognition , Information Sciences, Vol. h (1972), pp. 65-82. 5. The Integrated Circuits Catalog . Texas Instruments Inc. Dallas, Texas „ k 95 APPENDIX A The Clock Operation Figure A.l shows the clock circuitry. The hex inverters are SNT 1 +05's. The ratio of on to off time is almost unity, as will be shown "below, and is unaffected by the value of the capacitor, which can be choosen to generate frequencies from below 1 Hz. Figure A.l shows the central part of the circuit relevant to under- standing how it works. Q n is the output transistor of the leftmost inverter, and Q, is the input transistor of the rightmost inverter. Suppose that node b has just gone low, so that c is high and is in saturation. Node a is then clamped at V (~ 0.2V) and the L/HjS cL"C voltage at node b rises exponentially towards V -V-™ with time constant CR, . When node b reaches the threshold voltage V (- l.Uv) required to switch Qi , node c will go low, turning off Q_. The current in R , which formerly flowed via the emitter of Q into Q_, can now flow only into the base of Q p and the left side of C. Thus, Q and Q~ turn on, causing the voltage at node a to jump to V . This step is transmitted through C to node b, causing it to rise to 2V -V . Q , Q and Q now behave like an operational amplifier. Q_ and Q are on, but not saturated. Aside from a small base current into Q , most of the current in R flows via the emitter of Q and C into Q . Should this current tend to increase, thereby lowering the voltage at node a, the base drive at Q 9 will be reduced, tending to turn Q„ and Q off, which in turn will tend to block the passage of current into Q^ from C and pull the voltage at node a up again. A similar argument applies if the voltage at node a should tend to rise. This voltage, therefore, is 96 v C c (Out) v C c "-- R iS 4k R 2 <1.6k f — 1 w i R 4 £4k R*£lk 4/ V. tv, CE sat Exponentia CE sat r V, * \, CC V, CE sat Figure A.l The Clock Circuitry C, 91 clamped at V ("by negative feedback through C). Hence C receives a constant current from R , which causes the voltage at node b to fall linearly. When it reaches V , Q, switches back to its former state, node c goes high, Q saturates, snapping the voltage at node a and, via C, node b back down to V , at which point the cycle is complete. The waveforms at the three nodes are shown in Figure A.l. From the above reasoning one may readily obtain the on and off times t and t , if one neglects the switching times of the individual transistors and the base current into Q p when it is on. V - V - V , ^ n cc BE CEsat t, = OR, ion J l " k V - V__ - V cc BE 1 V - V 2 IV - V__ - V 4 cc BE 1 Nominal values are R n = R, , V = 5V, V^„ = 0.8V, V = 0.2V 1 4' cc BE ' CEsat and V = 1.4V. These yield the ratio: t 1 /t 2 a 0.83 - 5/6 If equal on and off times are needed, t p may be reduced, without affecting t , by connecting a suitable resistor between node a and V . This J. rr CC should be about 26k when R = R, = 4k. 98 APPENDIX B The Contents of the SROM TTY N CHARACTER E 8 E T E 6 E 5 E u E 3 E 2 E l 1 1 1 1 1 1 1 1 2 1 1 1 1 3 1 1 1 1 1 h 1 1 1 1 5 1 1 1 1 1 6 1 1 1 1 1 7 1 1 1 1 1 1 C 1 1 1 1 E- 1 1 1 1 L 1 1 1 1 N 1 1 1 1 1 R 1 1 1 1 Bell 1 1 1 1 Lf 1 1 1 Rt 1 1 1 1 E =0 E 9 * E 10 " 1 E — E leave floating. 1 corresponds to ground. corresponds to a connection to +5 volts. j* Non-printing The ROM is fabricated "by placing k SN7Hl50's per printed circuit "board. A total of h such boards are thus required to make up the memory. The boards are all made with an identical layout, which is programmed so that each of the SN7^150's can be wired to store any TTY character required. The C, 99 E. of each multiplexor can "be connected to +5 volts or volts by soldering a small jumper pin into the appropriate hole. orm AEC-427 (6/68) AECM 3201 U.S. ATOMIC ENERGY COMMISSION UNIVERSITY-TYPE CONTRACTOR'S RECOMMENDATION FOR DISPOSITION OF SCIENTIFIC AND TECHNICAL DOCUMENT / See Instructions on Reverse Side ) . AEC REPORT NO. 000-1469-0217 2. TITLE SEMANTRIX J>y_ A Semantic ally Guided Digital Electronic Machine Trevor Nigel Mud^e i. TYPE OF DOCUMENT (Check one): □ a. Scientific and technical report ^] b. Conference paper not to be published in a journal: Title of conference __^______^^____ Date of conference Exact location of conference Sponsoring organization c. Other (Specify) Thesis Research 1. RECOMMENDED ANNOUNCEMENT AND DISTRIBUTION (Check one): [xj a. AECs normal announcement and distribution procedures may be followed. 1] b. Make available only within AEC and to AEC contractors and other U.S. Government agencies and their contractors. 3 c. Make no announcement or distrubution. REASON FOR RECOMMENDED RESTRICTIONS: i. SUBMITTED BY: NAME AND POSITION (Please print or type) W. J. Poppelbaum Professor and Principal Investigator Organization Department of Computer Science University of Illinois at Urbana-Champaign Urbana, Illinois 6l801 Signature 4< ?. Pa/a,^ Date February 1973 FOR AEC USE ONLY AEC CONTRACT ADMINISTRATOR'S COMMENTS. IF ANY. ON ABOVE ANNOUNCEMENT AND DISTRIBUTION RECOMMENDATION: PATENT CLEARANCE: J a. AEC patent clearance has been granted by responsible AEC patent group. U b. Report has been sent to responsible AEC patent group for clearance. LJ c. Patent clearance not required. E3LI0GRAPHIC DATA SEET 1. Report No. UIUCDCS-R-73-559 3. Recipient's Accession No. 4 Title and Subtitle 5. Report Date February 1973 SEMANTRIX: A Semantically Guided Digital Electronic Machine 7 Author(s) 8. Performing Organization Rept. No. UIUCDCS-R-73-559 9 Performing Organization Name and Address Department of Computer Science University of Illinois at Urban a- Champaign Urbana, Illinois 6l801 10. Project/Task/Work Unit No. COO-1U69-0217 11. Contract /Grant No. US AEC AT(ll-l)lU69 1 Sponsoring Organization Name and Address US AEC Chicago Operations Office 9800 South Cass Avenue Argonne, Illinois 60^39 13. Type of Report & Period Covered Thesis Research 14. 1 Supplementary Notes 1. Abstracts Semantrix is a digital machine, whose domain of activity (or world) is a rectangular plane or table top. (See Figure 1.1.1 for a diagram of the machine). Its activity in the plane can be instructed from either a teletype or a digital computer. Semantrix and a teletype can form a stand alone system. However, to make full use of the machine, a digital computer should be used as a controller. Semantrix can thus be viewed as a special piece of I/O equipment. . Key Words and Document Analysis. 17a. Descriptors cognitive system special purpose digital controller semantrix two dimensional position locating system b. Identifiers /Open-Ended Terms e. ( osati Field/Group • Availability Statement unlimited distribution L RM N TIS- 33 ( 10-70) 19. Se< urity C lass (This Report) UNC1.ASS1MHD 20. Security Class (This Page UNCLASSlFlt-.D 21. No. of Pages 105 22. Price USCOMM-DC 40329-P7I ■ < ?9 1973