LIBRARY OF THE
UNIVERSITY OF ILLINOIS
AT URBANA-CHAMPAICN
5/0. 84
iJHor
no. 37/- 373
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Digitized by the Internet Archive
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371
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December 1969
Graphics 8
Graphics Hardware - IU69 Gear
by
C. E. Carter
R. Hostovsky
H. Levin
H . Lopeman
R. Miller
TUC
IK
UHW."
DEPARTMENT OF COMPUTER SCIENCE
UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN
URBANA, ILLINOIS
r o
r
Report No. 371
Graphics 8
Graphics Hardware - 1U69 Gear*
by
C. E. Carter
R. Hostovsky
H . Levin
H . Lopeman
R. Miller
December 1969
Department of Computer Science
University of Illinois
Urbana, Illinois 6l801
Supported in part by grant U. S. AEC AT(ll-l)lU69
? >
/iit>
Graphics 8
Graphics Hardware - 1^69 Gear
CONTENTS
Introduction
page
1
Basic System
1. PDP-8
2. ASR 33
3. Dec tape
k. PBD-338
5. Interval Timer
k
15
19
22
31
Operating Additions 32
1. PDP-8 to 630 Interface 33
2. Data Disc 35
3. Data Tablet (Sylvania) ^5
k. Music Generator 51
5. Push Button Bootstrap 52
6. Illiac III Interface 5^
7. 2701 Parallel Data Adapter 55
8. Microswitch Keyboard 58
Proposed Additions
1. Inktronic Printer
2. Display Processing Unit
60
61
71
Appendix A
1. Alphabetic IOT List
2. Sequential IOT List
75
75
79
Graphics 8
Introduction
This report was written for two reasons. The first was to serve
as a reference manual for the lU69 group in their everyday graphics work.
The second was to serve as an applications manual for use by those University
people who make use of the graphics facility.
The report is divided into three parts: basic system, operating
additions, and proposed additions. The basic system made up of a 16K-PDP-8
with interval timer, an ASR33 Teletype, 2 ea Dectapes , and a PDB-338 was
installed and checked-out in June of 1967 • The operating additions have
been made over the past two years. The proposed additions are being worked-on
for purposes of making the total facility better for user applications.
The items that make up the individual parts are described in this
report and/or reference is made to another report for a more detailed
description.
Figure 1 is a configuration drawing of the Graphics 8 hardware.
The four quadrants contain devices, controllers or interfaces corresponding
to the title of the quadrant. The three communication interfaces have
been particularly useful in enhansing the PDP-8 capabilities for graphics
developments and user applications. The Graphics (system) is the present
basic system tools for graphic work on the PDP-8. The Graphics (applications)
is the developmental project for expanding the user facilities of the PDP-8.
The local 1/0 contains the various low-speed devices access able to the
user at the PDP-8.
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Basic System
The graphics 8 was ordered as a stand-alone graphics system with
the PDP-8 processor, ASR33 teletype, 338 programmed buffered display, dectapes ,
and interval timer. This section of the report is made-up of short descriptions
of each of these five pieces of the basic system.
PDP-8 INTRODUCTION
The Digital Equipment Corporation Programmed Data Processor-8 (PDP-8)
is designed for use as a small-scale general -purpose computer, an independent
information handling facility in a large computer system, or as the control
element in a complex processing system. The PDP-8 is a one-address, fixed
word length, parallel computer using 12 bit, two's complement arithmetic.
Cycle time of the l6K word random-address magnetic-core memory is 1.5
microseconds. Standard features of the system include indirect addressing
and facilities for instruction skipping and program interruption as functions
of input-output device conditions.
Flexible, high-capacity, input-output capabilities of the computer
allow it to operate a variety of peripheral equipment. In addition to
standard Teletype and per formatted tape equipment, the system is capable of
operating in conjunction with a number of optional devices such as high-
speed perforated tape readers and punches, card equipment, a line printer,
analog-to-digital converters, cathode -ray-tube displays, magnetic drum
systems, and magnetic-tape equipment. Equipment of special design is easily
adapted for connection into the PDP-8 system.
COMPUTER ORGANIZATION
The PDP-8 system is organized into a processor, core memory, and
input/output equipment and facilities. All arithmetic, logic, and system
control operations of the standard PDP-8 are performed by the processor.
Permanent (longer than one instruction time) local information storage and
retrieval operations are performed by the core memory. The memory is
continuously cycling and automatically performing a read and write operation
during each computer cycle. Input and output address and data buffering
ALL OPTIONAL
PERIPHERAL -
EQUIPMENT
SKIP
H>
o-
AC
OATA
OPTIONAL
PERIPHERAL
EQUIPMENT
• USING
PROGRAMMED ^SELECT
TRANSFERS C0DE
(MS)
SWITCH
REGISTER
ADDRESS
TELETYPE
MODEL 33
ASR
TELETYPE
CONTROL
ALL OPTIONAL
PERIPHERAL
EQUIPMENT
OPTIONAL
PERIPHERAL
EQUIPMENT
USING THE
DATA BREAK
FACILITIES
<
ALL OPTIONAL
PERIPHERAL -<
EQUIPMENT
DATA
OUTPUT
BUS
DRIVERS
DATA
DATA
DATA
CLEAR AC
LINK
ACCUMULATOR
AC
CONTROL
DATA
OUTPUT
BUS
DRIVERS
DATA
INCREMENT MB
TRANSFER DIRECTION *
MEMORY
BUFFER
REGISTER
MB
CONTROL
PROGRAM
COUNTER
CONTROL
PROGRAM
COUNTER
INSTRUCTION
REGISTER
3
BREAK REQUEST
O-
BREAK STATE
4096 -WORD
CORE
MEMORY
MAJOR
STATE
GENERATOR
AOORESS
L<
ADDRESS ACCEPTED
,T1 AND T2A CLOCK PULSES
MEMORY
ADDRESS
REGISTER
MA
CONTROL
^IOP 1, 2, AND 4 PULSES
IOP PULSE
GENERATOR
N
^RUN
RUN AND PULSE
CONTROL
^,POWER CLEAR PULSES
POWER CLEAR PULSE
GENERATOR
"Q
PROGRAM INTERRUPT REQ
TIMING SIGNAL
GENERATOR
SPECIAL PULSE
GENERATOR
PROGRAM INTERRUPT
SYNCH0NIZATK3N
K TRANSFER DIRECTION IS INTO POP- 8
WHEN -3 VOLTS, OUT OF POP- 8
WHEN GROUND.
-> =FLOW DIRECTION
-t>=DEC STANDARD POSITIVE PULSE (-3V TO GROUND)
-J> = DEC STANDARD NEGATIVE PULSE (GNDTO -3V)
-O = 0EC STANDARD GROUND LEVEL SIGNAL
-C» = DEC STANDARD -3 VOLT LEVEL SIGNAL
Fig. 2 PDP-8 Block Diagram
for the core memory is performed by registers of the processor, and operation
of the memory is under control of timing signals produced by the processor.
Interface circuits for the processor allow bussed connections to a
variety of peripheral equipment. Each input/output device is responsible
for detecting its own select code and for providing any necessary input
or output gating. Individually programmed data transfers between the
processor and peripheral equipment take place through the processor accumu-
lator. Data transfers can be initiated by peripheral equipment rather than
by the program, by means of the data break facilities. Standard features
of the PDP-8 also allow peripheral equipment to perform certain control
functions such as instruction skipping and a transfer of program control
initiated by a program interrupt.
MAJOR REGISTERS
To store, retrieve, control, and modify information and to perform
the required logical, arithmetic, and data processing operations, the core
memory and the processor employ the logic components shown in Figure 2
and described in the following paragraphs.
Accumulator (AC)
Arithmetic and logic operations are performed in this 12-bit register.
Under program control the AC can be cleared or complemented, its content
can be rotated right or left with the link. The content of the memory
buffer register can be added to the content of the AC and the result left
in the AC. The content of both of these registers may be combined by the
logical operation AND, the result remaining in the AC. The memory buffer
register and the AC also have gates which allow them to be used together as
the shift register and buffer register of a successive approximation
analog-to-digital converter. Tb.3 inclusive OR may be performed between
the AC and the switch register on the operator console and the result left
in the AC.
The accumulator also serves as an input-output register. All programmed
information transfers between core memory and an external device pass through
the accumulator.
Link (L)
This one-bit register is used to extend the arithmetic facilities
of the accumulator. It is used as the carry register for two's complement
arithmetic. Overflow into the L from the AC can be checked by the program
to greatly simplify and speed up single and multiple precision arithmetic
routines. Under program control the link can be cleared and complemented,
and it can be rotated as part of the accumulator.
Program Counter (PC)
The program sequence, that is the order in which instructions are
performed, is determined by the PC. This 12-bit register contains the
address of the core memory location from which the next instruction will
be taken. Information enters the PC from the core memory, via the memory-
buffer register, and from the switch register on the operator console.
Information in the PC is transferred into the memory address register to
determine the core memory address from which each instruction is taken.
Incrementation of the content of the PC establishes the successive core
memory locations of the program and provides skipping of an instruction
based upon a programmed test of information or conditions.
Memory Address Register (MA)
The address in core memory which is currently selected for reading
or writing is contained in this 12-bit register. Data can be set into
it from the memory buffer register, from the program counter, or from
an I/O device using the data break facilities.
Switch Register (SR)
Information can be manually set into the switch register for transfer
into the PC as an address by means of the LOAD ADDRESS key, or into the
AC as data to be stored in core memory by means of the DEPOSIT key.
Core Memory
The core memory provides storage for instructions to be performed
and information to be processed or distributed. This random address magnetic
core memory holds l6K 12-bit words. Memory location 8 is used to store
the content of the PC following a program interrupt, and location I3 is
used to store the first instruction to be executed following a program
interrupt. (When a program interrupt occurs, the content of the PC is
stored in location 8 and program control is transferred to location 1
automatically.) Locations 10g through 17s are used for auto-indexing.
All other locations can be used to store instructions or data.
Core memory contains numerous circuits such as read-write switches ,
address decoders, inhibit drivers, and sense amplifiers. These circuits
perform the electrical conversions necessary to transfer information into
or out of the core array and perform no arithmetic or logic operations
upon the data.
Memory Buffer Register (MB)
All information transfers between the processor registers and the
core memory are temporarily held in the MB. Information can be transferred
into the MB from the accumulator or memory address register. The MB can
be cleared, incremented by one or two, or shifted right. Information can
8
be set into the MB from an external device during a data break or from
core memory, via the sense amplLfiers. Information is read from a memory
location in 0.8 microsecond and rewritten in the same location in another
0.8 microsecond of one 1.6 microsecond memory cycle.
Instruction Register (IR)
This 3-bit register contains the operation code of the instruction
currently being performed by the machine. The three most significant bits
of the current instruction are loaded into the IR from the memory buffer
register during a Fetch cycle. The content of the IR is decoded to produce
the eight basic instructions, and affect the cycles and states entered
at each step in the program.
Major State Generator
One or more major control states are entered to determine and execute
an instruction. The major state generator determines the machine state
during each computer cycle. The major states are Fetch, Defer, Execute,
and Break. Each state is produced as a function of the current instruction
and the current state, except for the Break state which is entered upon
receipt of the Break Request signal supplied by peripheral equipment.
Fetch
During this state an instruction is read into the MB from core memory
at the address specified by the content of the PC. The instruction is
restored in core memory and retained in the MB. The operation code of
the instruction is transferred into the IR to cause enactment, and the
content of the PC is incremented by one.
If a multiple-cycle instruction is fetched, the following major state
will be either Defer or Execute. If a one-cycle instruction is fetched,
the operations specified are performed during the last part of the Fetch
cycle and the next state will be another Fetch.
Defer
When a 1 is present in bit 3 of a memory reference instruction, the
Defer state is entered to obtain the full 12-bit address of the operand
from the address in the current page or page specified by bits h through
11 of the instruction. The process of address deferring is called indirect
addressing because access to the operand is addressed indirectly, or deferred,
to another memory location.
Execute
This state is entered for all memory reference instructions except
jump. During an AND, two's complement add, or increment and skip if zero
instruction the content of the core memory location specified by the address
portion of the instruction is read into the MB and the operation specified
by bits through 2 of the instruction is performed. During a deposit
and clear accumulator instruction the content of the AC is transferred
into the MB and is stored in core memory at the address specified in the
instruction. During a jump to subroutine instruction this state occurs
to write the content of the PC into the core memory address designated
by the instruction and to transfer this address into the PC to change
control.
Break
When this state is established, the sequence of instructions is broken
for a data break. The break occurs at the completion of the current instruction.
The data break allows information to be transferred between core memory
and an external device, via the MB. When this transfer has been completed,
the program sequence is resumed from the point of the break.
Output Bus Drivers
Output signals from the computer processor are power amplified by
output bus driver modules of the standard PDP-8; allowing these signals
to drive a heavy circuit load.
1Q
Functi :>nal Summary
Operation of the computer is accomplished on a limited scale by keys
on the operator console. Operation in this manner is limited to address
and data storage by means of the switch register, core memory data examination,
the normal start/stop/continue control, and the single step or single
instruction operation that allows a program to be monitored visually as
a maintenance operation. Most of these manually initiated operations are
performed by executing an instruction in the same manner as by automatic
programming, except that the gating is performed by special pulses rather
than by the normal clock pulses. In automatic operation, instructions
stored in core memory are loaded into the memory buffer register and executed
during one or more computer cycles. Each instruction determines the major
control states that must be entered for its execution. Each control state
lasts for one 1. 5-microsecond computer cycle and is divided into distinct
time states which can be used to perform sequential logical operations.
Performance of any function of the computer is controlled by gating of a
specific instruction during a specific major control state and a specific
time state.
TIMING AND CONTROL ELEMENTS
Figure 2 shows the timing and control elements described in the
succeeding paragraphs and indicates their relationship to the major
registers. These elements can be grouped categorically into timing
generators, register controls, and program controls.
Timing Generators
Timing pulses used to determine the computer cycle time and used
to initiate sequential time-synchronized gating operations are produced
11
by the timing signal generator. Timing pulses used during operations
resulting from the use of the keys and switches on the operator console
are produced by the special pulse generator. Pulses that reset registers
and control circuits during power turn on and turn off operations are
produced by the power clear pulse generator. Several of these pulses are
available to peripheral devices using programmed or data break information
transfers .
Register Controls
Operation of the AC, MA, MB, and PC is controlled by an associated
logic circuit. These circuits, in turn, transmit and receive control
signals to and from I/O equipment. Programmed data transfer equipment can
supply a pulse to the AC control to clear the AC prior to a data input and
can supply a pulse to cause the content of the PC to be incremented, thus
initiating an instruction skip. Equipment using the data break facility
passes signals with the MA control and MB control to determine the direction
and timing of data transfers in this mode.
Program Controls
Circuits are also included in the PDP-8 that produce the I/O pulses
which initiate operations involved in input/output transfers, determine the
advance of the computer program, and allow peripheral equipment to cause
a program interrupt of the main computer program to transfer program control
to a subroutine which performs some service for the I/O device.
INTERFACE
The input /output portion of the PDP-8 is very flexible and interfaces
readily with special equipment, especially in real time data processing
and control environment.
The PDP-8 utilizes a "bus" I/O system rather than the more conventional
"radial" system. The "bus" system allows a single set of data and control
12
lines to communicate with all I/O devices. The bus simply goes from one
device to the next. No additional connections to the computer are required.
External devices receive two types of information from the computer:
data and control signals. Computer output data is present as static levels
on 12 lines. These levels represent a 12-bit word to be transmitted in
parallel to a device. Data signals are received at all devices but are
sampled only by the appropriate one in response to a control signal. Control
signals are of two types: levels and timing pulses. Six static levels
and their complement are supplied by the MB on 12 lines. These lines
contain a code representing the device from which action is required.
Each device recognizes its own code and performs its function only when
this code is. present. There are three timing pulses which may be programmed
to occur. These IOP pulses are separated in time by one microsecond and
are brought to all devices on 3 lines. These pulses are used by a device
only when it is selected by the appropriate code on the level lines. They
may be used to perform sequential functions in an external register, such
as clear and read, or any other function requiring one, two, or three sequential
pulses .
Peripheral devices transmit information to the computer on four types
of "busses". These are the information bus, the clear AC bus, the skip bus,
and the program interrupt bus. The information bus consists of 12 lines
normally held at -3 volts by load resistors within the computer. Whenever
one of these lines is brought to ground, a binary 1 will be placed in the
corresponding accumulator bit. Each device may use the input bus only
when it is selected; and thus, these input lines are time shared among
all of the connected devices. The skip bus is electrically identical to
the information bus. However, when it is driven to ground the next sequential
instruction will be skipped. It too can be used only by the device currently
13
selected and is effectively time shared. The program interrupt bus may-
he driven to ground at any time by any device whether currently selected
or not. When more than one device is connected to the interrupt bus they
should also be connected to the skip bus so the program can identify the
device requesting program interruption.
The transmission of device slection levels and timing pulses is com-
pletely under program control. A single instruction can select any one of
6k devices and transmit up to three IOP timing pulses. Since the timing
pulses are individually programmable, one might be used to strobe data into
an external device buffer, another to transmit data to the computer, and
the third to test a status flip-flop and drive the skip bus to ground if
it is in the enabling state.
Data transfers may also be made directly with core memory at a high
speed using the data break facility. This is a completely separate I/O
system from the one described previously. It is standard equipment in
every PDP-8 and is ordinarily used with fast I/O devices such as magnetic
drums or tapes. Transfers through the data break facility are interlaced with
the program in progress. They are initiated by a request from the peripheral
device and not by programmed instruction. Thus, the device may exchange a
word with memory whenever it is ready and does not have to wait for the
program to issue an instruction. Computation may proceed on an interlaced
basis with these transfers.
lU
ASR33 (See Figure 3)
Teletype Corporation Model 33TY Standard Duty Automatic
Send-Receive Page Printer Set with Tape Perforator and Reader (Private
Line Version) has the following features:
Eight-level, 11.0 unit code (l.O unit start and 2.0 unit stop pulse)
8-1/2" sprocket feed platen with 11" form out and associated
reader control
Data communications type wheel arrangement with associated four-
row keyboard layout (American Standard Code for Information
Interchange)
115 V AC 60 cycle synchronous motor unit
Gears for 100 wpm operation ( 110.0 Bauds)
Adjusted for 72 character line
Horizontal spacing 10 characters per inch
Vertical spacing 3 or 6 lines per inch
Selector magnet driver can accept .020 or .060 amperes with
proper wiring (strapping)
Generates "even" vertical parity
Two-tone cover: Ivory and Greige
Copyholder
Answer-back drum to be coded by the customer
Function box "online" operation of line feed, carriage return,
bell and WRU
Space suppression at end-of-line
Control key (functions)
Shift key (locks out keys without shift case)
Break key and "Here-is" key
Power supply transformer
Convenience outlet
3-way switch (off, online and local)
Wiring provision for optional full duplex operation
Sheet metal stand with Greige color finish
IS
KEYBOARD
PAPER TAPE
PAPER TAPE PUNCH
PAPER TAPE READER
PRINT PAPER
101 CV DATA SET
TELETYPE STAND
ASR 33 Teletype
Figure 3.
16
Tape Reader Features
3-way operating switch for start, stop and free position
"End-of-Tape" mechanism to shut down reader
Feed sensing electromagnet is pulsed by the distributor
Automatic control contacts for start and "X-ON" code, stop
on "X-OFF" code and low paper alarm
Power pack assembly with automatic control relay
Parallel wire output to distributor
Operating sequence; reads tape and feeds
Capable of reading fully perforated tape
Tape Punch Features
Four operating buttons , "UNLOCK", LOCK "ON", "BACKSPACE", and
"RELEASE". (When the lock "ON" button is depressed, the tape
punch is locked into the "on" mode and cannot be turned off.
When the "UNLOCK" button is depressed, the tape punch will not
turn off but will be able to accept an "off" signal and turn
off automatically.)
l" Core of tape supply
Fully perforated 8-level code holes and feed holes
"V" shaped tape tearoff
Operating sequence; feed and punch
Removable chad box (designed for attaching to stand)
Automatic control contacts for start on "Tape Aux. On" code,
stop of "Tape Aux. Off" code and low paper alarm
General Information
Interoperates with existing teletypewriters having corresponding
features
Fewer options possible compared to Model 35 Heavy-Duty Equipment
IT
Actual and schematic wiring diagrams packaged with set
Set shipped completely assembled less stand and chad box
The above equipment requires a channel capable of handling 110.0 Bauds
(bits per second) for operation at 100 wpm.
One copy each of Bulletins 2T3B and 118UB furnished with each
Dimensions
Complete set less stand:
Width 22"
Depth 18-1/2"
Height 8-3/8"
Weight kk pounds
Stand: Supports Teletypewriter
Width 17-3/V
Depth (at Top) 8"
Depth (at Bottom) 6-1/2"
Height 22-1/2"
Weight 12 pounds
Estimated Service Life
U500 Hours at 100 wpm
Lubrication Intervals
(Printer, Tape Punch and Reader)
100 wpm 500 hours or 6 months, whichever is first
Preventive Maintenance and Overhaul
100 wpm 1500 and 3000 hours
NOTE: Hours indicates actual operating time.
18
DECT APE
The Dectapes are connected to the PDP-8 by way of the Data Break
Multiplexor feature through a Dectape Control (TCOl). The TC01 will be
described first.
Control, Dectape TCOl
The TCOl Dectape Control operates up to eight TU55 Dectape Transports.
Binary information is transferred between the tape and the computer in
12-bit computer words approximately every 133-1/3 microseconds. In writing,
the control disassembles 12-bit computer words so that they are written
at four successive lines on tape. Transfers between the computer and the
control always occur in parallel for a 12-bit word. Data transfers use
the PDP-8 Block Transfer Control (BTC) (high speed channel) facility
of the computer. As the start and end of each block are detected by the
Mark track detection circuits, the control raises a Dectape (DTCF) flag
which causes a computer program interrupt. The program interrupt is used
by the computer program to determine the block number. When it determines
that the forthcoming block is the one selected for a data transfer, it
selects the read or write control mode. Each time a word is assembled or
Dectape is ready to receive a word from the computer, the control raises
a data flag. This flag is connected to the computer facility to signify
a break request. Therefore, when each 12-bit computer word is assembled,
the data flag causes a transfer via the BTC. By using the Mark channel
decoding circuits and the BTC in this manner, computation in the main
computer program can continue during tape operations.
Dectape TU55
Dectape is a convenient, low cost in-out data storage facility and
updating device.
FIXED POSITION ADDRESSING permits selective updating of tape inform-
ation as in magnetic disk or drum storage devices. Units as small as a
19
single computer word may be stored or recorded on tape without disturbing
adjacent information. Data blocks are numbered and completely addressable.
AUTOMATIC WORD TRANSFERS use the PDP/8 Block Transfer Control
to allow concurrent information processing and data acquisition during
block transfers at 15 kc character rate.
SIMPLE TRANSPORT MECHANISM improves reliability. Dectape's simple
drive system requires no capstans, no pressure pad, and no mechanical
buffering; therefore tape and head wear is minimal.
POCKET-SIZE REELS are handy to carry, easy to load. Each 3-1/2
inch reel holds up to 3 million bits, the equivalent of U,000 feet of paper
tape, assuming 6-bit words are used.
BI-DIRECTIONAL OPERATION saves time, provides easy access to stored
information; reading, writing, and searching may be conducted in either
direction.
REDUNDANT, PHASE RECORDING insures transfer reliability, reduces
problem of skew in bi-directional operation. Use of phase (rather than
amplitude) recording greatly reduces drop-outs due to variations in amplitude,
PRE-RECORDED TIMING AND MARK TRACKS simplify programming. Relieve
the programmer of the responsibility of furnishing timing or counting
instructions and permit block and word addressability.
PRE-TESTED SUBROUTINES are available for information storage and
retrieval, maintenance, and diagnostic tests.
Dectape Transport Type TU55
The TU55 is a bi-directional magnetic-tape transport consisting of a
read/write head for recording and playback of information on five channels
of the tape. Connections from the read/write head are made directly to
the TC01 external control which contains the read and write amplifiers.
20
The logic circuits of the TU55 control tape movement in either
direction over the read/write heads. Tape drive motor control is exer-
cised completely through the use of solid state switching circuits to
provide reliable operation. These switching circuits contain silicon
controlled rectifiers (SCR) which are controlled by normal DEC diode and
transistor logic circuits. The function of these circuits is simply to
control the torque of the two motors which transport the tape across the
head according to the established function of the device, i.e., go, forward,
reverse, or stop. In normal tape movement, full torque is applied to the
forward or leading motor and a reduced torque is applied to the reverse
or trailing motor to keep proper tension on the tape. Since tape motion
is bidirectional, each motor serves as either the leading or trailing
drive for the tape, depending upon the forward or reverse control status
of the TU55. A positive stop is achieved by an electromagnetic brake
mounted on each motor shaft. When a stop command is given, the trailing
motor brake latches to stop tape motion. Enough torque is then applied
to the leading motor to take up slack in the tape.
Tape movement can be controlled by commands originating in the computer
and applied to the TU55 through the TC01 Dectape control, or can be controlled
by commands generated by manual operation of rocker type switches located
on the front panel of the transport. Manual control is used to mount new
reels of tape on the TU55, or as a quick maintenance check for proper
operation of the control logic in moving the tape.
21
PROGRAMMED BUFFERED DISPLAY 338
The Type 338 Programmed Buffered Display is an incremental
display system, consisting of a small scale, high speed computer and a
display subsystem for control of the CRT. The computer used is the
Digital Equipment PDP-8.
FUNCTIONAL DESCRIPTION
The 338 display logic can he thought of as a special purpose
computer which stores its instructions (display commands) in the memory
of the PDP8, and interacts with the computer through a series of
instruction interrupts and data transfers. The display is an output
device with respect to the computer for the following reasons:
a. The PDP8 has a series of instructions which start, stop, and
load and interrogate the registers of the display.
b. The PDP8 can modify the data commands which are interpreted
by the display because the commands are stored in the
PDP8 memory.
The commands are transferred to the display control via the
PDP8 single cycle data break system. The display file words are loaded into
a table or block of successive memory locations; and the beginning location
of this table is loaded into a special register called the display address
counter (DAC). The output of the DAC and the break field registers are
applied to the inputs of the memory (MA) register forming a 15-bit address
which can increment across memory field boundaries. The data break is then
22
initiated by either the display or the computer, and this address is read
into the MA. The computer then goes through a break cycle in which it
fetches the word from memory and places it into its memory buffer (MB)
register from where it is transferred to the buffer register (DX) in the
display. During this time, the display starts its operation and the DAC
is incrememted by one. The computer program counter (PC) is not incremented
during the break cycle. At the end of the break cycle the PDP8 continues
its main program until the display requires another data break.
Display Parameters (Coordinate System)
The display screen which is 9-3/8 inches square, has 10 bits
of resolution; in other words there are l,02ij- points in the x and y
directions or about a million points in all. The x and y position
registers are 13 bits long, however, and therefore the screen represents
only l/6k the total addressable area (paper). The paper is broken up
into 6k sectors corresponding to the upper 3 bits of x and y, with
sector defined as the lower left sector. Only information in sector
is intensified so that translation is accomplished by moving the paper in
relation to sector 0. The lower left corner is point (0,0), and the co-
ordinates increase to the right and up, and decrease to the left and down.
An edge violation occurs when a line is drawn across the boundary of the
paper. This is a warning that an overflow condition has just occurred in
the x or y position register. A vertical edge flag indicates the y
position register went from all Is to all 0s, or from all 0s to all Is.
The horizontal edge flag indicates overflow in the x register. The over-
flow can be set to occur after the 10th, 11th, 12th or 13th bit in x and y.
The virtual size can therefore be changed under program control.
23
Scale
The scale setting determines the number of positions each
succeeding spot is moved before it is intensified. It affects both the
size and appearance of lines or symbols drawn in the vector, vector
continue, short vector, increment, or character modes. At scale setting
11 , each point can be clearly distinguished. At scale setting 00 ,
lines and symbols appear to be continuous. The point spacing is
illustrated in the following table.
Scale
Point Spacing
Intensify
°°2
Every
0, 2
•
O
•
O • O * •
O
• O
2nd
,0 2
•
O
O
O • O O
O
O O
4th •
"2
•
O
OOOO
O
• O
8th
Intensity
There are eight intensity levels available on the display,
ranging from 000 , which is barely visible, to 111^, which is very bright.
Note that scale and intensity settings are interrelated. For example,
if characters are drawn (with the character generator) at the lowest scale
setting, and too high an intensity is used, they will be badly blurred. On
the other hand, if many characters are to be displayed simultaneously or if
the light pen is to be used, it is best to use as high an intensity level
as possible.
2k
State
The display logic is broken into two states,, data state and
control state. Control state commands are interpreted as instructions
to the display logic to change parameters, jump, skip, etc. The data
state commands are instructions to move the beam via the x and y position
registers. When the display is initialized, the commands are accepted in
control state until an "enter data state" command is given. The display
returns to control state from data state by escaping.
In control state , the first three bits (op code) designate the
operation to be performed by the remaining nine bits. Seven of the eight
op codes are used:
Parameter
1 Mode
2 Jump
3 Pop
k Conditional skip 1
5 Conditional skip 2
6 Miscellaneous (microprogrammed)
Arithmetic compare 1
1 Arithmetic compare 2
2 Skip on flags
3 Count
k-"J Set slaves (optional)
7 Sync
Data state words are accepted in one of seven formats according to
the contents of the mode register. The data state modes available are:
25
Increment Mode - This mode is used to draw alpha numeric characters or other
small symbols, and to draw curves. A half-word instruction that will cause
the beam position to be stepped one, two, or three times in one of eight
directions. Direction is to the right, direction 1 is up and to the
right, etc.
Vector Mode - This mode is used to draw straight line segments. A two-
word instruction which causes the beam position to be stepped along a line
represented by a 10-bit delta y and a 10-bit delta x, each having a sign bit,
Vector Continue Mode - This mode is used to draw a straight line to the
edge of the screen. Similar to Vector mode but causes the vector to be
extended until an "edge" is encountered.
Short Vector Mode - This mode is used to draw figures composed of short
line segments. A one-word instruction having a ^-bit delta y and a U-bit
delta x, plus sign bits. It is transformed within the display to the same
format as Vector mode, and operates in the same manner.
The preceding modes are "incrementing;" that is, they move the
beam by counting the x and y position registers. The counting is done
at 1.2 microseconds per step on an intensified move; at 0.30 microseconds
per step on a nonintensified move.
Point Mode - This mode is used for random point plotting. A two-word
instruction which causes new y and/or x coordinates to be set into the
y and x position registers.
26
Graph-Plot Mode - This mode is used to draw curves of mathematical
functions. A one-word instruction which causes the y or x position
register to be changed; at the same time, the other register is incremented
by a count of one, two, four, or eight, depending on the current scale
factor. This mode is useful for plotting curves resulting from a series
of solutions of an equation.
Point and Graph-Plot modes operate at one of two rates, depending
upon the position of the new point with respect to the previous point. The
high-order three bits of the ten y and ten x position bits are compared to
the corresponding bits in the new data words. If they are the same, the
delay for beam-settling time is 6 microseconds; if they differ, a 35 micro-
second delay is used.
Character Mode - A half-word instruction, using the Type VC38 Character Generator.
All modes are entered from control state by the "enter data state"
command. Each mode, however, has its own way of escaping back to control
state. The mode register is cleared by power clear and initialization of
display (IOT 165).
Subroutining
The display has control state commands which will modify the DAC.
This enables unconditional display jumps (jump), jump to subroutine (push
jump) and the return from subroutines (pop). The new address is specified
by 15 bits allowing direct addressing of 32 K of core. The jump and push
27
jump commands are specified by two consecutive 12 -"bit words. Push, jump
stores the return address, mode, intensity, scale, and light pen on a
push-down pointer list which resides in the first h K of PDP8 core. This
information is automatically written into two locations in the format
shown below.
B
reak Fie
d
Light
Pen
Scale
Mode
Intensity
1
2
3
4
5
6
7
8
9
10
11
First Word
Low Order 12-Bits of Memory Address
8
10
11
Second Word
The information is placed in the address indicated by the
push-down pointer, (PDP) which is a 12-bit register in the display logic.
When a push jump is executed, the PDP is incremented twice, adding a new
entry to the PDP list. This allows multi-level and recursive subroutines
in the display.
The pop command takes the last entry on the PDP list from core
and gates it back to the proper registers. The display status, however, can
be inhibited from being restored. The PDP is automatically decremented by
two, making the PDP list a last in first out stack.
28
Light Pen
The light pen is an input device which generates a signal Cflag)
that can be sensed and interpreted by the computer. A light pen
interruption stops the display, leaving the contents of all display
registers intact, and signals the computer that an interruption has
occurred. When this happens, the programmer can examine the contents of
the display registers to determine the location (on the display) of the
point of light that was sensed by the light pen and/or determine the
memory location of the data word specifying that point. The light pen
detects light in the range 1*300 to 56OO angstroms.
Pushbuttons
The 338 is equipped with a bank of twelve pushbuttons. They are
placed six in a row with a clear button to reset that group. The buttons
in each group are interlocked, but two buttons in different groups can be
pressed simultaneously. Pressing a button complements an associated
flip-flop. For reference, the pushbutton is lit when its flip-flop is in
the 1 state. The state of the pushbuttons can be sensed both by the
display, using the control state skip instructions, and the PDP8, which
can read the state of the pushbuttons into the accumulator. The PDP8 and
display can also clear and set the pushbuttons. This enables three-way
communication between the operator, display logic, and PDP8. The buttons
are labeled through 11 and are packaged in a compact, portable box. The
box is connected to the display by a 20 foot cable. There is also a
special computer interrupt button on the box.
29
Flags
There are a number of special conditions that can arise in the
display which require the attention of the PDP8 processor. These
conditions are indicated by display flags which can interrupt the computer
and he sensed by IOT skip instructions. The flags are:
a. Internal stop
b. External stop
c. Edge
d. Light pen find
e . Push button hit
f. Manual interrupt
The flags can be separated into two groups; a-d are flags which
stop the display; e-f are flags which do not stop the display. Group 1
flags are cleared in one of three ways: initialization of a display
sequence; resuming from the point the display stopped; and a pulse to clear
the flag if the display is no longer needed.
30
Interval Timer
The basic system was installed with an interval timer. It was changed
to synchronize with the line voltage. The orders associated with the timer
are:
6311 Skip on no timer flag,
6312 Clear timer flag, enable timer interrupt,
631^ Disable timer interrupt.
(H. Levin)
31
Operating Additions
Very soon after the Graphics 8 was put into operation it became
obvious that it could not stand alone and was in need of a number of
hardware improvements. The list began with a slow link to a large 360
installation and carried through a Data Disc for more local storage,
a Data Tablet for input, an Audio Output for sound production, a push
button bootstrap for convenience, an Illiac III connection for testing
applications, a 2701 P.D.A. for more rapid access to 360 and a microswitch
keyboard for replacement of the teletype keyboard.
32
PDP8 TO 630 INTERFACE
General Description
The PDP8 to 630 interface is a half duplex, 100 CPS, serial
input to the 630 Data Communications unit. The 630 has no knowledge of
the port being anything other than a high speed serial device.
The interface consists primarily of:
1. An entry to the PDP8 accumulator,
2. An entry from the PDP8 accumulator,
3. Six IOT instructions to control transfers,
h. An entry to the PDP8 skip bus, interrupt bus,
and clear ACC bus,
5. A DEC 4706 receiver card, and U707 transmitter card,
6. Miscellaneous control logic.
Instruction Set
IOT 6631 - SKIP ON RECEIVER FLAG
6632 - CLR ACC AND REC FLAG
663U - GATE REC TO ACC
66kl - CLR INT. ENABLE
66^2 - SET INT. ENABLE
66 UU - CLR TRANSMITTER FLAG AND INPUT DATA FROM ACC
Due to the half duplex mode of operation an echo is generated
in the receiver when data is transmitted. This allows testing of
transmitter completion with an IOT 6631.
Transmitter
Transmitting data to the 630 consists of gating the ACC
contents into the transmitter with an IOT 66hk. The interrupt enable
33
flag must have been set with an IOT 66^2 in order to test for transmitter
completion. The IOT 66kh also enables the shift clock and starts
transmitting data. The receiver is active during transmission and
receives the transmitted data as it is going to the 6 30. When the
receiver flag comes on, it has received the complete character. A test
of the receiver flag with an IOT 66 31 will generate a program skip when
the flag is present. A new character may then be transferred from the
accumulator to the transmitter.
Receiving
Receiving data from the 630 consists of clearing the receiver
flag and enabling the interrupt. An incoming character will set the
receiver flag and generate an interrupt (if allowed). A test of the
receiver flag with an IOT 6631 will generate a program skip, indicating
a character is present. An IOT 663^ will gate the contents of the
receiver into the accumulator.
(R. Miller)
3k
Data Disk
The following information describes our disk storage system
with the exception that:
The 6k heads of electronics will be divided into 32 groups
of 2 heads each.
Summary of Specifications
Disk Speed
Data Rate
Data Capacity
Input /Output
Levels
Envi ronment al
1800 RPM +1.32 - 3%
Hysteresis Synchronous Motor
3.0 Mbps per track
100,000 bits per track (tracks can
be added in increments of 8, up to 6k,
and +5V TTL integrated circuit interface
Operating temp: 50°F. - 105°F. ; less
than 20°F. change per hour.
Non-operating: -20°F. - +130°F.
Operating humidity: 105? - 80$ RH
without condensation.
Non-operating humidity: to 90% RH
without condensation.
Corrosive atmospheres such as those
found in steel and chemical plants are
not permitted.
AC Power
DC Power
Requirements
(Per track)
Floor vibration of 0.15 g's max.
from 10 to 65 Hz.
The disk package shall not be damaged
by 5 g's or less of shock in any axis.
120V + 10$ , 60 Hz +0.5 -1.5 Hz single
phase 8.2A starting (10 sec);
2.6A running
+18V at 125 ma (while writing)
+6V at 90 ma)
-6v at kO ma) +5% regulation
(Power supplied by internal power supply. )
Weight 86 pounds
35
General Description
Electrical
The F-series Parallel Digital Disk Memory System has a 12-inch
disk "which can contain as many as 6k data tracks with 100,000 bits on each
track. The disk rotates at 1800 RPM and the bit rate is 3 million bits
per second.
The FPD unit is designed for display buffer storage applications.
The disk unit uses synchronous clocking from a clock track and is recommended
for temporary storage only. Where data is to be stored for an indefinite
period, the Data Disk F6 Memory should be employed.
Each track is complete with a read/write head and all electronics
to perform the following functions (Figures k, 5);
Encode data
Write data
Read data
Decode data
Re-clock data
Any number of tracks may be written or read in parallel, since each has
a clocked flip-flop output.
System Application
The FPD unit is designed so that each track on the disk may
feed a separate TV monitor display. A high-speed processor can access
each track and update the presentation stored upon any track. Where
display rates higher than 3 million bits per second are needed, more than
one track can be combined to form the display buffer. For example, data
read from four channels may be loaded into a four-bit shift register and
with a kX clock the data can be shifted into the display channel at a 12
million bit rate (Figure 6). Any number of tracks, up to 6U, may be
combined.
TEXAS INSTR.
JKFF
SN7473N
3N7473N
SN7400N
J
K
WRITE
AMPLIFIER
READ
AMPLIFIER
J
CLOCK
K Q
A,
DATA WRITE
r\
A
F DATA READ
WR
cue
RE
CLC
TE
>CK
AD
)CK
WRITE ENAB
LE
J
-
Figure k
DATA WRITE #1
WRITE ENABLE #1
DATA READ#1
DATA WRITE #64
WRITE ENABLE #64
DATA READ #64
WRITE SHIFT
READ SHIFT
TRACK ORIGIN
WRITE/READ
AMP#1
WRITE/READ
AMP #64
CLOCK
LOGIC
UP TO 64 TRACKS
HEAD #1
HEAD #64
BIT
CLOCK
READ
CLOCK
HEAD
m-
o
CO
Figure 5
37
READ
DATA WRITE #1 — •>
TRACK #1
GATE
SHIFT
REGISTER
DATA WRITE #2 — *
TRACK #2
DATA WRITE #3 — •"
TRACK #3
DATA WRITE #4 — •*
TRACK #4
t
LOAD
t
SHIFT
4X CLOCK
Figure 6
FPD UNIT
INPUT DEVICE
WRITE LINE
READ LINE
SN7473N
TWISTED PAIR (10' MAX. ; 15 PF/FT.)
SN7400N
WRITE ENABLE
2 LOADS
TWISTED PAIR (10' MAX. ; 15 PF/FT.)
Figure 7
38
Input/Output Details
Input /Output Lines
Each track has three input/output lines that are sent over two tw:.sted
pairs of cables, as shown in Figure 7. The FPD unit uses Texas Instrument
Series SN7UOON and SN7U73N TTL integrated circuits.
Input Connectors
Eight 3^-pin connectors are provided, each serving eight heads. The
use of 16 heads would require two connectors, etc. All eight connectors (31
through S8) would be required if 6U heads were used. (See Table 2.) Table 2
also indicates the function served by each pin on each connector, as well as
the tracks served by each.
Table 1
Data Input/Output Lines
Data Write 1 thru 6U:
Write Enable 1 thru 6U:
Data Read 1 thru 6U:
An input line that is driven from output
of a flip-flop that is clocked by Data
Write Shift Clock.
The Write Enable line going high will
cause the data on the corresponding Data
Write line to be written on the track.
As long as the Write Enable line is high,
writing will continue.
Each Data Read line is the buffered out-
put of a clocked flip-flop. The Data
Read is delayed 2 bits times from Data
Write and may be shifted into an external
register by using the negative edge of
Data Read Shift Clocks. During Write the
output of the Data Read line is held low.
39
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Five clocks, all derived from one track, are available in the standard
i FPD system. Two are used internally, and the other three are for use at the
interface. The three interface clocks are the Track Origin (once per revolu-
tion), Write Shift and Read Shift (Figure 8 and Table 3).
The Write Shift Clocks are used to change the state of the Data Write
line and are counted down to indicate angular position of the disc. The Track
Origin clock is derived from the six-bit gap in the clock track and is used to
indicate the zero degree position of the disc and as a reset for any counters
used to identify other angular positions.
Clock Connector S9
S9 is a 3^-pin used by the clock track only. (See Table h for pin
assignments . )
Table 3
Clock Output Lines
Data Write Shift Clock:
A 3-million bit per second clock
with 6 clocks missing at Track
Origin time.
The negative edge is used for
changing state of Data Write lines
Data Read Shift Clocks:
Inverted Data Write Shift Clocks.
The negative edge is used for
sampling the Data Read lines.
The Data Read is delayed 2 bit
times from Data Write.
Data Origin Clock:
A once-per-revolution clock used
to reset counters, etc.
Ul
TRACK
ORIGIN
WRITE SHIFT
CLOCK
WRITE
ENABLE
DATA
WRITE
DATA READ
READ SHIFT
CLOCKS
V
Figure 8
Table k
Pin Assignment
S^-Pin Clock Connector S9*
Pin
No.
Function
A
B
Write shift clocks ) Twisted
Ground ) pair
C
D
Read shift clock ) Twisted
Ground ) pair
E
F
Track origin clock ) Twisted
Ground ) pair
H
J
Clock data write line ) Twisted
Clock write enable line) pair
*Data Disc No. 2535
Winchester MRAC 3^P
k2
Operation
Write
To write, the first bit of data is placed on the Data Write line
and at the correct angular position the Write Enable line is raised and writ-
ing begins. Each negative-going transition of the Write Shift clock is used
by the external device to transfer another data bit onto the Data Write line.
The turn on of the Write Enable should occur at no later than 100 nanoseconds
of the negative edge of a Write Shift clock. Write Enable should be turned
off at the next positive-going clock transition following the last shift
clock. (See timing diagram, Figure 8.)
Read
During Write the Data Read line is held low but at all other times,
any data on the track will be clocked out to the Data Read line. The data
may be transferred from the Data Read line to an external device at the nega-
tive edge of the Read Shift Clock.
U3
kh
.
SYLVAMA DATA TABLET
GENERAL INFORMATION
Introduction
The SYLVANIA DATA TABLET MODEL DT-1 is a coordinate encoder
designed to permit graphical communication between man and computer. This
solid state system enables the user to enter hand-printed alphanumeric
data, curve tracing and modification data, or any other form of hand-
generated graphic data into a computer system. The DT-1 is completely
contained within three units — a metal rimmed transparent glass writing
panel, an electronic pen, and a 1.5 cubic foot electronics package.
Description
The Sylvania Data Tablet is inherently an analog device in which
coordinate information is obtained by phase measurements. Several
advantages are forthcoming from this: First, the continuous nature of
analog signals allows infinite resolution limited only by system noise.
Second, since amplitude stability is not necessary, a capacitance pick up
(pen) can be used and dielectric layers may be interposed between it and
the active surface. The writing panel of the Sylvania Data Tablet consists
of a transparent, continuous conductive film bonded to a heavy glass base
plate. A thin glass sheet is laminated to the exposed surface of the film
to prevent wear and contamination. A drive network coupled to the
electronics package excites the film at discrete points along its circum-
ference in such a manner that a traveling wave (in a mathematical sense) is
established parallel to each orthogonal axis. This wave has the property
that its phase is a linear function of position as in the relationship:
V = K sin (wt - ax)
The actual tablet signals are more complicated due to the requirement for
axis separation. The latter is accomplished by introducting individual
frequency translations to the drive signals.
h<5
1 KHz
OSCILLATOR
90 KHz
'X' AXIS
MODULATOR
110 KHz
•V AXIS
MODULATOR
'X' DRIVE
AMPLIFIERS
'Y' DRIVE
AMPLIFIERS
IP l| I, H
STYLUS
'X' AXIS
DEMODULATOR
•Y' AXIS
DEMODULATOR
'X' PHASE
DETECTOR
12 BIT
DIGITAL
BUFFER
:}
12
LINES
2 ANALOG
OUTPUTS
'Y' PHASE
DETECTOR
12 BIT
DIGITAL
BUFFER
12
LINES
'Z' AXIS
AMP. DET.
3
LINES
TABLET
Figure 9 Sylvania Model DT-I Block Diagram
Figure 9 is a "block diagram of the Sylvania Data Tablet. A stable
1 KHz sinusoid oscillator generates the primary signal (which will later
contain the desired phase shift) used in the system. Balanced modulators
operating with 90 KHz and 110 KHz carrier frequencies multiplex the primary
signal to different portions of the frequency spectrum as double-sideband
suppressed-carrier signals. These are buffered by the 'X' and ' Y' drive
amplifiers which in turn drive the conductive film network through a
shielded drive cable. An electronic pen (with a high input impedance
amplifier built in), capacitively senses the field in the region beneath
the pen tip through the glass laminate and any overlayed paper. The voltage
is transferred to the electronic package via the attached coaxial cable.
ke
Circuitry within the electronics package separates the pen
signals into 'X' and 'Y' channels and extracts the phase information.
The desired phase is observed in the envelope waveform of the signals while
the axis information is contained in the carrier frequencies. 'X' and 'Y'
axis demodulators, which are in fact synchronous detectors keyed by the
carrier oscillators, extract the 1 KHz envelopes from the complex pen
signals. Phase detectors then compare the demodulator outputs against
the 1 KHz primary signal and produce analog and digital voltages prop-
ortional to the phase shifts .
An additional circuit measures the amplitude of the pen signals
and provides a coarse measure of height ('Z' axis).
Specifications
ELECTRICAL
Accuracy
Resolution
SYLVANIA DATA TABLET MODEL DT-1
Bandwidth
Data rate
Digital outputs :
'X' and 'Y 1 axis
'Z' axis
Data Ready Line
'One' state
'Zero' state
Maximum load
+_ 1% of full scale in each coordinate axis
+ .025$ of full scale or 12 binary bits at
5 Hz bandwidth
20 Hz supplied
200 coordinate points per second
Two 12 bit buffer register outputs
available — updated every 5 milliseconds
One bit for each threshold. Output levels
are designated 000 , 001 , 011 , 111 —
updated independent of system timing.
Set to 'zero' five microsec. before X-Y
buffers change and reset to 'one' state
five microsec. after change
+k volts
+.5 volts
600 pf . at 10 milliamps for either state
hi
Analog Outputs :
■X' and 'Y' axis
Z' axis
External connectors
and controls:
Front panel
Rear panel
Power source
Operating temp, range
MECHANICAL
Writing panel dimen-
sions
Writing aperture
Two buffered output lines with a dc
voltage proportional to position.
Range is from -2 volts to +2 volts
with zero at the center. Output
impedence is 500 ohms.
Same as digital except inverted. Output
impedance is 850 ohms in high state and
20 ohms in the low state.
Power on-off switch with built-in pilot light,
Miniature coaxial connector for the
electronic pen
ik pin auxiliary writing panel connector
3^ pin digital output connector containing
the 'one' side of the 'X-Y' buffer
registers. Three 'Z' axis bits and the
Data Ready Line are also available.
9 pin analog output connector containing
'X' and 'Y' dc outputs and three 'Z'
axis bits.
ik pin writing panel drive connector
Three-prong power connector
Power line fuse — 3 amps
Three power supply fuses — 3 amps
105 to 125 volts 60 Hz, 150 watts
+10°C. to +40°C.
15" x 16" x 3/U"
11" x 11"
kQ
Electronic package
dimensions IT" x 18 1/2" x 7"
Writing panel weight Approximately 15 pounds
Electronic package
weight Approximately 35 pounds
Pen replacement
cartridge "Papermate" standard refill
Operation
The Sylvania Data Tablet Model DT-1 may be used as a table-top
unit or a transparent overlay for a computer- controlled cathode ray tube
display. For the latter use, the bottom plate must be removed by taking
out the eight mounting bolts on the bottom. The writing panel may then
be mounted over the face of the CRT and the electronic pen used in a
"light pen" fashion. Rear projection techniques may also be employed by
placing a translucent diffusing overlay on the writing panel.
The electronic package may be converted from table top to relay
rack operation by attaching the included adaptor brackets. The writing
panel may be mounted up to ten feet (with appropriate cable) from the
electronic package using either the front or rear 1^- pin panel connectors.
The electronic pen can only be connected at the front panel of the
electronic package. Analog outputs are available on a 9-pin jack and
digital outputs on a 3^ pin jack both mounted on the rear panel. A three
prong connector and power cord are supplied for connecting 115 volts, 60 Hz
to the Model DT-1.
The digital output is a binary parallel format for the 'X' and 'Y'
axis. Two 12 -bit words are simultaneously stored in buffer registers which
are updated 200 times per second by internal timing signals. A Data Ready
Line, available at the digital connector, drops to the "zero" state five
microseconds before the buffer registers are updated and returns to the
"one" state five microseconds following the transfer. Only 100 nanoseconds
are required to load the buffer registers which remain quiescent during the
U9
remainder of the five millisecond period. The center of the tablet
corresponds to binary 100 000 000 000 . The left and bottom edges are
represented by 000 000 000 000 ; the top and righthand edges by 111 111 111 111 .
A ' Z' axis (pen height above the -writing panel) three-bit word
is also available at the digital connector. Each bit corresponds to an
adjustable threshold level and is independent of digital timing. As the
stylus approaches the writing panel surface from a remote position, the
'Z' representation changes in the following manner: 000 (over 1 inch away),
001, 011, (touching the tablet), and finally 111. The maximum value is
reached only when a slight downward pressure is applied to the pen forcing
the closure of built-in switch contacts.
The analog outputs are internally buffered and are protected
against short circuit. Zero volts corresponds to the center position
while the left and bottom edges produce minus two volts dc ; the right and
top edges produce plus two volts dc. Both analog outputs and three ' Z 1
axis bits are available on the 9-pin analog connector.
50
PDP/8 MUSIC GENERATOR
Introduction
The PDP/8 music generator is a low cost device that is
capable of producing audio tones over a speaker. Its main purpose is
to allow a program to audibly signal a user about various conditions,
e.g., an illegal command has been entered, an error has occurred, etc.
Hardware
The music generator consists of:
1. An IOT decoder board;
2. Two flip-flops resistively coupled to:
3. An audio amplifier;
k. A loudspeaker.
Instructions '
The following instructions are used in programming the
music generator:
6 701 - clear both flip-flops
6702 - complement flip-flop 1
6"J0h - complement flip-flop 2
51
PDP/8 BOOTSTRAP LOADER-
HISTORY AND GENERAL DESCRIPTION
The PDP/8 bootstrap loader was designed to do away with two
very messy and time consuming features of the PDP/8.
The PDP/8 rim loader formerly had to be toggled in by hand,
using the accumulator switches. This consisted of toggling in l6
instructions and depositing them in core memory. This loader is
necessary to read paper tape.
The PDP/8 tape loader (20 instructions) was formerly read in
via the teletype 10 CPS reader. The rim loader must have been present
in order to activate the reader. The tape loader is necessary in order
to use the Dectapes.
The bootstrap loader allows one to select either the rim or
the tape loader option via a switch. The starting address of the
selected bootstrap -1 must be set into the ace. switches and loaded
with the load address key. The ace. switches are then cleared to all
°' s and the loader pushbutton depressed. The selected loader is
automatically loaded into the PDP/8 memory. The teletype reader or
the Dectapes are then ready to use.
The accumulator entry is made to the unused side of the
accumulator switches. The set line is the deposit switch.
Logic Description
The loader uses a gated clock for timing and a flip-flop
register for decoding. The decoder register length is selected by the
52
bootstrap selector switch. The selector switch also gates the outputs
of two diode matrix boards to the accumulator. Either one or the other
of the two matrix boards is connected to the accumulator entry.
When the pushbutton is depressed, the clock is enabled and
counts the decoder register to output the first word into the accumulator,
The clock output is also used to set the deposit switch entry on the
PDP/8. At clock frequency, the decoder outputs consecutively gate words
from the selected matrix to the accumulator entry and the deposit line
is switched. At the proper count for the selected matrix, the clock
is disabled and further action is inhibited until the pushbutton is
released and depressed again.
Setting the starting address to -1, when loading the loader,
is necessary to insure the output of the matrix in a static condition
is all o' s. This will not interfere with the normal use of the
accumulator switches.
53
ILLIAC III INTERFACE
The interface from the PDP/8 to Illiac III is an accumulator
interface. It has the capability of transferring information to and from
the PDP/8 accumulator. The interface has an entry to the PDP/8 program
skip bus and several IOT instructions to control the transfer. There
are two control flops to control the status of the interface at the
PDP/8 END, device ready, and data ready.
IOT List
6731 - SKIP ON DEVICE READY
6732 - CLEAR DEVICE READY
673H - CLEAR DATA RDY
67^1 - SKIP ON DATA RDY
67^2 - GATE ACCUMULATOR, SENT TO ILLIAC 3 AS DATA ACCEPTED
6Thh - SENT TO ILLIAC 3 AS CONTROL
675^
6752 > SENT TO ILLIAC 3 AS CONTROL
6 75^ J
5h
2701 PARALLEL DATA ADAPTER*
In order to improve the communications capability to the
360 computers in the Department, a better hardware link was required.
The IBM 2701 parallel data adapter was chosen for interface purposes
for at least the following reasons.
1. The 2701 allows the PDP/8 to be reasonably well isolated
from the 360 channels. Thus, less chance of a system interference.
2. The parallel data adapter is a much simpler control that
operates in a parallel-by-word (l6 bits )-f ashion over a demand- response
interface .
3. This type of interface had been done before for a PDP/7
so there was some familiarity with its design.
The general operating characteristics of the PDP/8-2701 PDA
interface is such as to allow either computer ( 360 or PDP/8) to initiate
a block transfer. The 16 bit word that is transferred to the 360 is
broken into two bytes of 8 bits each for 360 channel transfers. The 16
bit word as it arrives at the PDP/8 is broken into two 6 bit characters.
The other four bits are not used.
The hardware requirement for this interface was to construct
a controller that would exchange information with the EDP/8 data break
facility on one side and the 2701 PDA on the other. The data break
requirements are reasonably simple to satisfy. The 2701 PDA interface
requirements are given below.
* See Report No. 372 for more detail.
55
2701
Parallel Data
Adapter
(PDA)
Output Data Lines (l6)
Input Data Lines (l6)
Write Select (l)
Read Select (l)
Write Ready (l)
Read Ready (l)
Demand (l)
End of Record (EOR) (l)
Redundancy Error (l)
Interrupt (l)
PDP/8
Interface
Parity (l)
Parity (l)
Parity Error
OUTPUT DATA LINES,
INPUT DATA LINES.
WRITE SELECT.
READ SELECT.
WRITE READY.
READ READY.
From the PDA to the interface buffer register. While
the word is held in the buffer register, parity is
generated in the interface and compared with PDA
parity.
From the interface buffer register to the PDA. Parity
is generated in the interface and sent to the PDA.
From the PDA to the interface to signal a write
operation from the 2701. This line also generates
an interrupt to the PDP/8 if the write enable flop
is set.
From the PDA to the interface to signal a read operation
from the 2701. This line also generates an interrupt
to the PDP/8 if the read enable flop is set.
From the PDA to the interface. This line notifies
the interface of a data word on the bus. The data is
valid and settled before the line is raised.
From the PDA to the interface. This line notifies the
interface it is available and ready to accept a word
from the bus .
56
DEMAND.
To the °DA from interface.
WRITE COMMAND.
READ COMMAND.
REDUNDANCY ERROR.
END OF RECORD (EOR).
INTERRUPT .
PARITY .
PARITY-INTERFACE TO PDA,
PARITY ERROR
More detailed
Computer Science Report
Signifies the interface has accepted the word on the bus
Signifies the data on the bus is valid. Read data must
be valid for the duration of the demand signal.
(Interface Parity Error). Interface to PDA.' Indicates
the interface has detected a parity error on a write
operation.
Interface to PDA. This line signifies the interface
has completed the operation and will not generate
or accept any more data. This line also
causes the PDA to present device end and channel
end status to the 360 channel.
Interface to PDA. Signals the PDA to interrupt the
CPU through the channel.
PDA to interface. Parity is sent simultaneously with
the data bus. The interface gates the data bus
into the buffer register, and calculates parity
to be compared with the PDA parity.
.The interface buffer register is loaded from the
P.D.P.8 and parity is calculated from the register
contents. The data and parity is sent simultan-
eously to the PDA.
The 2701 PDA signals the PDP/8 when an error is
detected when checking parity on a read operation.
information can be found in the Department of
#323 titled "DEC PDP/8 Interface to IBM 2701 PDA."
57
Microswitch Keyboard (see figures 10, ll)
The microswitch keyboard is an assembly of svitch modules into
a standard array of keys for alphanumeric character entry. Our particular
keyboard is ASCII codes so as to be somewhat compatable with our other
teletype keyboards .
The features of this keyboard that influenced our choice were
(l) the integrated ckt. compatability , (2) the single power supply requirement,
(3) the Hall Effect switch. The integrated ckt. compatability saves a
lot of level conversions and logic changes when applying the keyboard,
to hardware interfaces. The single power supply requirement certainly
makes life simple when using the keyboard with other devices. The Hall
Effect s W itch should allow the operation to be quiet and reliable.
Switch Specifications
Power Requirements
Current Drain
Output Capacity
Temp . Range
Force at Operating Point
Pretravel
Total Travel
Release Point
5V. DC. ±5%
Standby: 15 MA/switch
Quiescent: 100 yuA leakage
Operated: 3.5V § 10MA
Operating: +35° to +125°F
Non operating: -Uo° to l60°F
R.H. 95%
3 oz. nominal
0.125 in. (+0.025 -0.050)
0.187 in. nominal
0.i+0 in. min. from free position
58
Figure 10
PLUNGER
HOUSING
MAGNET/SHUNT
MEMBER
SOLID STATE
CHIP
LEAD FRAME
TERMINALS
Figure 11
59
PROPOSED ADDITIONS
As the general capabilities of the graphic system have increased
through its software development, communications interfaces and hardware
additions it has become more apparent that two things were needed for
applications. These were (l) a more rapid means of local printout and
(2) more terminals for simultaneous graphic operations.
After some looking, the Teletype Inktronic printer was chosen
for the printout. The main reasons for this choice were (l) price ($5300)
and (2) almost no mechanics. The speed of 2 lines/second with no mechanical
carriage return was appealing for our PDP8. The prospects of having a
printer that was completely Electronic was likewise appealing from the
maintenance point of view. A description of the Inktronic is given in
this section.
The method we chose for getting more terminals is described
under the heading of Display Processing Unit. It was taken directly from
DCS Report No. 3^3.
60
INTRONIC PAGE PRINTER
GENERAL
The receive-only "INKTRONIC" system forms characters from a series
of nozzles (jets) located in a horizontal plane in front of the page.
An ink supply cavity, common to ^0 ink nozzles and maintained at a selected
pressure and temperature, enables large quantities of uniform copy to be
recorded on a conventional teletypewriter paper. A high potential charge
on the platen, located directly behind the paper, attracts a stream of
ink at high velocity from the selected nozzle. In transit, the stream
breaks up into tiny droplets which are individually guided (electrostatically)
in a vertical and a horizontal plane to form each character one character
every eight milliseconds at 1200 words per minute. The nozzles are selected
sequentially to print an 80 character line.
PRINTER MODULE LAYOUT
The cabinet supports the nonimpact recording unit and its cover on
an extendable panel (figure 12). A shelf directly below the panel is
provided for certain data or auxiliary sets. A blank panel (except for
a recessed control switch) replaces the data set when used on our P.D.P.8.
All horizontal and vertical drive pulses, directing the excursion of each
stream of ink, are generated by one of four modules housed in the lower
section of the cabinet. A self-contained multivoltage power supply furnishes
the operating potential for the various logic circuits of the system
and initiates the high potential fields for the respective elements of
the printer. The memory logic is contained in the character generated
module with facilities for changing from Baudot to ASCII code or vice
versa. The interface module houses the terminal control logic, etc.
Facilities for supplying a large volume of teletypewriter paper to
61
-RECORDER AND PAPER TRANSPORT MP CRANISM
(Fully Dependent Upon Drive, Memory, and Interface Circuits in Modules Below)
PAPER UNWINDER ASSEMBLY
Supports roll of paper and paper-
out sensing mechanism on sliding
panel.
PAPER TRANSPORT MECHANISM
Facilities for friction feeding a
precise amount of paper from the
external supply roll, across the
platen and outward to the take-up
reel.
PAPER WINDER
ASSEMBLY
RECORDER MECHANISM
Ink reservoir enclosing
pump, manifold, nozzles
and deflecting electrodes.
FUNCTION CONTROL STRIP
Provides control, alarms,
and switching for the overall
set.
SLIDING PANEL
DATA SET
202C - Serial Input
804A - Parallel Input
Data Auxiliary
Set
402D - External
RECORDER DRIVE MODULE
CHARACTER GENERATOR MODULE
HIGH VOLTAGE ON
INDICATOR
MULTIVOLTAGE
POWER SUPPLY
INTERFACE MODULE
Figure 12
Inktronic Printer
62
the printer at high speeds and a motor driven take-up reel to retrieve
the printed copy from the unit are provided by the external paper handling
devices at the rear of the cabinet.
DESCRIPTION
The high speed page recorder and transport (figure 12) is capable of
printing copy at any rate of speed up to 1200 words per minute. Unlike
most telegraphic printing devices, this unit utilizes high potential fields
to transfer ink to the paper and, with the exception of paper feeding, line
feeding, and ink circulating (pump mechanisms, it has no moving parts.
The nonimpact printing function is dependent not only upon the
initiation of a high velocity stream of ink from the selected nozzle, but
also upon the direction of this trace to form a character. Printing takes
place from left to right across the page under control of the recorder
drive circuits. The recorder drive circuits control the flow of ink with
the valving electrode as well as the forming of characters with the horizontal
and vertical deflection electrodes. The maximum length of line is 80
characters .
Paper for the recorder and transport is fed from a U- 1/2 inch diameter
roll, through the paper transport mechanism, to the line feed mechanism
which controls the paper as it passes the ink nozzles. The paper tensioner
assembly pulls the printed paper from the platen and also keeps it tightly
against the platen during printing.
Illumination of the printing station is provided by a fluorescent
lamp assembly attached toward the front of the cover. The plastic lens
directs the light over the full width of the copy to be viewed.
The printing portion of the nonimpact page recorder consists of an
ink tank with a means of maintaining consistent pressure on i+0 ink nozzles,
and a series of (four-element) electrodes to initiate and control the ink
63
stream. The platen, which attracts the ink from the respective nozzles,
is located on the paper transport unit. The ink tank, enclosing the
electrodes and ink handling components, extends across the entire width
of the unit, and forms the front side of the paper transport mechanism.
The supply tank at the front of the unit has a liquid ink capacity
of about one bottle of "INKTRONIC" ink TP301168 (12 ounces per bottle).
The manifold, with its kO nozzles and attached character forming electrodes,
is located near the top of the tank and aligns with the platen. A continuous
flow of ink is forced into the manifold reservoir by a diaphram type pump.
The reservoir spillway maintains a certain ink level and enables the
excess ink to be returned to the tank. Individual ducts connect the common
reservoir with the respective nozzle. An electric heating element, embedded
in the manifold below the nozzles, warms the liquid to facilitate an even
flow of ink and the printing of a legible copy.
PRINTING
The recorder assembly consists of forty sets of printing units.
Each printing unit consists of a nozzle, a valving electrode, a pair of
vertical deflection electrodes, and a pair of horizontal deflection electrodes.
Across the front of the print head assembly is the mask. There is a rectangular
hole in the mask in front of each printing unit. Each printing unit
prints two characters, one in a left matrix and one in a right matrix. A
maximum of 32 points in the matrix are available for forming one character.
However, one of these points must be used to end the character. Therefore,
31 points in the matrix are the maximum area available for the actual printing
of one character (figure 13).
The manifold supports the nozzles and provides a supply of ink to
each of the forty nozzles. The manifold and nozzles are held at a constant
negative voltage of -1900 v dc.
6h
BDUKT
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JET DOWN-LEFT
JET DOWN-RIGHT
Figure ik
Basic Tracing Pattern of Typical Electrode Assembly
65
VERTICAL DEFLECTION ELECTRODE
Upper Element:
Potential to direct ink to bottom edge of
character: 1100 (+50) v dc. Voltage
differential to form character: 500 (+25) v
dc. Jet down function to restrict printing:
Min 780 v— -Max 820 v
Lower Element:
Potential to direct ink to top edge of
character: 1100 (+50) v dc. Voltage
differential to form character: 500 (+25) v
dc. Jet down function to restrict printing:
Min 1880 v~-Max 1920 v
SINGLE GUN ELECTRODE
ASSEMBLY
MANIFOLD (40 NOZZLES)
POTENTIAL - 1900 V DC
,_ 560 (+30) VOLT DIFFERENTIAL
1400 (+25) VOLT DIFFERENTIAL
560 (+30) VOLT DIFFERENTIAL
PLATEN POTENTIAL
+10, 000 (+400) V DC
VALVING ELECTRODE:
"ON" FUNCTION +550 (+20) V DC;
"OFF" FUNCTION (+1) V DC
,_500 (+25) VOLT
DIFFERENTIAL
v NOMINAL VALUES/
1600 V(HV)— !
100 V (HV)
3
CROSSOVER
1100 V(LV)
1600 V (LV)
'NOMINAL VALUES %
MASK: POTENTIAL
+5000 (+200) V DC
HORIZONTAL DEFLECTION ELECTRODE
Right Element:
Potential to direct ink to left side of left
character: 1360 (+50) v dc. Voltage
differential from left side to right side of
any full width character: 560 (+30) v dc.
Voltage differential between left side of left
character and right side of right character:
Min 1375 v— Max 1425 v
Left Element:
Potential to direct ink to right side of right
character: 1440 (+50) v dc. Voltage
differential from left side to right side of
any full width character: 560 (+30) v dc.
Voltage differential between left side of left
character and right side of right character:
Min 1295 v-*-Max 1345 v
Figure 15
Nominal Electrode Voltages
66
HORIZONTAL DEFLECTION ELECTRODE
(LEFT ELEMENT)
CHARACTER HEIGHT
1600
1544
1488
1433
1377
1S22
1266
1211
1155
1100
1044
988 -
933
877
822
800
OO OQOOOO
•0 c- V • IA * n M
N N N N N N N N
OOOOOOOO
8 8 S £ S I S3
CHARACTER
1
1"
1
1
10
11
12
13
14
15
16
1100
1155
1211
1266
1322
1377
1433
1488
1544
1600
1655
1766
1822
1877
1900
N ELECTROD!
ENT)
9
17
N ELECTRODI
[ENT)
8
18
7
^
19
6
20
5
21
L DEFLECTIO
(UPPER ELEM
4
22
OS
3
23
2
24
-1
30
29
28
27
26
25
1
1
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HORIZONTAL DEFLECTION ELECTRODE
(RIGHT ELEMENT)
LEFT MATRIX
RIGHT MATRIX
-VALVE DOWN
MASK POSITION
Figure 16
Character Matrix and Deflection Voltage
67
The valving electrode, in front of each nozzle, controls the flow
of ink from that nozzle. The valving electrode derives its potential of
+ 550 v dc (figure 15) from the spacing drive power supply contained in
cabinet. The spacing drive power supply uses the input signals, received
from the character generator, to select the appropriate valving electrodes
which will turn on the appropriate nozzles for printing. When the valving
electrode is at the off voltage (0 v dc), no ink issues from the nozzle.
When it is at the on voltage (+550 v dc), ink is extracted from the nozzle
in the form of a droplet stream. The droplets, approximately 0.001 inches
in diameter, pass through the hole in the valving electrode and proceed
with increasing velocity to the region of the deflection electrodes.
The first pair of deflection electrodes which influence the path of
the ink droplets are the vertical deflection electrodes. These electrodes
are supplied with their deflection voltage (figure 15) by the high voltage
power supply which is modulated by the digital-to-analog converter for
vertical printing contained in lower cabinet. The vertical deflection
electrodes, one above and one below the jet, are arranged to form a horizontal
slot. If the upper electrode is at a higher voltage than the lower, the
ink droplets will be deflected upward; or conversely, if the lower electrode
is at a high voltage than the upper, the path of the droplets will be
deflected downward. The average voltage of these two electrodes is higher
than that of the valving electrode; therefore, the droplets are accelerated.
The next set of electrodes, the horizontal deflection electrodes,
are arranged to form a vertical slot. These electrodes are supplied with
their deflection voltage (figure 12) by the high voltage power supply
(contained in the lower cabinet) which is modulated by the digital-to-analog
converter for horizontal printing. Similar to the above description, the
68
droplets can be deflected horizontally by varying the electrode voltage.
The average voltage of this electrode set is higher than the previous set;
so, again the ink droplets are accelerated.
In their flight toward the paper, the ink droplets encounter one
more electrode, the mask. The mask derives its constant +5000 v dc (figure 15)
from the power supply located at the rear of the paper handler. When
a nonprinting condition exists, the mask acts as a shield. That is, the
voltage at the deflection electrodes is such that the stream of ink droplets
are deflected downward striking the lower portion of the mask. The ink
droplets are therefore prevented from continuing their journey to the
paper and drain down the mask to be returned to the ink supply in the
manifold. When a printing condition exists, the voltage is selected to
hold the mask voltage at the same average voltage established by the
electric field between the previous electrode set and the platen. As
far as the ink droplets are concerned, the mask is invisible. Also the
mask provides some protection for the deflecting electrodes.
A fixed amount of time is available for printing each character.
At 1200 words per minute this is 8 milliseconds. However, characters
built up from relatively few dots in the matrix pattern, such as the letter
I will be finished printing early and a wait period occurs. Even though
the ink jet is turned on, it must not print. This is accomplished by
deflecting the ink jet downward to a considerable distance below the
printing area where it strikes the mask shown in figure l6. Ink that
hits the mask cannot reach the paper, so deflecting the ink downward
is equivalent, in effect, to turning off the ink jet. Whenever a jet
is turned on by the valving electrode (ink flowing) but is not printing,
it is directed toward the mask. This situation occurs at three different
69
times in the printing process: first, during the time allowed for ink
to start flowing, but before printing has begun; second, after a left
character has been printed but before a right character has started; and
third, after printing has been completed and during the time allowed to
turn off the ink jet.
To print a line of characters from left to right, each of the kO
ink jets could be turned on in successize order. Thus, the first jet
could be turned on, print two characters followed by the second jet to
print the next two characters, and so forth. Each individual jet prints
first a left and then a right character until the entire line is printed.
The return to starting position for a new line is called reset and is
initiated by a CARRIAGE RETURN (reset) signal.
To understand the character signals which must be supplied as input
signals to the printer drive for providing the required vertical and
horizontal deflection at the electrodes, refer to figure 13. This basic
matrix pattern shows 12 possible positions above the zero position. The
seven horizontal positions are represented by a 3-bit binary code, as shown
above the matrix pattern. Any position in the matrix pattern may be
located by specifying four vertical bits and three horizontal bits.
TO
DISPLAY PROCESSING UNIT
The Display Processing Unit (DPU) is the interface between
the PDP8 memory and the remainder of a display system. (The display
system configuration is shown in Figure IT). Because this interface
executes programs from memory, because it has an instruction repertoire,
and because programs can be written for the display processor, it can
be thought of as a computer. It is a special kind of computer with
capabilities oriented toward making pictures rather than performing
computational tasks. Many of its instructions are descriptive of
drawing operations rather than computational operations. Because the
DPU operates in conjunction with a general purpose computer, "general"
computing capabilities were not given to it. The DPU fetches data from
the PDP8 core memory, decodes it and generates picture information. This
information is then transferred via a core memory buffer to a track of
the central disk buffer, thus releasing the DPU for other tasks. The DPU
performs the same functions that the DEC 338 does, with the additional
capabilities of controlling and refreshing the picture at as many as l6
display terminals. All commands are transferred to the DPU via the PDP8
single cycle data-break system. The programmer may specify which terminal
he wishes to access at any time.
A special hardware scheme is used to generate the incremental
commands from the combinations of codes which form lines and characters.
The order of execution of all the Control State instructions,
PDP8 display oriented instructions and the picture generation, is
determined by a central control unit. The unit is composed of several
sequential control points which govern the data flow in the DPU.
An interrupt queueing scheme controls the data communication
between the display terminals and the DPU.
71
o
•H
u
B
bO
•H
>
CO
Pu
w
•H
O
72
A central disk buffer holds the picture information for up to
16 display terminals, with a single track of the disk being dedicated to
each of the terminals. Each of the tracks has its own read-head and line
driver. The disk rotates at 30 revolutions per second, so the picture
on each scope is refreshed at 30-cycle rate. This rate is high enough to
give a flicker- free display. At the data rate used, 10 points /second
are plotted by the display terminals .
The picture on each track of the disk is specified in terms of
simple 3-bit incremental command. These commands are decoded by a display
control at each of the scope terminals where X-Y deflection signals are
produced to position and display points. The commands allow the beam to
be moved a certain number of units in any direction on a 102U x 102U grid
(left-right, up-down, or diagonally) covering a 10" x 10" area on the
s cope face .
Information corresponding to the initial values of X and Y,
four spot intensities, scale factor, P. B. enable, and joystick interrupt-
enable are also stored on the disk. Zoom option information is
transferred directly to the display terminal, so that frames may be
expanded by a factor of two, four, or eight.
The operator of the CRT display can communicate immediately with
the DPU and the PDP8 processor by using the incremental joystick or the
push-button control box.
The DEC 338, in order to generate typical pictures, uses about
30,000 moves per frame, and the picture has to be reconstructed and
regenerated 30 times per second to avoid excessive flicker. Also, the
338 may access the PDP8 via the data-break system only once in three
73
PDP8 memory cycles, degrading the speed of generating points and vectors
which results in lower picture capacity. The DPU disk "buffer contains
about 100,000 bits or 33,000 instructions in a full track. A track of
data corresponds to a picture containing 660" of drawings . This means
66 screen widths of horizontal or vertical lines (in scale of 2) or
about 1500 characters, or a proportional mix.
Consequently, the DPU disk configuration with its independent
picture refreshing capability, easily handles display files like those
executed by the DEC 338.
lh
ALPHABETIC IOT LIST
Data Disk
6551
6552
655U
6561
6562
656U
DECTAPE
6761
DTRA
6762
DTCA
676I4
DTXA
6771
DTSF
6772
DTRB
677^
DTLB
DISPLAY
6051
6052
605^
6061
6062
606U
6071
6072
607^
6132
6135
61U2
61U5
6151
6152
615U
6155
6161
6162
6i6h
6165
6171
6172
617U
6303
630U
6311
6312
631k
RPDP
RXP
RYP
RDAC
RSI
RS2
RPB
RSG1
RSG2
SLLP
SPDP
SPSP
SIC
SPES
SPEF
STPD
LBF
CFD
RES2
INIT
SPSF
SPMI
RES1
SCG
RCG
Gate AC to Address Register
Clear Disk Done and Interrupt Enable
Enable Interrupt
Skip on Disk Done
Transfer AC contents to Disk Control
Read Status Register A
Clear Status Register A
Load Status Register A
Skip On Flags
Read Status Register B
Load Status Register B
Read Push Down Pointer
Read X Position Register, bits 1-12
Read Y Position Register, bits 1-12
Read Display Address Counter
Read Status 1
Read Status 2
Read Push Buttons
Read Slave Group 1
Read Slave Group 2
Skip on Light Pen Hit Flag
Set the Push Down Pointer
Skip on Slave Light Pen Hit Flag
Set Initial Conditions
Skip on External Stop Flag
Skip on Edge Flag
Stop Display (External)
Load Break Field
Clear Display Flags
Resume After Stop Code
Initialize the Display
Skip on Internal Stop Flag
Skip on Manual Interrupt
Resume after Light Pen Hit, Edge, or External Stop Flag
Set Character Generator
Read Character Generator
Skip if Clock Flag =
Clear Clock Flag and Enable Clock Interrupt
Disable Clock Interrupt
75
EXTENDED MEMORY
6201
CDFO
6202
CIFO
6204
6211
CDF1
6212
CIF1
6214
RDF
6221
CDF2
6222
CIF2
6224
RIF
6231
CDF 3
6232
CIF3
6234
RIB
62 4l
CDF4
62 42
CIF4
6244
RMF
6251
CDF5
6252
CIF5
6254
6261
CDF6
6262
CTF6
6264
6271
CDF 7
6272
CIF7
6274
ILLIAC
III
6731
6732
6734
6741
67^2
67M+
6751
6752
6754
INKTRONIC
61+Ui
6442
6444
6451
6452
6454
Change to Data Field
Change to Instruction Field
Change to Data Field 1
Change to Instruction Field 1
Read Data Field
Change to Data Field 2
Change to Instruction Field 2
Read Instruction Field
Change to Data Field 3
Change to Instruction Field 3
Read Interrupt Buffer
Change to Data Field
Change to Instruction Field 4
Restore Memory Field
Change to Data Field 5
Change to Instruction Field 5
Change to Data Field 6
Change to Instruction Field 6
Change to Data Field 7
Change to Instruction Field 7
Skip on Device Ready
Clear Device Ready, Information Ready
Clear Data Ready
Skip on Data Ready
Gate Contents of AC and Data Accepted
External Device Comp.
Skip on Printer Ready
Enable Interrupt
Disable Interrupt
Skip on Character Done
Clear Character Done
Gate Character and Start Print
76
Interface to 630
6631
6632
663I+
66U1
66 1+2
6641+
MUSIC MAKER
6701
6702
670U
PDA-2701
64oi
ICR1
61+02
ICR2
61+01+
ICR1+
61+11
SRR
61+12
ERI
61+11+
CRD
61+21
SRD
61+22
DRI
61+21+
SWCR
61+31
SPE
61+32
CPE
61+31+
SEM
6501
ICW1
6502
ICW2
650I+
ICW1+
6511
SWR
6512
EWI
651I+
CWD
6521
SWD
6522
DWI
652I+
PROGRAM
INTERRUPT
6001
ION
6002
IOF
Skip on Flags
Clear AC and Receiver Flag
Gate Receiver Output to AC
Clear Interrupt Enable
Set Interrupt Enable
Clear Transmitter Flag and Input Data from AC
Reset both flip flops to "0"
Complements flip flop "l"
Complements flip flop "2"
Initiate Channel Read
Gate Contents of AC into Data Address Register
(not used)
Skip on Read Ready
Enable Read Interrupt
Clear Read Done
Skip on Read Done
Disable Read Interrupt
Set Word Count Register
Skip on Parity Error
Clear Parity Error
Set Extended Memory
Initiate Channel Write
Gate Contents of AC into Data Address Register
(not used)
Skip on Write Ready
Enable Write Interrupt
Clear Write Done
Skip on Write Done
Disable Write Interrupt
(not used)
Turn Interrupt On
Turn Interrupt Off
77
SYLVANIA TABLET
6711 Skip on Tablet Ready
6712 Disable Interrupt and Clear Data Ready
671^ Enable Interrupt
6721 Read Tablet "X"
6722 Read Tablet "Y M
672I+ Read Tablet "Z"
TELETYPE-KEYBOARD/READER
Skip if Keyboard/Reader Flag = 1
Clear AC and Keyboard/Reader Flag
Read Keyboard/Reader Buffer, Static
Clear AC, read Keyboard/Reader Buffer and
Clear Keyboard Flag
TELETYPE-TELEPRINTER /PUNCH
Skip if Teleprinter /Punch Flag = 1
Clear Teleprinter /Punch Flag
Load Teleprinter/Punch Buffer, Select
and Print
60k6 TLS Load Teleprinter /Punch Buffer, Select and
Print, and Clear Teleprinter /Punch Flag
6031
KSF
6032
KCC
603h
KRS
6036
KRB
601+1
TSF
60 k2
TCF
6ohh
TPC
78
PDP-8 IOT LIST
6001 ION
6002 IOF
600U ADC
6101
6102
6lOh
6011 Save for high speed reader 6lll
6012 " 6112
601U " 6llU
6021 Save for high speed punch 6121
6022 " 6122
602k " 612U
6031
TTY
Reader
6032
ti
603h
11
60U1
TTY
Printer
60I+2
ti
6okk
11
6051
338
6052
605U
6061
6062
606U
6071
60T2
607^
6131
338
6132
11
613^
11
6lUl
11
6lU2
11
6lUU
n
6151
11
6152
11
615U
n
6l6l
11
6162
11
6164
it
6171
11
6172
11
617U
11
79
6201 Extended Memory
6301 Type VC38 Character Generator
6202 "
6302 "
6201+ "
6301+ "
6211 "
6311 338 Real Time Clock
6212 "
6312 "
621U "
631U "
6221 "
6321
6222 "
6322
622U "
6321+
6231 "
6331
6232 "
6332
623U "
6331+
62Ul "
63I+I
621+2 "
631+2
621+1+ »
63I+I+
6251 "
6351
6252 "
6352
6251+ "
635U
6261 "
6361
6262 "
6362
626U "
6361+
6271 "
6371
6272 "
6372
6271+ "
637U
80
61+01 PDP-8 to 2701
61+02
6Uoi+
61+11
61+12
6UH+
61+21
6U22
6U2U
(not used)
6501 PDP-8 to 2701
6502
650I+
6511
6512
65lU
6521
6522
652U
(not used)
6431 PDP-8 to 2701
6432
6434
6 4 Ul Inktronic Printer
61+1+2
6U1+1+
61+51
61+52
6U5I+
61+61
6U62
61+61+
61+71
6I+72
6U7I+
6531
6532
6531+
65I+I
65I+2
65I+I+
6551 Data Disk
6552
6554
656I
6562
6561+
6571
6572
81 6 ^
6601
6602
660h
6611
6612
66H+
6621
6622
6621+
6631 PDP-8 Interface to 630
6632
663k
661+1
661+2
66hk
6651
6652
665U
6661
6662
6661+
6671
6672
667I+
6701
Music Maker
6702
IT
670I+
II
6711
Sylvania Tablet
6712
11
671 1+
it
6721
11
6722
11
672U
11
6731
ILLIAC III
6732
it
6l3h
it
67>+l
ti
671+2"
67I+U
tt
6751
11
6752
ti
6751+
it
6761
DECTAPE
6762
tt
676I+
it
6771
ti
6772
tt
6771+
tt
82
Form AEC-427
16/68)
AECM 3201
U.S. ATOMIC ENERGY COMMISSION
UNIVERSITY-TYPE CONTRACTOR'S RECOMMENDATION FOR
DISPOSITION OF SCIENTIFIC AND TECHNICAL DOCUMENT
( See Instructions on Reverse Side )
1. AEC REPORT NO.
COO-li+69-0151
2. TITLE
Graphics 8
Graphics Hardware - 1U69 Gear
3. TYPE OF DOCUMENT (Check one):
nta. Scientific and technical report
I I b. Conference paper not to be published in a journal:
Title of conference
Date of conference
Exact location of conference
Sponsoring organization
□ c. Other (Specify)
4. RECOMMENDED ANNOUNCEMENT AND DISTRIBUTION (Check one):
\A a. AEC's normal announcement and distribution procedures may be followed.
I I b. Make available only within AEC and to AEC contractors and other U.S. Government agencies and their contractors.
I I c. Make no announcement or distrubution.
5. REASON FOR RECOMMENDED RESTRICTIONS:
6. SUBMITTED BY: NAME AND POSITION (Please print or type)
C. W. Gear
Principle Investigator
Organization
Department of Computer Science
University of Illinois
Urbana, Illinois 6l801
Signature
^l\o£kk> C i^--
Date
December 2U,' 1969
FOR AEC USE ONLY
7. AEC CONTRACT ADMINISTRATOR'S COMMENTS, IF ANY, ON ABOVE ANNOUNCEMENT AND DISTRIBUTION
RECOMMENDATION:
8. PATENT CLEARANCE:
a. AEC patent clearance has been granted by responsible AEC patent group.
I) b. Report has been sent to responsible AEC patent group for clearance.
1 1 c. Patent clearance not required.