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To renew call Telephone Center, 333-8400 UNIVERSITY OF ILLINOIS LIBRARY AT URBANA-CHAMPAIGN DEC 2 9 19£0 L161— O-1096 Digitized by the Internet Archive in 2013 http://archive.org/details/optimumnetworkde375swee 7$ y-yisLstAi Report No. 375 OPTIMUM NETWORK DESIGN USING NOR-OR GATES BY INTEGER PROGRAMMING *y Richard Stuart Swee February 2, 1970 THE LIBRARY OF THE MAR 3 1970 UNIVERSITY OF ILL HftR- 3W& Report No. 375 OPTIMUM NETWORK DESIGN USING NOR-OR GATES BY INTEGER PROGRAMMING hy Richard Stuart Swee February 2, 1970 Department of Computer Science University of Illinois Urbana, Illinois 618OI This work was submitted in partial fulfillment of the requirements for the degree of Master of Science in Computer Science, February, 1970. iii ACKNOWLEDGMENT I would like to express my most sincere gratitude to my thesis advisor, Professor Saburo Muroga for his suggestion of the topic and constant encouragement which made it a pleasure to do this research. I am grateful to Charles Richmond Baugh and to Toshihide Ibaraki without whose cooperation and help this paper could not have been written. I dedicate this work to my wife, Elaine, and to my parents without whose understanding this paper would not have been completed. IV TABLE OF CONTENTS Page 1. INTRODUCTION 1 2. OPTIMUM NETWORK DESIGN USING NOR-OR GATES BY INTEGER PROGRAMMING 2 3. INTEGER PROGRAMMING AND IMPLICIT ENUMERATION k k. NOR-OR SYNTHESIS 8 k.l Definition of NOR-OR gate 8 k.2 Objective of NOR-OR synthesis and relation to Hellerman 11 k. 3 Restrictions on networks to be synthesized 11 h.k Definition of the problem 13 U.5 Presentation of the problem inputs lk 5. ANALYSIS OF RESULTS 29 6. CONCLUSION 33 LIST OF REFERENCES 3I+ APPENDICES 36 1. INTRODUCTION This paper presents the results obtained when a modified version of numerical integer linear programming was used to find the optimum networks of NOR-OR gates for ho representative three variable logic functions. These representative functions represent equivalent classes under permutation of variables and negation of a given function. The type of gate which we used to realize these functions was restricted to a NOR-OR gate. The optimum networks for the kO representative functions were r on obtained by an exhaustive method by L. Hellerman, (using only NOR gates or only NAND gates). Thus this report is the first attempt to catalog the optimum networks of 3- variable functions using NOR gates, OR gates, or both, in a network. It was found that NOR-OR computation time increased exponentially as the number of gates in a network increased. OPTIMUM NETWORK DESIGN USING NOR-OR GATES BY INTEGER PROGRAMMING Based on the integer linear programming approach discussed in the ["121 ri3l previous papers ">^ optimum combinational networks of NOR-OR gates have been synthesized. This paper presents the computational results. The integer programming algorithm used for solving those problems is the implicit enumeration method and it is described in detail elsewhere In this paper the optimal networks of NOR-OR gates for most of the three variable switching functions are exhausted by the integer programming approach (kO representative functions of equivalent classes by permutation of variables and negation of the function). The computation was done on an IBM 360/751 with the H level FORTRAN IV compiler. It took forty minutes for synthesizing optimum NOR-OR combination networks for all but five of the kO three variable functions. However, the computation time exponentially increases as the number of gates in a network increases. Thus after all but five of the kO functions had been solved we decided to use a modified approach on the last five functions in order to speed up computation. This method is termed the all interconnection formulation The synthesis of optimum networks of the last five functions has not been accomplished at the time this paper was written and so is not presented. This thesis is organized as follows. Section 3 explains the integer programming algorithm and generally describes its operation. Sections U.U and U.5 link sections 3 and U.l, U.2 and k.3 by explaining how an integer programming problem was defined for optimizing NOR-OR networks. Appendices 1.1, 1.2 and 1.3 present the results of the actual computer run, applying the integer programming algorithm to NOR-OR network optimiza- tion. Sections 5 and 6 analyze these results. All symbols used in this paper are defined in Appendix l.k. 3- INTEGER PROGRAMMING AND IMPLICIT ENUMERATION This section presents the outlines of the integer programming problem and implicit enumeration algorithm for solving it. For detailed description, see the references for example. The computer code used for the network synthesis is discussed in the reference . It is a result of simplification and modification of the original implicit enumeration algorithm in order to improve computational efficiency. An integer programming problem with n unknown variables and m constraints is in general stated as follows: Minimize c* x* subject to A x* + ft > 0, where c* is an n-dimensional vector of non-negative constants, tf is an Tri- dimensional vector of constants and A is an (m x n) matrix of given coefficients and x* is an n-dimensional vector of variables. In our case, all variables J? are integers which assume only 1 or 0. Sometimes this is referred to as the zero-one integer programming problem. implicit enumeration algorithm has been computationally proved to be one of the most efficient methods for solving this type of zero- problem. It implicitly enumerates all the 2 solutions without explicitly and exhaustively examining all of them, and picks up the best feasible solution. Let us start with several definitions. When all the variables in 3? are assigned 1 or it will be called a solution . If a solution satisfies the St + V > 0, it will be called a feasible solution and if not, an in feasible solution. A feasible solution that minimizes c* x* 5 is an optimum feasible solution . A partial solution S is defined as an assignment of "binary values to a subset of the n variables. Any variables which are not assigned are called free variables . A completion of a partial solution S is a binary assignment to all free variables. Let us outline the implicit enumeration algorithm as it is shown in Figure 3-1-1* With a given partial solution S and the incumbent solution (the feasible solution having the smallest value of the objective function obtained thus far), the block entitled "CHK-IEQ" is entered. At this point, examine whether some of the free variables must be 1 or if each inequality is to be satisfied. Scanning through the inequalities until no more free variables are assigned, S with these free variables assigned becomes a new partial solution S . Next the partial solution S is checked to determine which of the following 3 cases occurs. (1) Feasible : The completion of S obtained by setting all free variables to is found to be feasible. It is compared with the incumbent and the better of the two is maintained as the incumbent. The backtrack 2 procedure is initiated to obtain a new partial solution S by changing seme of the assigned variables according to a certain rule.* (2) Infeasible : If at least one inequality is not satisfied by S whatever binary values are assigned to the free variables, then S is discarded immediately by initiating the backtrack procedure. The 2 backtrack procedure forms a new partial solution S from S . (3) Augment S : If neither of the above two cases occur, a free 2 variable is assigned to 1, forming S . The choice of this variable greatly affects the convergence and it should be made according to the type of problem being solved. [71 *The backtrack procedure was first proposed by Glover . A detailed explanation can also be found in *• * , L9J and will not be described in this report. 2 After replacing 3 with S , the entire procedure is repeated by reenterin g the block "CHK-IEQ". Figure 3.1.1 Implicit enumeration algorithm ■ .jJant S ) 7 •- VAh -.-lit S by i free to obtain S S = cp C'HK - IEQ Clik inequ. with S . Assign free variables, Form S ! ;ial Solution \l s 1 1 .. 1 (Feas Lble) > ' Keep better solution as , . Incumbent (infeasible ) Backtrack foims S 7. By cycling through this procedure repeatedly, the computation results in the implicit enumeration of all possible solutions. When the computation terminates, the incumbent is the optimum solution. The checking procedure of each inequality such that one of cases (l), (2), and (3) is quickly identified is explained in . The implicit enumeration algorithm converges in a finite number of steps, but the efficiency of the algorithm heavily depends on the nature of an individual problem. Our computational experience shows that tailoring the block labeled AGMT-VAR in Figure 3«1«1 ("the subroutine which augments the partial [Q] solution when (3) occurs) to a given particular problem speeds up the convergence. k. NOR -OR SYNTHESIS U.l Definition of NOR-OR gate The NOR-OR gate is a combinational gate which may supply both the logical OR of n input variables and its negation to the gate. From a hardware viewpoint it might be noted that this type of gate is easily obtained in many hardware configurations and should not be looked upon as only an academic curiousity. An example is emitter coupled logic which can realize a NOR-OR gate easily. As a result of its characteristics the NOR-OR gate may in specific networks simplify to be only a NOR gate (if the OR output is not used) or an OR gate (if the NOR output is not used) in addition to the possibility of supplying both NOR and OR output values. The NOR-OR gate of three inputs may be symbolized* as: a ~ " :: ;_:IE> a -~ p Algebraically the two outputs are expressed as two products: a P = a b c • = a v b v c where ct and a are variables which specify existence of NOR and OR output connectio; ■ rations of all variables and symbols used in this j The value of a and a determine the nature of the gate. This is explained in the following table: Table U.l.l a a GATE TYPE Non-existent gate NOR gate OR gate NOR-OR gate Both a and a (from gate i) cannot be connected to the same gate since this produces constant output values. Mathematically this can be stated as: a., + a., < 1 (for all i < k < R) lk -lk - - ' A more detailed explanation is given in the section on additional inequalities. While a and a in the above diagram determine a gate type (OR, NOR, NOR-OR ), they do not specify the output value of a gate. P indicates the value of an output (0 or l) and P its complement. Hence the " output " of a gate is determined by a combination of two factors; the presence or absence of an output connection (cu or a) and the output value of a connection (P or P). Hereafter the term output will refer to the product aP and the product aP. NOR output connection will refer to a, and OR output connection will refer to a. Finally the OR output value will refer to P and the NOR output value will refer to P or (l - P). All of these variables are Boolean and are equal to 1 if the connection is present and if the connection is absent. The inputs a, b, and c can be grouped into two types; external inputs and internal inputs. If b, for example, is an external input , then it is represented by the product of two factors w and x, where w represents the presence (w = l) or absence (w = 0) of an external variable x to a gate and x represents the value of the external variable, or 1. Note that 10 only x , x and x are available as inputs, but x , x and x are not available . If b, for example, is an internal input , then it is represented by aP + aP which is the output of another gate (within the network) to gate i. The symbol 3 is used as equivalent to aP + aP. * With the aide of the symbols and concepts thus far defined, we can show the relationship** between inputs and outputs of a N0R-0R gate as: aP = ( W;L x 1 ) (w 2 x 2 ) (w x ) (p x ) (3 2 ) ... aP = w x v w x 2 v w x v 3 v p v ... The terminology used for inputs, then, will be similar to that used to describe output connections and values. An input will refer to the logical AND of wx; input connection will refer to w (l if present, if absent) and input value will refer to x (0 or l). Since we are dealing with three variable functions, the concept of the variable x becomes more complex. We must allow for 8 possible relationships among x , x p and x as shown in the following table. Table U.1.2 j x J 1 x J X 2 x J 3 1 2 l 3 1 h 1 1 5 1 6 1 1 7 1 1 1 1 1 The purpose for 3 is described in detail in section U. 5- 5 below. o*ee external inputs are indicated in these relationships. This is not general, but is used since it was part of the definition of the problem this paper solv 11 k.2 Objective of NQR-OR synthesis and relation to Hellerman The objective of NOR-OR network synthesis (as applied to this paper) is to optimize a network consisting solely of NOR-OR gates based on two criteria: (1) Minimize number of NOR-OR gates first (2) Minimize number of connections second (both internal and external) L. Hellerman attempted a similar problem using all NOR gates in his network. His method was to find all optimum solutions by actually exhausting all the network configurations and then finding the "best" network among them for each function. Our computation time, of course, was much less than Hellerman's since the modified integer linear programming problem described above was run on the IBM 360/751 computer and Hellerman^ was run on the slower IBM 7090. However, if our integer programming algorithm had been run on the IBM 7090 the computation time would be approximately 1/6 of Hellerman's time. 4.3 Restrictions on networks to be synthesized We assumed that the network was a feed-forward network. A feed- forward network may be defined as a network consisting solely of logic gates j whose output connections Oi ., and a can be connected to any j. Figure ^.3*1 shows the form of a feed-forward network and gives some visual explanation of the meaning and relationship of variables to be used throughout the rest of this paper. Note the manner in which the gates are numbered. The "last" gate (output gate) has the highest number, thus conforming with the definition of a feed- forward network stated above. Y> o c I PC 5 OJ HOJ OO OJ HOJ ro H --H < iH CO H «-H CVi * > > 1X 13 Additional assumptions limit the number of external input connections to any gate in a network to three and the complements of external input values were assumed not to be available. Farther we force the output gate to be either a NOR gate or an OR gate, but not both. Finally we force the other gates in the network to be only NOR-OR gates. h.k Definition of the problem Integer linear programming was the method used to solve the synthesis problem. We made the list of optimum networks for three variable functions by setting up a sequence of problems. The first problem was to find all Boolean functions that could be realized with one gate, then remove those which were solved and redefine the integer programming problem to find all functions left in the entire set of three variable functions which could by optimized with two gates. This process was continued with an increasing number of gates until all functions were realized. Each problem was defined in the form of an integer program statement. It was composed of: (1) The objective function for an R gate feed-forward network (See section 4.5.1) (2) The basic gate description inequalities for an R gate feed- forward network (See section 4.5.2) (3) The additional inequalities to restrict solutions based on the properties of the NOR-OR gate (See section k. 5*3) The linear inequalities can be stated in general for all of the sequence of problems and then evaluated for a given number of gates for [121 each problem. See for detailed explanation of the derivation of the inequalities. It might be pointed out that the additional inequalities are not needed to describe the problem in a theoretical sense. However, these narrow the solution space of the integer programming problem and thereby reduce the computation time greatly. Ik U.5 Presentation of the problem inputs h. 5.1 Objective function The objective function for a given number of gates R is to minimize the sum of the following three factors: (1) The number of internal OR interconnections from gate i to gate j (termed a. .)* (2) The number of internal NOR interconnections from gate i to gate j( termed a. . ) (3) The number of external connections (w ) to gate k from the input variable x , . Symbolically this is: R k - 1 3 (1) MET [ E [ E (a + a. R ) + E (w£)] k = li=l -u=l i ^k In words this is: R INTERNAL EXTERNAL MIN [ E [E (CONNECTIONS) + E (CONNECTIONS) ]] k = 1 TO GATE k TO GATE k k. 5«2 3asic description of gates These consist of the basic gate description inequalities. They describe what a NOR-OR gate "is" in a mathematical expression. . -2.1 Gate descriptive inequality This inequality set describes the relationship between wx, f3, and the outputs P of a NOR-OR gate. It states: Llx 1.^ 11 symbols in this paper. 15 (2) Z w k x/ J ) + Z 3.,^<0+UP.^ t - 1 * l i - 1 lk k i ^k (3) Z w k x, (d) + 2 p.. (J) > 1- U (1 - pj j) ) i ^k (J = 1, ..., 8) (k = 2, ..., R - 1) U is chosen to make one of the inequalities non restrictive, depending on the value of P. If P = 1, then inequality (2) becomes: Z w k x/ J ') + Z P., ' < + U 1=1 l l 1 = 1 lk ~ i ^k It can be easily seen that the left term will always be < 10 for R = "J. Hence if U = 10, (2) becomes nonrestrictive. The second inequality (3) is restrictive if P = 1 since it becomes: Z W* x/ j) + Z R (J) > 1 I = 1 l l i - 1 ik " i^k forcing at least one of the terms to be 1. The inequalities repeated for each of the 8 possible input values * (J) as: / . % EXTERNAL INTERNAL / . v 1 - 10 (1 - P k ) < 2 (INPUTS ) + Z (INPUTS ) < 10P U } TO GATE k TO GATE k 16 h. 3.2.2 Description of last gate Since the last gate (k = R) must provide the output of the function desired (due to the feed-forward assumption), the inequality set above (k. 5.2.1) cannot be used to describe this gate. More specifically, the main difference between this gate and all the others in a given network is that the last gate can only have one output. That is, it cannot be a NOR-OR gate. It can be either an OR gate or a NOR gate. To state this mathematically, a new variable \ was introduced. By convention, if h. = 1, this means that the last gate is a NOR gate and if X = 0, this indicates that the last gate is an OR gate. In addition to the introduction of a new variable \, the inequality set for the last gate differs from the set k. 5-2.1 in that there must be one descriptive set for f (j?) = 1 and another for f(x*) = 0. In other words, no inequality includes the term UP, . K These inequalities are: For f(x) = 1 i, = 1 1 = 1 (5) Z w R x (J) + Z |3. D (J) < + U(l - M lR — (for j = 1, 2, ..., 8) ■0 -o J iR \, = 1 i = 1 This set of inequalities (^,5) can be restated as: EXTERNAL INTERNAL - \) > Z (INPUTS TO) + Z (INPUTS TO) > 1 - UX LAST GATE LAST GATE 17 Then if X = 1, (last gate is a NOR gate): EXTERNAL INTERNAL > S (INPUTS TO) + Z (INPUTS TO) > -9 LAST GATE LAST GATE forces the input to and thus the output is 1. If X = 0, (last gate is an OR gate): EXTERNAL INTERNAL 10 > Z (INPUTS TO) + Z (INPUTS TO) > 1 LAST GATE LAST GATE forces the input to have at least one input value of 1. For f(3f) = Q R — 1 (6) Z w R x (d) + z p. D (j) < o+ ux <, = 1 <- * i = 1 iR (7) Z, w*x^ (d) + Z p (J) >1-U(1-X) -u = 1 i = 1 (j = 1, 2, ..., 8) This set of inequalities (6,7) can be restated as: EXTERNAL INTERNAL U*. > Z (INPUTS TO) + Z (INPUTS TO) > 1 - U(l - X) LAST GATE LAST GATE Then if X = 1, (last gate is a NOR gate) EXTERNAL INTERNAL 10 > Z (INPUTS TO) + Z (INPUTS TO) > 1 LAST GATE LAST GATE 18 forces the input value to the last gate to be 1 and thus the output value = 0. And if X = 0, (last gate is an OR gate) EXTERNAL INTERNAL > Z (INPUTS TO) + Z (INPUTS TO) > -9 LAST GATE LAST GATE forces the input value to be and therefore the output value = 0. U. 5.2.3 Definition of B Throughout inequalities of type (2,3) and (^,5) we have used a variable B., for internal input to gate k from gate i. B. , is XK IK the input to the k-th gate from the i-th gate for the j-th input vector 3T . Algebraically: B., '=a., P. ^' + a.. (l-p.^M ik lk 1 -lk 1 ' This indicates that: (J) _ ik INTERNAL OR OUTPUT FROM GATE i TO GATE k FOR THE j-th INPUT IVECTOR r I INTERNAL NOR OUTPUT ! FROM GATE i TO GATE ! k FOR THE j-th INPUT l VECTOR must be introduced since all inequalities in an integer linear IK program statement must be linear and the product aP is not linear. Introducing B.. allows us to get around this problem. :urther step must be taken to restate the equality of non-linear ibove as a linear inequality set, again to fit the integer programming r-dem fonn. The following inequalities (8, 9, 10, 11) serve this purpose: 19 (8) p., (J) >c* - (1 - P. (<3) ) ik - lk i > (9) p., (J) a - P,^ lk - lk l (11) 3 ^ < a. + P. ^ ik - ik i (for j = 1, . .., 8) (for i = 1, ..., R - 1) (for k = i + 1, . .., R) Note that (l - P) is used in place of P eliminating the need for a new variable P. If a and a = 0, then p = and gates i and k are not connected. This is derived from the definition of p as defined above. 4.3.3 Additional inequalities These restrictions consist of additional information which is not needed to describe the integer linear programming problem but are introduced to narrow the solution space and thus speed up the convergence to optimal solutions. U. 5«3»1 Internal connection between two gates The first additional inequality states: (12) a., + a., < 1 (for all i < k < R) ik -ik — - In other words at most one of a., and en., can be 1. ik — ik This prevents the following network which can realize only the constant values and 1: E? 20 k. 5-3-2 Input connection condition This condition specifies first of all, that every gate must have an input connection. It also specifies that the number of input connections to a gate (except the last) plus the number of NOR output connections from gate k to gate j must be greater than or equal to two.* 3 k k-1 (13) Z w*+ Z (« ik +g ik )>l (for 22-(i-e) sa -ex 1^=1 i=l j=k+l (0=1 if k=R, elsewhere) These inequalities can be restated as: EXTERNAL INHJT INTERNAL OUTHJT Z (CONNECTIONS TO) + Z (CONNECTIONS TO ) >1 (for all k) GATE k GATE k NOR OUTHJT >2-Z (CONNECTION) (for k } R) FROM k TO ALL OTHER GATES >2-\ (for k = R) This would prevent the following type of network which effectively does nothing except introduce another gate into the network. Allowing "extra" gates would prohibit optimal solutions according to the objectives stated in section k.2 below. T r> OR output No NOR output connection used * See section ;.8 for summary of priorities / / N 21 k.5 3.3 Output connection condition (k / R) Condition (16) is analogous to condition (13)> but for outputs. It states that each gate must have at least one output. If it has only one output, other inequalities will force it to be a NOR output. Mathematically this inequality is: R (16) E (a + a ) > 1 j = k + 1 kJ K ° (for k = 1, 2, ..., R - 1) Restated in English this is: ALL OUTPUT L (CONNECTIONS) > 1 FROM GATE k k. 5. 3.^ Last gate connection condition (k = R) Extending the concept of ^••5«3-3 to the last gate provides the reasoning behind inequality (17). Inequality (17) has an ordering effect on the "last" gates in a network. It states that if the output connection between a gate (R - i) - 1 and the last gate R exists, then the output connection between gate (R - i) and the last gate R must exist. Some optimal solutions are eliminated by (17)- The eliminated solutions differ from those which will be found by some permutation of gate numbers. In this way the generality of (17) is not lost and its effect is to speed up computation time. 22 For example the following network should be allowed: £> E> But an equally optimal network would not be allowed: u 3 >:• JTN, Thus these inequalities eliminate some networks which are permutations of gate numbers of another equally optimal network. This saves on computation time by reducing the solution space. The inequality states: (17) (a (R - 1), R + *(R - i), R } " (a (R - i - 1), R + 2(R - i - i), r>> (i = 1, 2, ..., R - 2) This can be explained as: [THE OUTPUT CONNECTION FROM GATE R - i TO GATE R 1 [the output connection Ifrom GATE R - i - 1 to GATE I h. 5.3. 5 Triangular condition A Precautions must be taken to prevent the following triangular network* because the outputs of k can be obtained with only two gates. o- \ k H t £ for all i ( a ik + ^ik) + ^ itJ + ^) + ^ k < 2 (for alli J N £ d (for i = 1, ..., R - 1) j = i + 1 * J j = i + 1 The following diagram exemplifies the type of network (22) eliminates: no NOR output connections £> U. 5. 3.8 Two inputs to each gate (23) strengthens the restriction of (22) by requiring that if a gate has an OR output it must have at least two inputs. This is advantageous since a network containing a gate k with an OR output and only a single input to k could have realized the OR output with one less connection by by-passing k. (See saction k.2). This eliminates some optimal networks which can be easily found by hand. The computation time saved by inclusion of this restriction more than out-weighs the cost of finding these simple networks by hand. For example, the following network would be found by the integer programming al corn t.hrrr 26 number of connections = 5 An equally optimal network which can be obtained by hand is: a b o H O P -H^J aJ bOfn c 92 g § o L' X> number of connections = 5 This inequality states: [22) s »i*'i ("n^l -o=l k = 1 2 a. . > id - ( for i = 1, . . . , R - 1 ) (for j = i + 1, . .., R) In summary (22) and (23) characterize the priorities of inputs and outputs. The rules established are: (1) A gate must have at least one output connection to exist (2 ) If it has only one output connection, then the output must be the NOR output connection (3) If it has an OR output connection then the gate must have a NOR output connection and at least two inputs h. 5»3»9 Ordering of gate output connections Inequality set (24,25) gives the linear program a specific ordering rule as to which gates should be connected in the event none of the other inequalities finds any of the possible connections disadvantageous. Inequality (2k) tries to prevent connections between two gates in a r ir< i. sub-network which are most "distant" in terms of gate numbers. For example, the following network would be prevented from occ > 27 However, some of the networks which would be allowed are: JI> OR It should be noted that this is consistent with the concept of a feed-forward network. Inequality (2*0 states: (2U) R < Z j = i + 2 (2 2(d ri - 2) 2 . 2 2(j - i - 2) i + 1, J .) - £ (2 2 ^' - 1 - 2 )c.. + 2'2 2 ^ - 1 - 2 ) a. . "~i + l> J a. .) + u (a. . . + a. . . ) ij' i, i + 1 -i, i h- l y 10 f or i = 1, . . . , R - 2 ) (25) is a direct result of (22) which states that all but the Rth gate cannot have a solitary OR output. Hence: a =0 since QL, « 1. R - J-> R — R - ±) R (25 » ^R - 1, R 2 x 28 The effect of inequality set (24,25) can be most easily demonstrated by an example. The first network below would be chosen over the second, not because one is better than the other, but for the saving in computation time. We have thus given the inequalities an arbitrary ordering rule. The second network is easily derived by hand by permutation of gate numbers. FIRST NETWORK SECOND NETWORK 29 5. ANALYSIS OF RESULTS The following charts summarize some of the statistical relationships among the networks obtained in the catalog at the end of this paper. (See Appendices 1.2 and 1-3)- Generally speaking, the computation time increased exponentially as the number of gates increased linearly. For example, the average computation time per function for feasible solutions increased from one second for 3- gate networks to fifteen seconds for 4-gate networks and to one hundred two seconds for 5-gate networks. The computation time for infeasible solutions was less than that for feasible solutions, but it was proportional to the computation time for feasible solutions. The 6-gate networks took approximately fifteen minutes to find a feasible solution and thus indicated that the algorithm needed modification for improvement of computation time with a larger number of gates. Of the kO functions used in the computations only 35 were realized. And 3 functions have optimum networks which contain at least one gate with both NOR and OR outputs. These functions* are: (1) a c v b c octal code 033 (2) abvacvab octal code 27^ (3) abvacvabvac octal code 275 All other networks were composed of NOR gates, OR gates or both. It appeared that the N0R-0R gate proved useful in these networks since the complements of external inputs x , x , x were assumed not to See definition of octal code in Appendix 1.1. 30 be available. The N0R-0R gate was used in the above cases (l) and (2) to provide the complement of a single input as well as the input itself. In the case of multiple inputs (as in (3) above) the N0R-0R gate appeared as: It is conjectured that as the number of gates in a network increases, the advantages of the N0R-0R gate would also increase. The charts on the next two pages show in more detail how computation time was affected for each of the functions attempted by computer. They are grouped by number of gates (R = 0, 1, 2, 3> ^> 5 and 6 or more). 31 < EH vo O o on LT\ 8 OJ t- • • CO H o H & o CO \0 00 n VO O CO £1 sn CO CO OJ o ir\ 0J OJ CO CO ON o ON co ITN OJ CO H <; O En En ITN H OJ • H ON o H J- CO vo 8 >H pq itn oo t— co o Ol CO OJ t- • • • On ON o co ON H -Hr Oj" CO CO VO O CO CI CO CO VO • m i/N co H OJ Q CO CO O CO r— O CO OJ OJ OJ LTN 8n VO OJ co ON O o OJ ON o OJ OJ OJ CO CO OJ OJ K OJ CO ir\ VO fn U O O a 32 110 ioo •• 90 80 70 60 50 30 - 20 10 h 5 :ber of gates ' i vi'ion time ier function for nor-or gates 33 CONCLUSION This report has shown that the design of optimum NOR-OR logic networks can be realized computationally by using a modified version of implicit enumeration. The modified version was also used for NOR gate synthesis and NOR-AND gate synthesis and thus we have shown further flexibility in this algorithm. It can be seen that the advantages of the integer programming approach include its versatility and simplicity to handle a variety of gate types, a variety of network restrictions and also various objectives, without changing the algorithm. While this thesis is not the first attempt at using implicit enumeration, it does represent the first attempt at cataloging optimum three variable NOR-OR gate networks. Forty representative functions were used for solution of NOR-OR networks and run on an IBM 360/751 system. They represented all three variable functions in that others could be obtained by negation of the function and permutation of the variables. We were not able to realize all forty functions due to excessive computation time for five of them. Work is being done to realize the last five functions in a reasonable amount of computation time by modifying the implicit enumeration algorithm to what is termed the all-interconnection formulation. These results will be presented at a future time. 3^ [2] [3] m [5] [6] [7] [8] [9] [loj LIST OF REFERENCES Balas, E. "An additive algorithm for solving linear programs with zero-one variables," Operations Research , vol. 13, no. k, pp. 517- 5^9, July- Aug., 196 5. "" Breuer, M. A , "implementation of threshold nets by integer linear programming," IEEETEC , vol. EC-lA, no. 6, pp. 950-952, Dec, 1965. Cameron, S. H , "The generation of minimal threshold nets by an integer program," IEEETEC , vol. EC-13, no. 3, PP- 299-302, June, 196h. Davidson, E. S-, "An algorithm for NAND decomposition of combinational switching function," Ph.D. dissertation, Department of Electrical Engineering and Coordinated Science Laboratory, University of Illinois, 1968. Fleischman, B. , "Computational experience with the algorithm of Balas," Operations Research , vol. 15, no. 1, pp. 153-155, Jan.- Feb., 1967. Geoffrion, A. M-, "integer programming by implicit enumeration and Balas' method," STAM Review , vol. 9, no. 2, pp. I78-I9O, April, 1967. Glover, F-, "A multiphase -dual algorithm for the zero-one integer programming problem," Operations Research , vol. 13, no. 6, pp. 879- 919, Nov. -Dec, 1965- Hellerman, L. , "A catalog of three -variable OR-invert and AND- invert logical circuits," IEEETEC , vol. EC-12, no. 3, PP- 198-223, June, 1963- Ibaraki, T», T- K. Liu, C R. Baugh and S. Muroga, "implicit enumeration program for zero-one integer programming," Report no. 05, Department of Computer Science, University of Illinois, auary, 1 *'• • Ibaraki, T., T K. Liu, C. R Baugh, and S. Muroga, "Optimal network design using NOR and NOR-AND gates by integer programming, " Report no. 293* Department of Computer Science, University of Illinois, ■ , Liu, T. K- , "A code for zero-one integer linear programming by implicit enumeration," Master Thesis, Department of Computer :e, University of Illinois, 1968. [12] [13] [1U] 35 Muroga, S., and T. Ibaraki, "Logical design of an optimum network "by integer linear programming- Part 1, " Report no. 26k, Department of Computer Science, University of Illinois, July, 1968. Muroga, S., and T. Ibaraki, "Logical design of an optimum network "by integer linear programming-Part 2, " Report no. 289, Department of Computer Science, University of Illinois, Dec, 1968. Taniguchi, K. , N. Tokura, T. Kasami and H. Ozaki, "Logical functions realizable by a planar NAND network, " The Trans of Electronics and Communication Engineers of Japan , vol. 51-C, no. 2, pp. 59-65, Feb. , 196o\ 36 Appendix 1.1 Tabulation of Optimum NOR-OR Networks Here listed are all the optimum networks for each function of three variables, using NOR-OR gates. The networks which have the minimum number of interconnections and connections among the networks with the minimum number of gates are chosen as optimal networks. The procedure for obtaining the optimum network diagram for a given function follows that of Hellerman's . A function can be represented by a truth table as shown below, by specifying the values of f , f , ..., f o where f , . . • , f o show the values of the given f for input vectors in the same rows, a, b and c denote the variables of f. a b c f l f 2 1 f 3 1 f U 1 1 f 5 1 f 6 1 1 f 7 1 1 f 8 1 1 1 Let us write eight binary numbers f , . . . , fn as follows: A\ f 5*» h r <>, 37 Grouping the f. 's as shown, we obtain the octal number CL n . This octal number is used throughout the Appendix to identify a function. In Tables 1.1.2 and 1.1-3 only representatives of equivalence class obtained by permutation of variables and negation of the function are listed, reducing the 256 functions into forty representatives. This is done for conciseness. However, every three -variable function can be derived from the networks in Table 1.1. 3 (except those not solved) by use of Table 1.1.1. Table 1.1.1 lists all three -variable functions 000-377 and explains what modifications are needed to a given network (shown in Table 1.1. 3) in order to realize a desired function. An example may provide better insight into this procedure: Assume that we are trying to find the optimum N0R-0R network which will realize the three -variable function a b c v a b c The network may be obtained by the following steps: Step (l) Convert a b c v a b c into its octal representation. For this function we have Okk which is demonstrated below. a b c f (a, b, c) 1 k 10 1 11 10 h 10 1 1 110 111 38 Step (2) Look in Table 1.1.1 for Okk as a function code. The table explains that Okh can be realized by modifying either network 31 or 32 of Table 1.1-3 with modifications 7 and 2. The modifications are explained below. Step (3) Find network 31 (32 could also have been chosen) in Table 1,1.3* It appears as: a ' c Step (4) Apply modification 7 which indicates that the output gate should be changed from its present gate type (OR or NOR) to the opposite gate type, or if the network has no gates then the output should be negated. In this case the output gate is a NOR gate. Hence, modification 7 changes it to an OR gate. Step (5) Apply modification 2 to the network resulting from Step k. Modification 2 changes a 3-tuple (a, b, c) to (c, a, b). The resulting network, then is: This network realizes 0^+U orabcvabc There are seven modification codes used in Table 1.1.1. They may be looked upon as operators and will be denoted by M , NL, M , M. , M , NL, ML- The notation M. (3f) will be used to denote an operation of operator i on X. :'J_ly the M, 's can be defined as: 39 M l «2 % a, b, c) >(a, b, c) a, b, c) >*(c, a, b) a, b, c)- a, b, c ) M^, c, a) ->(a, c, b) a, b, c) *"(c, b, a) a, b, c) ^"(b, a, c) M_ is used to change the output gate of a network from its present state to the opposite state (as from NOR to OR). In the case of a network with no gates the effect is to have the output negated. Some additional properties of the operators are shown below: 1 ) M ± 'V 2 ) ^ i V 3: I M 3 ( K, ( k ) % A < 5 ) M 5 :m 5 ( 6 ) M g •m 6 ( 7 ) M 3 ( V 8, 1 Mg 1 M 5 ( 9, ) H, 1 \ ( io : 1 H U M ? ( ii ; , M3I :m 5 ( 12: I ^ ( M 5 ( (a, b, c) (a, b, c) (a, b, c) (a, b, c) (a, b, c) (a, b, c) (a, b, c) (a, b, c) (a, b, c) (a, b, c) (a, b, c) (a, b, c) :"i - M. :«l - a. :"3 :\ : M 6 (a, b, c) - (a, b, c) (a, b, c) (a, b, c) (a, b, c) (a, b, c) (a, b, c) (a, b, c) (a, b, c) (a, b, c) (a, b, c) (a, b, c) (a, b, c) ko Proof of these 12 properties are omitted since they are easily- obtained from the definition of operators M. in A) - G) above. Table 1.1.3 shows all the optimum networks obtained for each function without imposing fan-in restrictions. Tables 1.1.2 and 1.1. 3 do not list the negation of each function. The negations can be obtained by changing the output gate of a function listed in Tables 1.1.2 and 1.1.3 from its present state to the opposite state. That is from OR to NOR or from NOR to OR. Note that if a given function is symmetric in some variables say a and b, then among all the optimum networks obtainable by permuting these symetric variables, a and b, only one network is listed in Table 1.1.2 and Table 1.1.3- The rest of the networks can be obtained by simply exchanging the connection from the external variables according to the permutation of variables. Table 1.1.1* . Ul FUNCTION CODE BASIC NETWORK NUMBER MODIFICATION CODE OOO 001 002 003 OOU 005 006 007 010 Oil 012 013 oiU 015 016 017 020 021 022 023 02 k 025 026 027 030 031 032 033 03U 035 036 037 0U0 0U1 01+2 0U3 okk 0U5 okG 0k7 050 051 052 053 ID 1 2 3D 2 3D 10 k 5 11 1+D 7 kD 7 3 2D 2 3D 10 k 10 k 33 8 31 & 32 28 & 29 & 30 12 13 & Ik 12 13 & Ik 15 6 5 11 UD 7 31 & 32 28 & 29 & 30 12 13 & 1U 27 not solved 16 23 & 2k & 25 -1 1 1 -1 2 -2 1 1 1 1 -1 1 -1+ k 1 7, -3 3 -3 3 3 2 2 7, 1 1 7, 3 7, 3 1 1 k k 1 7, 3 3 3 ■6 6 7, 2 7, 2 6 6 7, 2 1 7, 2 Negative signs used to denote degenerate functions. k2 FUNCTION BASIC MODIFICATION CODE NETWORK CODE NUMBER 05U 26 7, 5 055 35 7, 5 056 17 1 057 18 1 060 Ud -3 061 7 3 062 3 3 063 2D 7, -2 06U 12 3 065 13 & lU 3 066 15 3 067 6 7, 2 070 26 7, 2 071 35 1, 2 072 17 6 073 18 6 07*+ 6d -1 075 3^ 1, 2 076 19 1 077 5D -1 100 5 2 101 11 2 102 31 & 32 7, 1 103 28 & 29 & 30 1, 1 10U Ud -2 105 7 2 106 12 2 107 13 & lU 2 110 27 7, 3 111 not solved 122 26 7, 3 113 35 7, 3 llU 16 2 115 23 & 2l+ & 25 7, 3 116 17 U 117 18 - k 120 UD -5 121 7 5 122 12 5 123 13 & 1*» 5 12U 3 2 125 2D 7, -1 126 15 2 127 7, 1 26 7, 6 131 35 7, 6 132 6d -2 133 7, 3 2 18 2 19 ? FUNCTION BASIC CODE NETWORK NUMBER U3 MODIFICATION CODE -2 7, 1 7, 1* 7, U 7, l 1> l -3 7, 1 137 5D iko 27 lUl not solved 1U2 26 1^3 35 lWt 26 1^5 35 1U6 6d 1U7 3^ 150 not solved 151 not solved 152 not solved 153 not solved 15^ not solved 155 not solved 156 22 157 21 160 16 161 23 & 2k & 25 162 17 163 18 l6k 17 165 18 166 19 167 5D 170 not solved 171 not solved 172 22 173 21 Ilk 22 175 21 176 20 177 9 200 9 201 20 202 21 203 22 20U 21 205 22 206 not solved 207 not solved 210 5D 211 19 212 18 213 17 2lU 18 215 17 216 23 & 2k & 25 217 16 7, 3 7, 3 3 7, 1 3 3 5 5 3 •3 1, 2 1, 2 1, 1 7, 1 1, 1 1 7, 1 1 1 1 2. 2 7, -3 7, 3 7, 5 7, 5 7, 3 7, 3 1 7, 3 hk FUNCTION BASIC MODIFICATION CODE NETWORK CODE NUMBER 220 21 3 221 22 3 222 not solved 223 no "t solved 22^ not solved 225 not solved 226 not solved 227 not solved 230 3h 231 6d 232 35 233 26 23^ 35 235 26 236 not solved 237 27 2U0 5D 2kl 19 21+2 18 2U3 17 2kk 3h 2U5 6d 2k6 35 2U7 26 250 6 251 15 252 2D 253 3 25^ 13 & lh 255 12 256 7 257 *+D 260 18 261 17 262 23 & 2k & 25 263 16 2614 35 265 26 266 not solved 27 270 13 & l 1 * 12 7 UD 28 & 29 % 30 31 & 32 11 5 1 7, -3 1 1 k k 1 7, -2 1, 2 7, 2 7, 2 3 7, -2 6 6 1 7, 2 ■1 7, 2 7, 5 7, 5 7, 5 7, -5 7, U 1, 1+ 3 7, 2 3 3 3 7, 2 7, 2 7, 2 7, -2 1 1 7, 2 7, 2 U5 FUNCTION BASIC CODE NETWORK NUMBER MODIFICATION CODE 7, -1 7, 1 2 7, -1 7, 6 7, 6 2 2 2 7, 3 7, 3 7, 3 -2 7, 3 7, 3 7, -3 7, 1 7, 1 5 5 2 7, 1 2 7, 6 7, 6 2 2 7, 6 7, -6 7, 3 7, 3 3 7, 1 7, h 7, k - 7, 1 7, 1 3 3 7, l 1 7, 2 7, 2 7, 3 7, 3 7, -3 7, 3 300 5D 301 19 302 3h 303 6d 30U 18 305 17 306 35 307 26 310 6 311 15 312 13 & lU 313 12 3lU 2D 315 3 316 7 317 hD 320 18 321 17 322 35 323 26 32U 23 & 2h & 25 325 16 326 not solved 327 27 330 13 & lh 331 12 332 28 & 29 & 30 333 31 & 32 33^ 7 335 UD 336 11 337 5 3^0 6 3^1 15 3^2 13 & lU 3^3 12 3M+ 13 & lU 3^5 12 3^ 28 & 29 & 30 3^7 31 & 32 350 8 351 33 352 k 353 10 35^ h 355 10 356 3D 357 2 U6 FUNCTION BASIC MODIFICATION CODE NETWORK CODE NUMBER 360 2D 361 3 362 7 363 *+D 36U 7 365 ^D 366 11 367 5 370 k 371 10 372 3D 373 2 37^ 3D 375 2 376 1 377 ID -3 7, 1 7, k 7, -k 7, 1 7, -1 7, 1 7, 1 7, 1 7, 1 7, -2 1, 2 1, -1 1, 1 1, 1 7, -1 Appendix 1.2 Catalog of UP representative functions hi Table 1.2.1 FUNC- NEGA- NEGA- NET- NUMBER NUM- NUM- TION TION TION FUNCTIONAL WORK OF BER BER CODE OF EQUIV. NUM- GATES OF OF (OC- FUNC- CLASS EXPRESSION BER CON- LEV- TAL) TION TOT NOR OR NOR- OR NEC- TIONS ELS 000 377 377 _0_ ID 003 37^ 356 a b 3D 1 1 2 1 012 365 257 a c 4D 2 2 3 2 07U 303 231 a b v a b 6D 1+ 3 1 8 3 077 300 210 a v b 5D 3 2 1 k 2 252 125 017 a 2D 1 1 NON -DEGENERATE . •• 001 376 376 a b c 1 1 1 3 1 002 375 357 a b c 2 2 2 k 2 006 371 353 a b c v a b c 10 h 3 1 10 3 007 370 352 a b v a c k 3 2 1 6 2 010 367 277 a b c 5 3 3 5 2 Oil 366 276 a b c v a b c 11 k k 9 3 013 36h 256 a b v a c 7 3 3 5 3 016 361 350 253 350 a b v a c 3 8 2 1+ 2 3 1 k 9 2 027 a b v a c v b c 2 032 3^5 255 a c v a b c 12 k 3 1 9 3 033 3kk 25^ a c v b c 13 k 3 1 7 3 Ik k 3 2 1 7 3 036 3^1 251 a b v a c v a b c 15 k 3 1 10 3 052 325 217 a c v b c 16 h 3 1 7 3 056 321 213 a b v b c 17 k 3 1 8 3 057 320 212 a v b c 18 k 3 1 6 3 O76 301 211 a b v a b v a c 19 h 3 1 9 3 177 200 200 a v b v c 9 k 3 1 6 2 201 176 176 a b c v a b c 20 5 5 12 3 202 175 157 a b c v a b c 21 5 5 10 3 203 lfk 156 a b c v a b 22 5 5 11 3 216 161 053 a b v a c v b c 23 5 5 10 3 21+ 5 5 ' 10 k 25 5 5 10 k 230 IU7 075 a b c v b c 3h 5 5 10 k 232 li+5 055 a c v b c v a b c 35 5 5 11 k 233 ikk 05^ a b v b c v b c 26 5 5 10 3 237 1^0 050 b c v a v b c 27 5 5 n 3 250 127 037 a c v b c 6 3 3 5 2 27k 103 031 a b v a c v a b 28 5 5 9 3 29 5 5 1 1 9 3 30 5 5 2 2 9 3 275 102 030 ab V ac v ab v a c 31 5 5 11 3 32 5 5 1 1 11 1+ 351 026 026 ab V ac v be v a b c 33 5 5 15 3 U8 Appendix 1. 3 Catalog of optimal networks 1+9 ffi IS rs * O u O A A U 50 ts z z z o >- o z 3 ° L T J A 51 X) A i' IO C\ A > JnL o Jrl_ z u o k i > r^^~i o A A A A > / \ / \ IU /\ / \ K ii i ' 1.0 f \ 1 \ o LO L 1 1 o z o T it- A A * c ° V o r-Jr ■* h- '"y ro A (VJ u - C\J CD O o V o a u z rO ro 1 u IJ3 ♦ I 1 O jO IO 4 > A > A J3 A z u o JnL > LrrL o i — i ■ — i /A /A /A z o f \ ii z> LJ LJ O u. " o I 1 1 o 1 ro ro J 3 •A- ° S£ o o o> ro z (M ro IU IO A ♦ > IO I -Q > /> IO z o u o JnL > K > H S O o A A > z |J3 f\ f\ Li_ O \i JnL o y ff/X\ o ° -° i i /i V LJ LJ IT> A f-~ U-pJ L-r-J r^ A J> CJ A o c\j ft o CO pj z (\J ro 1 u IO t A LO 1 o I IU A > .O A o W z IO IO > (J H > r^^ o > H H <-> A A o z u o > (V?) > IO ft, f 3 b. O jk^ A o if hi 1 A Oi A, ro in PI I .. A- <\J H (\J n O U A pj o f- A u m T o z (VI rt ro Appendix l.h Glossary of symbols used 1.4.1 Definition of symbols 52 Symbol (l) Internal connections a ij a. -ij 3, U) (j) ik Meaning Internal connection from the i-th gate to the j-th gate. This indicates the presence of a connection from the OR output of gate i to gate j (0 or l) if value = 1 or absence if value = 0. Internal connection from the i-th gate to the j-th gate. This indicates the presence of a connection from the NOR of gate i (0 or 1) if value = 1, value = 0. to gate j or absence if The OR output value of the i-th gate for the j-th input vector T^ for an OR gate. Input to the k-th gate from the i-th gate for the j-th input vector (3f) That is: a \0) _ « pU ) + a pU) ik ik i ik i '2) External connections k v I .(j) w k x (j) I k Other syrr,bols \ The -t-th external connection to the k-th gate. This indicates the presence of a connection of value = 1 or absence if value = 0. The value of the variable x to the k-th gate, for the j-th input vector. Input to the k-th gate from an external source. Used to determine what type of gate the last gate (output gate) is since the last gate cannot have two outputs. ^ indicates that the last gate is U) OR gate. X 1 indicates a NOR gate. R n k, i U F (x) 53 Number of gates in the network. Number of variables. Used for gate numbers: 1 < k < R 1 < i < R (k, i integers) Sufficiently large positive number. Output value of a network with input vector x\ a, b, c Used in optimum network diagrams in the same sense as: «3> 1 2 3 x , x , x or p k k k lk NOR gate f = a b *" b-=L^ b — 1 OR gate NOR -OR gate f = a v b v I- a b f = a v b v •]