LIBRARY OF THE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN 510.84 I£6r no. 480-489 cop. ft* Digitized by the Internet Archive in 2013 http://archive.org/details/degreesofunsolva482cudi Report No. U80 d,3- ON THE SYNTHESIS BY INTEGER PROGRAMMING OF OPTIMAL NOR GATE NETWORKS FOR FOUR VARIABLE SWITCHING FUNCTIONS , ; by Jay Niel Culliney I September 1971 IHE LIBRARY OF THE SEP 3 1971 .UNIVERSITY OF ILLINOIS NA-CHAMF"AIG N Report No. U80 d.3- ON THE SYNTHESIS BY INTEGER PROGRAMMING OF OPTIMAL NOR GATE NETWORKS FOR FOUR VARIABLE SWITCHING FUNCTIONS by Jay Niel Culliney ^ September 1971 IHE LIBRARY OF THE SEP 3 1971 .UNIVERSITY OF ILUNOIS &£ WRBANA-CHAMI^AIGN DEPARTMENT OF COMPUTER SCIENCE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN URBANA, ILLINOIS Report No. 480 ON THE SYNTHESIS BY INTEGER PROGRAMMING OF OPTIMAL NOR GATE NETWORKS FOR FOUR VARIABLE SWITCHING FUNCTIONS* by Jay Niel Culliney September 1971 Department of Computer Science University of Illinois Urbana, Illinois 6l801 This work was submitted in partial fulfillment of the requirements for the degree of Master of Science in Computer Science in the Graduate College of the University of Illinois, September 1971 and supported in part by the National Science Foundation under Grant No. NSF GJ-503. ACKNOWLEDGMENT The author would like to express his deep gratitude to his advisor, Professor Saburo Muroga, for his enthusiastic guidance and encouragement during the preparation of this thesis, and also for his careful reading and valuable suggestions for the improvement of the original manuscript. This work was supported in part by the National Science Foundation under Grant No. NSF GJ-503. This paper is dedicated to two friends, Janet Lynn and John Misha Petkevich. 111 IV TABLE OF CONTENTS PAGE 1. INTRODUCTION 1 2. INTEGER PROGRAMMING AND IMPLICIT ENUMERATION 2 3. ALL- INTERCONNECTION NOR SYNTHESIS 8 k. AUGMENTATION OF PARTIAL SOLUTION 20 5. RESULTS 26 6. CONCLUSION 35 APPENDICES 36 LIST OF REFERENCES "?6 1. INTRODUCTION This report represents an effort to apply the implicit enumeration algorithm developed in [2, lU, 15] to the problem of synthesizing optimal networks for four variable switching functions. In particular, NOR gates were used in the synthesis of these networks; complements of variables were assumed to be unavailable. To avoid superfluous efforts, the 65,536 functions of four variables were divided into 3>98^+ P (permutation of variables) equivalence classes. From among the representative functions of these classes, were selected ^38 functions for which optimal networks were synthesized. These selected functions required from 3 to 8 NOR gates in their network realizations (networks, and the corresponding functions, of 2 or fewer NOR gates are easily exhausted by hand ) . Although networks with the minimal numbers of gates were already known [12] for ^-36 of these functions , this report is believed to be the first list- ing of networks for these functions where the sum of the number of connections of external variables to gates plus the number of interconnections among gates is also known to be minimal. See Appendix D. 2. INTEGER PROGRAMMING AND IMPLICIT ENUMERATION The problem of finding an optimal network to realize a given function is conveniently posed as an integer programming problem. This approach proves to be very flexible, accommodating a wide spectrum of optimality criteria. The general integer programming problem with N unknown variables and m constraints may be stated: minimize i C X subject to b + A x > where c = [c, , • • • , Cjj], b = [b r ..., bj; and A ■ [a idU ], c. > i =. 1, . .., N; are coefficient matrices and x = [x 1 , . . . , x ] is an N-dimensional vector of variables. In this work, all coefficients and variables are integral; and the variables, x.'s, assume only the values 1 or 0. The objective function, c x, represents the "cost" of a proposed solution x. In minimizing c x, we are finding the x which yields the lowest "cost". One way to do this is to generate every possible x (there are 2 such vectors since x. =0, l), test each to see if it satisfies the constraints b + A x > 0, discard those that fail, and select the x's (or x, if there is only one) with the lowest cost out of those remaining. These x's must then be optimal solu- tions to the integer programming problem by virtue of the fact that all potential solutions would have been explicitly enumerated and examined. This algorithm is theoretically possible, but, for large values of N, it becomes impossible in practice. For example, for two problems in this work, 1112 variables are employed. To examine 2 possible x's individually, say at the rate of one billion x's per second, would require about 2 years (plus or minus a couple orders of magnitude). Luckily, a vastly more efficient algorithm is available for solving this type of zero-one problem: the implicit enumeration method. As its name suggests, it enumerates implicitly all of the 2 solutions and selects the best feasible solution(s). To illustrate how constraints may be written as inequalities, consider a person making payments on his monthly bills. (For the sake of this example, only allow the x. to assume integral values other than or 1. ) One of the constraints this person must work under is: - Z (PAYMENT ON BILL i) + Z (LOAN FROM COMPANY k) + MONTHLY INCOME > 0. i k In this case, the monthly income is an element of b, the coefficients of the corresponding row of A are - l's and + l's (and 0's for columns correspond- ing to any variables not appearing in this constraint), and the payments on various bills and loans from various companies are elements of x. To understand the implicit enumeration scheme, several definitions are necessary: * For details of the implicit enumeration algorithm, see [2], [8], and [11]. The mathematical theory behind this algorithm is outlined in [l], [7], [8], and [9]. k A solution is an assignment of the values or 1 to all the variables of x. A solution which satisfies b + A x > is said to be feasible ; a solution which does not, is said to be infeasible . A feasible solution which minimizes c x is called an optimal feasible solution . A partial solution , S,is defined as an ordered assignment of binary- values to a proper subset of the N variables of x. A variable that has not been assigned a value is called a free variable ; a variable that has been assigned is called a fixed variable . A completion of a partial solution S is a solution consisting of S followed by a binary assignment to all free variables of S. Since the implicit enumeration algorithm is discussed in depth else- [13] where and since many of the details are unnecessary for the purpose of understanding this report, the algorithm will only be outlined as shown in the simplified flowchart of Fig. 2.1. (However, the part of the algorithm which chooses variables to augment the partial solutions, being tailored specifically for this NOR network problem, will be discussed in more detail in Section k. ) Starting with a given partial solution S (which may be an assignment to no variables at all) and an incumbent solution (the feasible solution having the smallest value of the objective function obtained so far), the main block, labeled "CHK-IEQ" (for "check inequalities"), is entered. In a typical application of the implicit enumeration algorithm to the problem of finding an optimal network for a function, the incumbent might represent the Fig. 2.1 Implicit enumeration algorithm ITERATION COUNTER REPLACE INCUMBENT BY THIS IMPROVED SOLUTION. best network found by using a heuristic method. Or, if no solution is known at all, the incumbent might just be a "dummy" with a sufficiently high objective function value to guarantee that there is some real solution(s) (with a lower value of the objective function) which will displace it. (if one's purpose is to show the infeasibility of the integer programming problem, the objective function value of the initial "dummy" incumbent must be set higher than the objective function values of all potential solutions.) Upon entering "CHK-IEQ", we examine inequalities and may find that certain free variables must be set (i.e., forced) to or 1 in order that all of the inequalities can be satisfied. The inequalities are scanned repeatedly until no more free variables may be assigned. The original partial solution, S , augmented by the free variables thus assigned, becomes a new partial solution, S . This new partial solution, S , is then checked to determine which of the following three cases has occurred: (1) A feasible solution has been found . The completion of S obtained by setting all free variables to is a feasible solution. Compare it with the incumbent solution and retain the better (i.e., the one with the lower objective function value) as the incumbent. Initiate the backtrack proce- 2 dure to obtain a new partial solution, S (see Appendix A for a brief expla- nation of the backtrack procedure). (2) All completions of the partial solution are infeasible. If at least one inequality is not satisfied by S , whatever binary values are assigned to the free variables, then discard S immediately by initiating p the backtrack procedure to obtain a new partial solution, S . (3) Augment the partial solution . If neither case (l) nor (2) occurs, 2 assign a free variable to the value 1, forming S . The choice of this variable is extremely important to the convergence rate of the algorithm and should take into consideration the type of problem being solved. 2 After obtaining S , reenter the block "CHK-IEQ," and repeat the process. Cycling through this process until the algorithm terminates (this will occur when we try to backtrack and find all fixed variables underlined) will result in the implicit enumeration of all possible solutions. Also, the optimum solution will be the incumbent at the termination of the algorithm. Without knowing more details of the algorithm, it might appear difficult (i.e., time-consuming) to choose among the above cases during each cycle. In fact, this can be done rather quickly as explained in [11]. The algorithm will, of course, converge in a finite number of steps, but its efficiency will depend heavily on the nature of the individual problem being solved. Computational experience shows the tailoring of the "AGMT-VAR" block in Fig. 2.1 (the subroutine which augments the partial solution when case (3) occurs) to a particular problem increases the rate of convergence. 3. ALL- INTERCONNECTION NOR SYNTHESIS r -| o i At least one earlier paper presented optimal combinational networks of gates, based on the integer programming approach discussed in [1^], [15]. This synthesis was based upon the feed- forward approach. In this approach the NOR gates were prearranged according to levels such that each gate could only receive inputs from the external variables x , x , . . . , x or from the outputs of gates of the preceding levels (this was done by simply not provid- ing variables to represent any other possible interconnections among the gates). This restriction forces every solution to be of the desired "feed- forward" type. Later papers ' employ a somewhat different formulation to obtain the same "feed- forward" type networks. This new formulation, the all- inter - connection approach, allows interconnections between every distinct pair of gates (i.e., variables are provided to represent every possible interconnection) Then inequalities are added to prevent loops from occurring in the generated networks. This new formulation, although apparently slower (because more variables and inequalities are involved), actually speeds up the network synthesis considerably. This paper, using the faster all- interconnect ion approach, presents computational results in the synthesis of single output, multilevel, loop- free networks of NOR gates which realize given ^-variable switching functions. In determining the optimal networks presented in this paper, certain assumptions were made: complements of external variables were not available, infinite fan- in and fan-out were allowed, and the number of levels of logic was unrestricted. However, any of these constraints could have been easily applied by simple modifications of the program used to obtain the optimal networks . 3.1 Introduction of Notation In order to explain how the optimization problem can be characterized by a corresponding integer programming problem, certain notations must be introduced. Assume that we are trying to characterize a network of R gates and n external variables (x_ , .... x ) to realize a function, f, of n (or In ' ' in degenerative cases, fewer) variables. First we need variables to represent all possible connections (of exter- nal variables to gates) and interconnections (of gates to other gates): w., is the connection from the i-th external variable, x. , to the k-th gate lk 1' w., =1 will mean that the connection exists lk w., =0 will mean that the connection does not exist lk a. is the interconnection from gate i to gate k lJ£ a. n =1 will mean that the interconnection exists lk a.. =0 will mean that the interconnection does not exist lk In addition to these variables, others must be introduced to allow the representation of the gate outputs for all 2 possible external input vectors . (The input vectors, (x , x , x , x, ), (using n = h as an example) are assumed to be ordered as follows: (0, 0, 0, 0) is the 1-st, (0, 0, 0, l) is the 2-nd, (0, 0, 1, 0) is the 3-rd, ..., (l, 1, 1, l) is the 2-th.) P. is the output of gate i corresponding to the j-th input vector. But in order to determine the output of each gate in a network, we must know the inputs to that gate. Inputs to a gate are classified as two types: 10 external inputs , which are from external variables, and internal inputs , which are from outputs of other gates in the network. So an input to a gate is dependent on two things: whether or not a connection (interconnection) exists from a certain external variable (gate) and, if it does, the state (1 or 0) of that variable (gate output): w x is the input to gate k from the i-th external variable ik i for the j-th input vector 8 = a P. is the input to gate k from the i-th gate for the ik ik i j-th input vector. To simplify later discussions, let an input connection to a gate be defined as either an external variable connection or a gate interconnection which supplies an input to that gate. 3.2 Problem Formulation In the last section, it was mentioned that we are explaining the problem formulation for R gates, i.e., the number of gates is fixed for a given formu- lation. This might raise the question of how the number of gates is minimized in the network for a given function, since we seemingly must know the optimal number of gates in advance in order to choose the correct formulation with which to run the program (to further optimize the network by minimizing the number of input connections). The answer is simple, of course. First try to solve the problem with the R = 1 formulation. If it is infeasible, repeat the attempt using the R = 2 formulation. Continue incrementing R and solving n the corresponding formulations until a feasible solution occurs for a certain value of R; this value must then represent the minimum number of gates nec- essary to realize the given function. Of course, if a lower bound, r, is known on the number of gates needed to realize a given function, we can skip all attempts to realize the function with fewer than r gates (i.e., start with R = r rather than R = l). In fact, this is what has been done for the functions whose networks were optimized in this paper. Based on previous research of N. Ikeno, A. Hashimoto, and [12] K. Naito , the optimal number of gates for almost every function was known in advance; and, therefore, each function could be run with the correct for- mulation on the first attempt (thereby saving some computation time). The following sections will explain explicitly the objective function and inequalities comprising the integer programming problem. It is again pointed out that this formulation is for a network of R gates and n external variables under the assumptions stated above in the introduction to Section 3« 3.3 Objective Function Recall that we want to minimize the number of input connections used to realize a given function, f, for a fixed number of gates, R. So the objective function to be minimized is simply, Z CONNECTIONS + Z INTERCONNECTIONS, or R Z k=l n R Z W ik + L °7k i=l lk &=1 m 4k " (1) 12 3*1+ Inequalities Describing Gates This section includes both the basic inequalities needed to describe the gates and supplementary inequalities to speed the computation or to restrict the network. 3»^-.l Regular Inequalities These inequalities describe the function of a NOR gate for each gate in the network. They are just a mathematical expression of the fact that the output of a NOR gate must be a 1 if all its inputs are 0, or the output must be a if at least one of its inputs is a. 1. These inequalities are written in two sets: the first set is for non- output gates whose outputs change dynamically during the computation, the second set is for the output gate of the network (designated gate number l) whose output is fixed during the computation. For all gates in the network except the output gate (k = 2, ..., R) : E w. n xH^ + Z Q\P > 1-U Pp) (2) 1=1 lk X i=l ik " k $k n "R .^ik x i d) +^ L e£ ) 1 4k if f(x (d) ) = (h) n Z i=l ik X i Z ^ < .0=1 ^ 4k if ffx^ = 1 1, ..., 2 n (5) The value U in the above inequalities (2) and (3) is a sufficiently large positive number such that (2) becomes non- restrictive when P =1 and (3) becomes non-restrictive when P n =0 (i.e., U > R + n - l). k — Notice that each of the above gate description inequalities represents 2 inequalities - one for every possible input vector. So that the inequalities (2) - (5) could be linear (note that the w. x. u terms are linear since x is known for every j), the "beta" terms were defined V.y = a., P:^ , where p:?' ik ik 1 ' ik earlier, P.}; = 2 i=l lk i=l ik 4k k = 2, (8) 3.4.2.2 Output Conditions Each NOR gate (except the output gate) must have at least one output to another gate in the network. This obvious requirement is expressed as: 1 < L a k=l 4k ik i = 2, ..., R (9) 3.4.2.3 Triangular Conditions The following triangular subnetworks cannot appear in an optimal circuit and may therefore be prohibited by inequalities. In both cases gate j is assumed to have only one output connection. 16 X. The redundant Input connections are marked by a short bar. That these are in fact redundant can be easily seen by considering separately the case when the output of gate i (or input x. ) is 1 and the case when it is 0. Observe that when a gate output in a network of NOR gates is 0, the gate is effectively disconnected from the network. The inequalities used to prohibit these configurations are respectively: R a. . + a., + a., < 2 + z a. . ij lk jk - ^ 3 i 4a i = 1, ..., R j =1, ..., R k = 1, ..., R i |= j, i j= k, j ): k; (10) 17 R ij lk jk - , n oi i = 1, . . . , n (11) Ska i - i, . • . , r k = 1, ..., R d 1= k. 3. ^-.2. 4 Generalized Triangular Conditions Somewhat similar to the preceding redundant triangular subnetworks are configurations in which a gate output connects both to the output gate and to some other gate in the network. By again considering the cases when this gate output is or 1, it is easily seen that every connection of this gate output to a non-output gate is redundant. Therefore, these configurations cannot occur in an optimal network. The appropriate restrictive inequalities are: R Z k=2 U a., + Z a., < U i = 2, .... R (12) ll , „ lk — where U has the value chosen earlier. 3.^4-.3 Fan-In Fan-Out Restrictions Although fan- in, fan-out restrictions were not applied in obtaining the optimal networks found here, the program used has the option of generating the inequalities to impose these restrictions. The form of these inequalities, for the case when 3 is the maximum fan- in, fan-out, is: 18 R n (fan- in) 3 > £ ct . + 2 w.. " k=l * x j=l J1 4i i = 1, . . . , R (13) ( fan- out ) R 3 > 2 a k=l lk 4k i = 2,. . . , R. a*o 3.k.k Loop-Free Conditions This last set of inequalities is a necessary part of the all- inter- connection formulation. These inequalities insure that any networks obtained are of the feedforward type, i.e., no "feedback" loops will occur. In this group of inequalities, there is one inequality for each possible "loop" of gates. For example, to prevent the subnetwork we would use the inequality O' + a T . n + a„. < 2. Inequalities must be Aid BO LA — provided for loops consisting of from 2 to R - 1 gates. The output gate is 19 not included in any of these loops since, before the computation begins, all of the variables representing output connections from this gate to others in the network will be placed in the initial partial solution, set to 0, and underlined. The number of these inequalities grows very rapidly compared to the other types as the number of gates increases. The set of these inequalities may be expressed, somewhat awkwardly, as: ex. . + a. . < 1 i = 2, .. ., R j = 2, . . . , R i > j a. . + a.. + a, . < 2 ij jk Tci - i — 2, • • • , R j — 2, . . . , R k = 2, ..., R i > j, k j^k • • « (15) a. . + a. . + V2 V3 + a. . < R-2 Vl 1 ! ~ i_= 2, . . . , R; i_ -2, 5 1 p_q ~~ f • ' ' ) "■> ± 1 > i 2 , i 3 , ..., i R _ 2 ; all i ' s distinct, k . , R; The total number of the loop-preventing inequalities is: R-l E 1=2 ;R-l) (R-2) ... (R-i) i 20 k. AUGMENTATION OF PARTIAL SOLUTION As shown in the simplified flow chart of the implicit enumeration algorithm, there are cases (in the CHK-IEQ block) when it is unknown whether or not there exist completions of the current partial solution with costs less than or equal to the cost of the incumbent. Having fixed, in an earlier part of CHK-IEQ, all of the free variables forced to certain values by the inequalities, the only direction in which to proceed is to choose some free x. J and set it to or 1. Hopefully, this will cause enough variables to be set by the inequalities on the next iteration (each iteration corresponds to a pass through the "Iteration Counter" block in Fig. 2.1) to enable a deter- mination of whether or not a better feasible solution than the incumbent exists as a completion of the current partial solution. If still more infor- mation is required, another variable is selected to be set to or 1, and so forth. The choice of the variables to be set in these cases is very important; consistently good choices improve computation time considerably. This choice takes place in the AGMT-VAR block of Fig. 2.1, which is detailed in Fig. k.l. ENTER AGMT-VAR DETERMINE OUT- PUT TYPES, GATE TYPES, AND NET- WORK TYPE. OF THE OUTPUTS P? J ' = WHICH DEFINE 1 GATE TYPE, SELECT ONE WITH SMALLEST j OF GATES WHICH DE- FINE NETWORK TYPE, SELECT GATE i WITH LOWEST NUMBER. DETERMINE AND SET FREE VARIABLE PRO- VIDING MOST DESIR- ABLE COVER OF p: 3, (j) RETURN TO CHK-IEQ Fig. k.l AGMT-VAR detailed 21 k.l Covers Consider the output' P of gate k for the input vector x . This variable is either 0, 1, or unassigned. If P is unassigned, it makes no demands on the assignments of other variables; and, without considering other factors, there is no justification for making an assignment one way or the other (0 or l). If P = 1, the inequalities (3) in Section 3»^«1 have already forced all of the influenced variables (w 's and g\~ 's to 0. For the third case, p}_ = 0* the inequalities (2) in Section ^.h.1. become restrictive and require at least one of the inputs to gate k to be a 1 for y~ . If this condition is satisfied for the particular p) = 0, then it is said to be covered , otherwise it is uncovered (remember that this discus- sion only applies to P ' s with the assigned value 0). Thus, a cover of K. — ^ — P ( = 0) is any source (either a gate or an external input variable) providing an input with the value 1 to gate k for x . Before proceeding further, certain definitions are necessary: An isolated gate is a gate i for which no a. . (j = 1, •••, R; j f i) is 1 in the corresponding partial solution. The classifications of possible covers of an output P). = are: COV - if there exists an i or an I such that w. n x. = 1 or fi\, = 1 lk i zk (i.e., P^ is COVered); G_ - if there exists a gate £, such that a, = 1 and P^ J ; = * ("*" will denote unassigned") (G represents the type of the possible cover, gate #); * (i) VC - if there exists an external variable i such that x. = 1 and w = * (VC represents the type of the possible cover, variable i); 22 GC - if there exists a non-isolated gate £ such that a ^ = * and (i) * T\ = 1 (GC represents the type of the possible cover, gate £) % G C - if there exists a non-isolated gate £ such that a„ = * and P\ uy = * (G C represents the type of the possible cover, gate £) ; NWG - if there exists an isolated gate £ such that a. = * and P» = * (NWG represents the type of the possible cover, NeW Gate £).. The above classifications are then ordered (in a list termed a lesirability order) according to decreasing desirability: COV, G , VC , GC , G C , and N¥G. (Roughly, the more desirable a cover is, the less "disturbance" is caused to the network when the appropriate free variables are fixed in order to cover the P, . ) k k.2 Variable Augmentation Scheme Using the above desirability order, output types, gate types, and network types may be defined. For each output P^ = of each non-isolated gate, the type of P/_ , called the output type , is defined as the most desirable type of possible cover among those possible covers of P^. . (The output type of v}, is COV if it is already covered. ) Generally, the gate type is the same as the least desirable output type of the gate. However, if the gate is isolated, the gate type is ISL (iSoLated); or if the gate is non-isolated, has no input connections, and 23 all of the outputs are or *, the gate type is LTG (LaTently useful Gate). The desirability order of the gate types is defined as: •# -* ■* -x- * ISL, GOV, LTG, G , VC , GC , G C , N¥G (from most to least desirable). Finally, the network type is defined as the least desirable gate type. A network whose type is COV realizes the given function (since all outputs are then covered). Using these definitions, the variable to be specified is determined as follows : (1) Locate the gate, k, which defines the network type. (2) Identify the P ^ which defines that gate type. (3) Determine the free variable associated with the possible cover that defines the output type of that P . K. Of course, it is possible that ties may occur in any of these three steps. If a tie occurs in step (l), the gate with the smallest number is chosen (the gates are numbered 1 to R, with the output gate being number l). If a tie occurs in step (2) and the gate type is G , GC , G C , or NWG, then select the p) (of those tied) with the smallest j; otherwise, (the type is VC ) skip step (2). The free variable assignment is made according to the variable selected in step (3), as shown in table form in Fig. k.2. Rules for breaking ties are included. In general, the selected free variable is set to 1 and included in the partial solution without being underlined; but when this free variable 2k is associated with a type NWG cover, the assignment is underlined (for the reason of preventing equivalent permuted solutions). k.3 Cost Estimation After selecting and fixing the free variable in AGMT-VAR, an estimate is prepared of the lower bound of the objective function for a completion of the current partial solution (i.e., assuming the least possible cost of completing the current partial solution, the cost of the resulting network is calculated) . If this cost exceeds the cost of the current incumbent, it is quite obvious that pursuing the extension of this partial solution would be fruitless. So, in that case, the program immediately ba.cktracks. If the estimated cost bound does not exceed the incumbent cost, the computation pro- ceeds as before; the program again enters CHK-IEQ. 25 Fie. k.2 Selection of a free variable to be fixed selected type variable action cov none All inputs are covered; the current solui a feasible solution. ;ion is G p ik Choose B.r that is * with smallest i lk such that the (i) *\ P/. (of type G ) with the smallest j is covered. * vc w ik Choose w.. that is * with smallest i lk such that the largest number of uncovered outputs is covered. -* GC p ik Choose B., that is * with smallest i lk such that the ( i) * Pl° J (of type GC ) with the smallest j is covered. G C p ik Choose B., that is * with smallest i lk such that the ( i) ■* ■*. K' )J (of type G C ) with the smallest j is covered. NWG p ik Choose B.. that is * with smallest i lk such that the P^' (of type NWG) with the smallest j is covered (gate i will be isolated). 26 5. RESULTS Let a unique l6 Lit Linary number Le defined for each U-variahle function, f, such that, going from left to right, the hits of the Linary numher represent the functional values: f (0, 0, 0, 0), f (0, 0, 0, l), f (0, 0, 1, 0), . .., f (l, 1, 1, l) . The representative functions of the 3,98U P-equi valence classes of ^-variahle functions were chosen such that the Linary number corresponding to the representative function is less than the Linary numbers corresponding to all of the other functions in the class. From these representative functions, 4-38 were selected and their respective optimal NOR-gate network realizations were ohtained. The optimal networks are listed in Appendix E along with various statistics for each network. The selected functions are listed in order of their Linary numbers which are also rewritten in hexidecimal form for easier reference. Column two of the table shows the minimal number of NOR-gates required to realize [12] each function. These numhers were previously known in all cases except for the two functions which required 8 gates. The fourth column, laLeled "cost", is the number of input connections for the optimal networks. For some functions, two or more distinct optimal networks were ohtained. In these cases, only the last network to Le generated is listed in the tahle. Column five, laLeled "num. of intercon" shows the numher of interconnections for each optimal circuit listed (the numher of connections in a given case is easily found Ly subtracting the entry in this column from the cost). Where multiple optimal networks are generated, the numher of connections, interconnections, or levels of gates may vary (of course, the sum of the numher The method of selection will appear later in this section. 27 of connections plus the number of interconnections does not vary) . The sixth and seventh columns of the table indicate, respectively, the greatest number of levels and the least number of levels found among all optimal net- works generated for a given function. Similarly, the eighth and ninth columns show the largest and smallest numbers of interconnections among the optimal networks generated (from this, the largest and smallest numbers of connections are easily deduced) . The next four columns define the pattern of external variable connections for the optimal network listed. The four binary numbers (one in each column) represent the input connections from x , x , x , and x. , respectively. Within each binary number, i, a 1 in the j-th bit position (counting from left to right) indicates a connection of the external variable, x., to the j'-th gate of the network (a indicates the absence of such a connection). The final column specifies the interconnection of the gates. For each function, the entry consists of several groups of consecutive numbers separated by blanks. If we suppose y y ... y is one such group, this is to be interpreted as gate y feeds gates y~, y z>> •••* y • For example, consider the function whose binary representation (defined at the beginning of this section) is 1000100010100111. First, convert this number to hexidecimal form ; we get 88A7. Locating the corresponding row in the table, the entries "00010100", "00101000", "01010000", and "01110000" indicate, respectively: x feeds gates h and 6; x. feeds gates 3 and 5; x_ feeds gates 2 and k; and x, feeds gates 2, 3, and k. The gate inter- connection pattern is specified by the entries "21 325 1+26 51 6l". This means: The hexidecimal (base l6) digits A, B, C, D, E, F correspond, respectively, to the base 10 values 10, 11, 12, 13, lk, 15. 28 gate 2 feeds gate 1; gate 3 feeds gates 2 and 5; gate k feeds gates 2 and 6; gate 5 feeds gate 1; and gate 6 feeds gate 1. Then the optimal network is, as constructed from the table listings: x. X, It is interesting to notice that the majority of the optimal networks found for the functions in Appendix E have the same cost as the networks listed [12] * by Ikeno et al for these functions. So, although Ikeno had sought to minimize only the number of gates required to realize each function, in many cases he had also unknowingly found the networks with the minimal number of interconnections plus connections (for that minimal number of gates). The important difference between this work and Ikeno 's is that, in this work, the networks are known to be optimal in terms of having the minimal number of connections plus interconnections for the minimal number of gates, while in Ikeno ' s case only the number of gates is known to be optimal for each function. Actually, [12] lists only NAND gate networks; but to find the optimal NOR gate network for a, given function using this listing, one need only determine the optimal NAND gate network for its dual. 29 Table E-2 condenses some of the results shown in Table E-l. The number of functions for which optimal networks were obtained is shown for each number of gates. All functions which required 3,^> or 5 gates were exhausted (this fact is known since no other functions were listed by Ikeno as requiring 3> h r ' or 5 gates). The group of 83 functions chosen from the 707 functions of exactly k variables requiring (optimally) 6 gates was a fairly biased sample. Of these 83, 32 were chosen because their corresponding P-equivalence classes each had exactly 6 members; the rest were chosen at random. The k6 7-gate functions were chosen to obtain a good sampling of groups of functions with different numbers of true vectors (i.e., group i consists of all functions of i true vectors, i = 0, 1, 2, . .., l6), as will be shown later in Table C-l in Appendix C. Since 8-gate functions require considerable amounts of computation time to determine optimal networks, only two 8-gate functions were selected. And these two were among the 8-gate functions suspected of requiring the least computation times (this will be discussed more later). For each number of gates, R, the average cost of the optimal networks obtained is shown along with the largest and smallest costs encountered. Also, for each R, the most and least numbers of interconnections and levels are shown. Averages of the columns "most levels", "least levels", "most inter", and "least inter" of Table E-l for each value of R, complete Table E-2. $.1 Computation Time Versus Number of Gates Table 5.1. 1 presents the computation times actually required to obtain the optimal networks listed in Appendix E; the times are given as a function of the number of gates. In studying this table, it must be remembered that 30 the results for 6, 7, and (especially) 8 gates are only partial; only a fraction of the number of functions in these groups were used in obtaining optimal networks. Table 5* 1*1 Computation time vs. number of gates number computation t ime (in sec. )/fn. number of iterat ;ions/fn, of gates least most average total least most average 3 .17 • 32 .26 3.kk 2 8 3.8 k .1*0 • 97 • 55 33.23 5 23 10 5 .75 h.Q6 1.35 317.0 9 152 26 6 1.93 32.55 6.36 527.6 33 798 129 7 l6.ll J+35.2 92.25 1421+1+. 336 7666 1700 8 99^-7 151U. 125k. 2509. 13^55 I89U8 16202 The results in Table 5- 1.1 concerning computation time are graphed in Appendix B. Apparently, the logarithm of the logarithm of the computation time is a linear function of the number of gates (disregarding the 8-gate results as too incomplete to be significant) . 31 5.2 Computation Time Versus Number of True Vectors Interestingly, within a group of functions requiring the same number of gates, there was found to be a strong correlation between the number of true vectors of a function (i.e., the number of l's in the binary representation of a function) and the computation time required to exhaust all optimal net- works for that function. As the number of true vectors increases, the compu- tation time decreases. Table C-l in Appendix C presents this correlation in table form. Perhaps the reason for this correlation is as follows: For every true vector of the output gate, all of the inputs to that gate corresponding to the true vector must be zero; but for every false vector of the output gate, only one of its inputs must be one a.nd the others may be either zero or one, thus the inputs to that gate may assume any of many different combinations of zeros and ones. Therefore, in a rough sense, the more true vectors a function has, the fewer the possibilities which must be tried in synthesizing a network for that function. As the number of gates increases, the differences in the computation time for different numbers of true vectors become more and more pronounced. The results shown in Table C-l are given again, this time in the form of a graph, in Fig. C-l. Notice that this correlation is just a general tendency; any given function may not hold to this pattern. For example, in the 6 -gate case we see the computation time rising as the number of true vectors decreases (i.e., as the number of false vectors increases), but the tendency seems to reverse itself as the number of true vectors drops below four. In particular, there is only one function with two true vectors; and, instead of requiring the 32 longest time, its computation time is even less than the average time for a 6-gate function. So any predictions based on this tendency should only be applied to fairly large samples of functions. Again, remember that the results for 6 or more gates are based on only partial samples. The two functions which required 8 gates were specifically chosen for their large numbers of true vectors (13 apiece); it was anticipated that only such 8-gate functions would be within computational range. Indeed, this sus- picion was supported by the fact that these two functions were among those functions requiring the least amount of time out of a group of 8-gate functions run with a program using a "branch and bound' algorithm. This is a program specifically tailored to the task of designing NOR networks (and hence, is considerably faster than the implicit enumeration program used for this report), which had proven itself in earlier trials to be a fairly good indicator of the relative difficulty of solving a given function by the implicit enumera- tion program. Another interesting observation that we may make at this point is that the "easiest" f requiring the least amounts of computation time) functions of R gates required approximately the same amount of time as the "hardest" (greatest computation times) functions of R-l gates. The suspected cause is as follows. First, it should be pointed out that no external variables can be connected to the output (NOR) gate of a network realizing a function of 9 or more true vectors (any such connection would force 8 input vectors to be false vectors for this gate). So the program must attempt to connect * ri7l Program developed by T. Nakagawa and H.C. Lai improving on a previous work by Davidson in [6]. 33 other gates to the output gate. One of the cases it considers is the case when only one gate (call it gate number 2) connects to the output gate. What is the output of gate 2? It is just the complement of the original function, and the complement of a function of very many true vectors is a function of very few true vectors (and there are now R-l gates to realize this second function) . So a function of R gates which has a large number of true vectors is somewhat like a function of R-l gates which has a small number of true vectors. Of course the argument given here is quite crude and ignores many important factors, but it is only intended to point out a likely cause behind the observation. 5.3 Comparison with Three Variable Case Earlier, C.R. Baugh et al had found optimal networks for 3-variable y- f unctions using an all-interconnection NOR formulation. Since the implicit enumeration program he used was somewhat different from the one used here, the results cannot be considered directly comparable. He assumed unlimited fan-in and fan-out (except for the 8-gate problem, where fan-in, fan-out = 3) and also assumed the three gate subnetwork (gate 1 is the output gate of the network to be synthesized): *- The algorithm used is described briefly in [2] and also the results for the 3-variable parity function (requiring 8 gates) are contained. The results for the other 6- and 7-gate, 3-variable functions discussed in this section are as yet unpublished. 3k The present program is somewhat Improved (various programming gimmicks were added, as well as a subroutine to automatically generate the neces- sary inequalities) over Baugh's original version, hut it does not assume the existence of any such subnetwork. The average computation times for 3-variable functions are compared with those for ^--variable functions for 6, 7, and 8-gate cases (dotted lines in graph of Appendix B). The average computation times for 3-variable functions of 6 and 7 gates are approximately equal to the lowest computation times for 6- and 7-g a te_, k- variable functions (which were investigated for this work), respec- tively. The computation time for the 3-variable function of 8 gates was far below even the lowest time for a ^-variable function requiring 8 gates. The ratios between the average computation times for the 3-variable and the U-variable functions (for the case of 6, 7, and 8 gates) are: number of gates ratio (3-var : k-var) 6 1 : 2.k 7 1 : 5-5 8 1 : ll.lt 35 6. CONCLUSION This report, combined with earlier reports along similar lines ' , demonstrates the great flexibility of the integer programming approach in the design of optimal networks using different types of gates and network restrictions. The computations were performed by an IBM 360/75 I system using both the G level and H level Fortran IV compilers (for different subroutines). The program used to solve functions of 7 or fewer gates required 232K bytes of core, while the 8 gate program required about ^50K bytes; although the necessary memory space could be reduced by a more ingenious packing of data, computation time would probably increase due to a longer time needed to access this data. Totally, U38 P-equivalence class representatives (representing 6303 functions) were solved in about 7^30 seconds. [12] The results proved that many of Ikeno's networks were optimal both in the number of gates (first) and (secondly) in the total number of connections plus interconnections. For the 13 functions requiring 3 gates, no networks were found better than Ikeno's in terms of our optimality criteria; for the 60 func- tions requiring k- gates, k networks were improved over Ikeno's. Results were not compared for the cases of more than 5 gates. It was found that the log of the log of the average computation time appar- ently varies linearly with the number of gates in the formulation. More importantly, it was discovered that if a group of functions requiring R gates is considered, then the functions with few true vectors tend to take more computation time to determine optimal networks than the functions with many true vectors. Also, the magnitude of this variation seems to increase with R. 36 Appendix A Backtrack Procedure The backtrack procedure works, briefly, as follows: A partial solution S is an ordered set of binary assignments to certain variables. An assignment to a variable x. is said to be underlined if we have already investigated all of the J / partial solutions, S 's, which have assignments identical to S of the variables preceding x., have x. assigned to the complement (of that value assigned in S), and have arbitrary assignments following. An assignment is not underlined if we have not investigated all such S . In the implicit enumeration algorithm we often reach a point where the current partial solution is known to have no feasible completions or a point where it is clear that all possible completions of this partial solution would exceed the cost of the incumbent. We then backtrack to obtain a new partial solution by locating the rightmost non-underlined element of the partial solution (if none exists, the algorithm terminates), setting this element to its comple- ment and underlining, and deleting all elements to its right. This backtrack procedure is also used to obtain the next partial solution after a feasible solution has been found. 37 Appendix B Number of Gates vs. Computation Time The graphs in Fig. B-l and Fig. B-2 show the computation times re- quired to synthesize optimal networks of different numbers of gates. The three solid lines in Fig. B-l show, for each number of gates: the most, average, and least computation times required to synthesize networks for U-variable functions needing that number of gates. The dashed line shows the average computation time for some 3-variable functions of 6, 7 > and 8 gates. Fig. B-2, the inset to Fig. B-l, plots the log of the log of the average computation time (in centiseconds) of the U-variable functions, against the number of gates required to realize those functions. 38 1000 100 10 io -r H EH O CO O O H CQ H O o p; • o >; ^ C5 2 ~ NUMBER OF GATES Fig. B-l Computation time vs. number of gates IEAST TIME variable case- solid lines variable case- dashed lines NUMBER OF GATES 39 Appendix C Number of True Vectors vs. Computation Time The first part of this section of the appendix is a table displaying the average computation time, t. ., for each group of functions (for which optimal networks were obtained), F. ., having i true vectors and requiring j gates (i = 1, ..., 15; j = 3, •'•> 8)- The number of elements in each group F. . is also shown. The last part is a graph of the information contained in this table. Notice the slope of the lines from left to right. i ko oo s s 1 H P-H co < i o fe s s O [X, _4 3 CM CD -p o •H ■P w f> w rH o -p o -P H w H H LCA _4 VO -4 VO VO lAIAIALlAlf\ir\lAlA4 -4-4 t^ CM VO lA O in I- IA 4 H LTN o vo oo s H CD O w § o 0) w Ed •H CD 8- w CD co OO rH 6 pt) 2 fe s S O (^ o oo vo CM OO -4 VO O \T\ LTN CM CM CO CM CM H CM CM CM CM CM rH K CO H [V| Ph pq J_J o 2 o Ph H i— > H CO 3 rH H H H rH kl 10000 -r- Fig. C-l Number of true vectors vs. average computation time 1000 .8 GATE 1 2 h 5 6 7 9 10 n 12 13 i^ i 5 ' NUMBER OF TRUE VECTORS k2 Appendix D Networks of Two or Fewer NOR Gates This appendix lists all functions of exactly h variables which require fewer than 3 NOR gates. Degenerate functions of k variables (i.e., functions which actually depend on only 0, 1, 2, or 3 variables') are not included. h3 x. X, X, x l x 2 x 3 \ X. X, Xi >- X, v X^ -^ X^ v X 1 v "2 v "3 ^ X. X, X. X, x 3 >. (x x ^ x 2 ) x x^ X. Xi x l x 2 x 3 x h kk Appendix E Optimal Networks This appendix consists of two tables. The first of these, Table E-l, lists the configurations for all of the optimal networks found in this work. Earlier in the text, it is described how to use this table. The second table, Table E-2, summarizes some of the information given in Table E-l. The use of this table is also described earlier in the text. The number of optimal networks for each function was not given due to the difficulty in determining which generated optimal networks are equivalent (i.e., the program may generate the same network twice or more, with a different permutation of gate labels each time). ^5 Table E-l Optimal Networks for certain U- variable functions k6 IT -t .J- -* it. in m in ur> ^ — . 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M V-* —4 1-4 o —* r-4 •~A ^4 —4 *"■ ^~> *"■ — •-« »-• —* •— i _t c o o o o o o o — o r~t o o -" — - -' — rt -- — -" — — — — — — _ _ — — -< — — — _ _ _ ^ o — t~ o o o o o O o r- o r . i-. ^ rt o d — — 1 ^ r- o _ „ _ ^ _. o c- <- _ o o o o ""* "^ o o c- o c~ o o - - - - - - <-> o o C3 o o r-i o o c D " o -- «-» r. o n a C o o - r. - - - " o o o o o o o o ifNinMnir^r.'t'ir^ir^^ g^u^li*'>J■lPl^^rlL^^lJf^^i , 'lrocu'l/^l/^lf^ac<>^- «t i/\ -o in ^) Ku. Cu-Cu^_u-C cru. au.oc3ii-b.oau.ir. a.u-uu u u U> U-U-OOOOu u. U.LjLLluU' H ^ o t- a ><•>!_ < C z 1 — 1/1 nr UJ Z o »- > 1/1 > «1 C uj X _J o iu U. ut C UJ 55 56 LIST OF REFERENCES Balas, E. , "An Additive Algorithm for Solving Linear Programs With Zero-One Variables/' Operations Research , vol. 13, no. k, pp. 517-5^9, July -Aug., 1965. r?i Baugh, C.R. , T. Ibaraki, T.K. Liu, and S. Muroga, "Optimal Network Design Using NOR and NOR-AND Gates by Integer Programming," Report no. 293, Department of Computer Science, University of Illinois, January, 1969* r o 1 Breuer, M.A. , "implementation of Threshold Nets by Integer Linear Programming," IEEETEC, vol. EC-lU, no. 6, pp. 950-952, Dec, I965. Ik] [5] [6] [7] [8] [9] [10] [11] Cameron, S.H. , "The Generation of Minimal Threshold Nets by an Integer Program," IEEETEC , vol. EC-13, no. 3, pp. 299-302, June, 1964. Chandersekaran, C.S., "Synthesis of Optimal Double-Rail Logic Networks Using NOR-OR Gates by Integer Programming," Report no. 384, Department of Computer Science, University of Illinois, February, 1970° Davidson, E.S., "An Algorithm for NAND Decomposition of Combinational Switching Systems," Ph.D. dissertation, Department of Electrical Engineering and Coordinated Science Laboratory, University of Illinois, 1968. Fleischman, B. , "Computational Experience With the Algorithm of Balas," Operations Research , vol. 15, no. 1, pp. 153-155, Jan. -Feb., 1967* Geoffrion, A.M., "Integer Programming by Implicit Enumeration and Balas' Method," SIAM Review , vol. 9, no. 2, pp. I78-I9O, April, 1967. Glover, F. , "A Multiphase -Dual Algorithm for the Zero-One Integer Programming Problem," Operations Research , vol. 13, no. 6, pp. 879- 919, Nov. -Dec, I965. Hellerman, L. , "A Catalog of Three-Variable OR- Invert and AND- Invert Logical Circuits," IEEETEC, vol. EC-12, no. 3, pp. 198-223, June, I963. Ibaraki, T., T.K. Liu, C.R. Baugh, and S. Muroga, "Implicit Enumer- ation Program for Zero-One Integer Programming," Report no. 305, Department of Computer Science, University of Illinois, January, I969. [12] [13] ilk] [15] [16] [17] [18] [19] 57 Ikeno, N. , A. Hashimoto, and K. Naito, "A Table of Four- Variable Minimal NAND Circuits," Electrical Communication Lab. Tech. J . , Extra Issue no. 26, Electrical Communication Laboratory, Nippon Telegraph and Telephone Public Corporation, Tokyo, Japan, 1968 (in Japanese) . Liu, T.K. , "A Code for Zero-One Integer Linear Programming by Implicit Enumeration," Master thesis, Department of Computer Science, University of Illinois, I968. Muroga, S. and T. Ibaraki, "Logical Design of an Optimum Network by Integer Linear Programming-Part 1," Report no. 26k, Department of Computer Science, University of Illinois, July, 1968. Muroga, S. and T. Ibaraki, "Logical Design of an Optimum Network by Integer Linear Programming-Part 2," Report no. 289, Department of Computer Science, University of Illinois, December, 1968. Muroga, S. , "Logical Design of Optimal Digital Networks by Integer Programming," in Advances in Information Systems Science , vol. 3j J.T. Tou, Ed. Plenum Press: New York, 1970, pp. 283-3^8. Nakagawa, T., and H.C. Lai, "A Branch-and-Bound Algorithm for Optimal NOR Networks," Report no. i+38, Department of Computer Science, University of Illinois, 1971« Swee, R.S., "Optimum Network Design Using NOR-OR Gates by Integer Programming," Master thesis, Department of Computer Science, University of Illinois, 1970. Taniguchi, K. , N. Tokura, T. Kasami and H. Ozaki, "Logical Functions Realizable by a Planar NAND Network," The Transactions of Electronics and Communications Engineers of Japan, vol. 51-C, no. 2, pp. 59-65* February, 1968. IHi wm ■■ MB ■B H * H I I UNIVERSITY OF ILLINOIS-UBBANA UNIVERSITY OF ILLINOIS-UBBANA 510.84 IL6R no. C002 no.480-466(1971 Synchtonlutlonsyst.m tor. revision ^Q112 088400061_ *"s ■ ■ > 'j * i