LIBRARY OF THE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAICN CENTRAL CHCULATIOH „ "* "brary fr ' ts re "ewal ™f. ter,a ' « re- below, roo ™ ? l ««» dL. borr °wed £"; ""»-»«.. « eot '' '<•» b^fc" m, -« MAR When Digitized by the Internet Archive in 2013 http://archive.org/details/orbitonlinereduc430ober / L , "l I REPORT NO. 430 )7UM COO-1U69-0178 ORBIT ONLINE REDUCED BANDWIDTH INFORMATION TRANSMISSION by PETER ERNST RUDOLF OBERBECK February, 1971 The Lit: REPORT NO. U30 ORBIT ONLINE REDUCED BANDWIDTH INFORMATION TRANSMISSION* by PETER ERNST RUDOLF OBERBECK February, 1971 Department of Computer Science University of Illinois Urbana, Illinois 6l801 * Supported in part by Contract Number U.S. AEC AT(ll-l) lh69 and submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical Engineering at the University of Illinois, February, 1971. ORBIT ONLINE REDUCED BANDWIDTH INFORMATION TRANSMISSION Peter Ernst Rudolf Oberbeck, Ph.D. Department of Electrical Engineering University of Illinois at Urbana-Champaign, 197 1 This paper describes a real time television bandwidth compression scheme proposed by Professor W. J. Poppelbaum in -which the required bandwidth is a function of the complexity of the picture to be transmitted. The class of pictures to be transmitted are black on white line drawings. The encoding and decoding of the picture are done by two digital processors. The trans- mission link between the two digital processors is an analog line with a D/A conversion at the transmitter and an A/D conversion at the receiver. The paper describes in detail the operation of the transmitter and receiver and their interaction with peripheral systems such as the camera and television monitor. The encoding involves a time to voltage conversion and redistribution of the various points of information on the picture. The decoding process reconverts voltages to times and uses these times to place points of information in their original position on the picture. The bandwidth requirements for the system are analyzed, with the conclusion that an average bandwidth compression of twenty-five to one can be realized. This, however, is a strong function of the complexity of the picture to be encoded. A circuit section describes the operation of each circuit card used in the system and shows a schematic diagram of each circuit. Ill ACKNOWLEDGEMENTS The author would like to thank Professor W. J. Poppelbaum for his guidance and counsel in the development of this project. His patience toward the completion of the project was both persevering and encouraging. The author is also indebted to Edward Carr and Arthur Simons for their contributions to the project. Appreciation goes to Carla Donaldson for deciphering and typing the manuscript . IV TABLE OF CONTENTS Page 1. INTRODUCTION 1 2. TRANSMITTER ' k 2.1 Video to Logic Conversion h 2.2 Camera Synchronization 7 2.3 Transmitter Synchronization 9 2.U Video Encoding 17 2.5 Horizontal Lines 23 3. RECEIVER 27 3.1 Receiver Synchronization 27 3.2 Video Decoding 29 k. BANDWIDTH REQUIREMENTS 35 5. NOISE AND ERROR CONSIDERATIONS 39 6. CIRCUITS kh 6.1 Dual Nine Bit Register -- 130A and Nine Bit Register -- ih'J kk 6.2 Thirty-Two Bit Shift Register (Card 1 -- 131 and Card 2 -- 132) 1+7 6.3 Nine Bit Buffer -- lU2 50 6.U Thirty-Two Input Nand -- IU3 and Sixty -Four Input Nand Extender -- lUU 50 6.5 Nine Bit Counter -- lU6 52 6.6 Counter Extender and Decoder -- 219 57 6.7 Master Synchronization Logic -- 15 5A 57 6.8 Operational Amplifier and + 15 Volt Supply -- l60 .... 60 6.9 Nine Bit Digital to Analog Converter -- 167 60 6.10 Clock and Driver -- 169 65 6.11 Sixteen Bit Counter Gate -- 283 65 6.12 Comparator -- 33U 67 6.13 Logic to Video Converter -- 336 67 6.1k Bandwidth Selector and Line Switch -- 3U0 71 6.15 D/A Gate -- U39 73 6.16 Synchronization Converter II -- kk^ 7k 6.17 Video to Logic Converter II -- kk$ 76 6.18 A/D Level Shifter 77 6.19 A/D Converter and Power 77 7. SUMMARY 80 LIST OF REFERENCES 8l VITA 82 V LIST OF FIGURES Figure Page 1. Video to Logic Converter 6 Video to Logic Converter II 8 Camera Synchronization 10 Master Synchronization Logic 11 Odd and Even Field Code Generation 13 D/A Gate ±k Transmitter Timing Diagram 16 Transmitter Block Diagram 18 Detailed Transmitter Block Diagram 19 Video Encoding Scheme 21 Receiver Block Diagram 30 Receiver Timing Diagram 31 Detailed Receiver Block Diagram 32 Encoded Video Passed Through an RC Filter 36 Dual Nine Bit Register 1+5 Nine Bit Register 1+6 Basic Circuit of Digital Storage Register 1+7 Thirty -Two Bit Shift Register (Card l) 48 Thirty-Two Bit Shift Register (Card 2) 1+9 Nine Bit Buffer 51 Thirty-Two Input Nand 53 Sixty-Four Input Nand Extender 51+ Nine Bit Counter 55 Counter Extender and Decoder 58 VI Figure Page 25. Operational Amplifier and + 15 Volt Supply 6l 26. Nine Bit Digital to Analog Converter 62 27. Clock and Driver 66 28. Sixteen Bit Counter Gate 68 29. Comparator 69 30. Logic to Video Converter 70 31. Bandwidth Selector and Line Switch 72 32. Synchronization Converter 75 33. A/D Level Shifter 78 34. A/D Converter and Power 79 1. INTRODUCTION ORBIT (Online Reduced Bandwidth Information Transmission) is a television "bandwidth reduction scheme that will transmit a special class of pictures over a narrow bandwidth. The advantages of a narrow bandwidth need hardly be justified with present day communications channels being as over- crowded and expensive as they are. The resultant narrower bandwidth not only saves valuable bandwidth, but it tends to ignore high frequency noise and hence results in a better and more accurate transmission. The class of pictures to be transmitted is limited to black on white line drawings with no shades of grey or large black areas. Since this class of pictures has inherently less information content than pictures with shades of grey and much detail, like a photograph, one can - by suitable encoding - produce a video signal that has considerably less bandwidth than would normally be required. The complexity of a picture is a measure of its information content and consequently the bandwidth required to transmit it. From this we can conclude that a line drawing should lend itself readily to some bandwidth reduction scheme. In the ORBIT system the bandwidth is directly proportional to the complexity of the drawing to be transmitted; the complexity being measured by the number of intersections a horizontal scan encounters when sweeping across a picture. The band- width required is roughly 20Khz times the number of these intersections, with the upper limit being thirty- two intersections. If the upper limit of thirty-two intersections is exceeded, the picture is truncated at that intersection with the quality of the first part of the picture being unaffected. It may seem that thirty-two points is a rather low figure and that a picture with any complexity would have more than thirty-two points of intersection with a straight line drawn through it. This is n< the case unless some writing in the drawing is encountered. If one were take the pictures in this paper as drawings to be transmitted one can see that just about all of them could be transmitted without exceeding the thirty-two point limit. The resolution of the system is 512 lines horizontally and about 350 lines vertically. A bandwidth of about lOMhz would normally be required to transmit a picture with that horizontal resolution. With the ORBIT system an average bandwidth reduction of about twenty-five to one can be expected, depending on the complexity of the picture . Processing of the video signal is done almost entirely digitally in both the transmitter and the receiver. The link between the transmitter and the receiver is an analog link with a D/A conversion at the transmitter output, a low pass filter and an A/D conversion at the input of the receiver. Hybrid processing is also done in the video to logic and logic to video conversion. The system uses a conventional vidicon television camera as a pickup device, and a television monitor as an output display. Synchronization and video levels are the same as standard broadcast television signals. This makes the system completely compatible with all standard 525 line television systems. Except for a 126us delay, the system works in real time, so that an observer could not detect that the picture is being sent over a reduced bandwidth. Many bandwidth compression schemes work on the principle of taking more time to transmit a given amount of information which becomes obvious when the picture changes rapidly. The basic principle behind the ORBIT encoding scheme is that the information is redistributed in such a way that its bandwidth is relatively constant. If a great deal of detail exists in one part of the picture, the information contained in that part is redistributed to parts of the picture that have very little information content. The result is essentially that a high bandwidth requirement is averaged with a very low bandwidth requirement resulting in a lower overall bandwidth requirement. 2 . TRANSMITTER 2.1 Video to Logic Conversion The class of pictures that the system operates on is limited to black on white line drawings. The black on white feature readily lends itself to the binary on, off or logical zero and one conditions. So, the first operation that the system performs is a video to logic conversion in which all white areas on the picture are represented by a logical one and all black areas (points and lines) by a logical zero. The video signal that comes from the camera is a standard one volt peak to peak signal with blanking and sync included. It would be a trivial matter to convert the video to a logic signal if the video were well-behaved, that is if a white background would always be a certain voltage and a black line (or area) would always be another voltage. A simple threshold detector could then do the video to logic conversion, where everything above some predetermined level would be a logical one and everything below a logical zero. Unf ortuantely, the video signal is not well-behaved, but has a considerable variation in the back- ground or white level of the picture. A characteristic curvature that varies from line to line can be observed. The white video level will typically be lower at the beginning and end of a horizontal line than in the center. There is also a variation as the picture is measured from top to bottom, with the top and bottom lines having a lower white video level than those in the center. This variation in the white level is due to the beam landing error inherent in the vidicon electron-optical system. If the curvature is well-behaved it is a rough parabolic variation and can be corrected by modulating the cathode current. For the vidicon used in this particular system the variation was not predictable and made correction for this problem very difficult. The detection of a black level is essentially the same as detecting a white to black transition, except that one could not detect the size of a large black region. Since initially there was no interest in detecting the size of black regions, a scheme that would detect a transition proved to be adequate. A differentiation circuit with a high frequency response and no low frequency response would produce an output at each white to black and black to white transition yet not respond to the relatively low frequency of the curvature. The diagram in Figure 1 shows the circuit used. An integrated circuit video amplifier with a lOOMhz frequency response is used as an operational amplifier and wired to perform as a frequency selective differentiator. Low frequency response is limited by the RC time constant determined by the 150pf input capacitor and the 10K feedback resistor. The 5pf across the 10K feedback resistor limits the upper frequency response of the differentiator. This is necessary since high frequency noise would be amplified and differentiated. Output of the differentiating circuit then goes to an emitter follower that serves as a buffer. A threshold detection of this differentiated signal is then done by the next stage. Only the negative pulses due to a white to black transition are detected. The 2N97& is used as the threshold device and the 2Nl6l3 and its associated circuitry as the threshold voltage reference generator. The logic circuitry that follows is used to blank out that portion of the signal that occurs during horizontal sync and retrace. It is then also compatible with the TTL logic used in the rest of the system. In order to transmit a horizontal line it becomes necessary to detect a continuous black level. The system is designed to handle data on a point by point basis. Therefore, it becomes necessary to convert this black level into a series of points. This is done by using the black video cr LJ cc UJ > u 5 o o UJ Q u CD -p u d) !> O O a •H bO o O -P O CD T3 •H > •H W» ||l a i > 7 level to gate a multivibrator on and off. If a narrow pulse of less than 200ns triggers the multivibrator it acts like a single-shot and only produces one output pulse. If a wide pulse of greater than 200ns triggers it, then a series of equally spaced pulses occur for as long as the video level is black. This way a horizontal line can be approximated by a series of dots. Again the video curvature becomes a problem, because one has to perform a strict threshold detection in order to detect a long black video level. The problem was mostly solved by using a very high contrast drawing in front of the camera. Black lines on transparent celluloid paper, backlit by a white diffused light source. Using this method, most of the picture despite the curvature would be threshold detected. Figure 2 shows a schematic of the gated multi- vibrator video to logic converter, with its associated video threshold detection circuitry. 2.2 Camera Synchronization The camera being used has a standard 525 line raster scan with a 15750 horizontal line repetition rate and a 2:1 fixed interlace. It is required that the camera start a horizontal sweep each time the system synchronization clock is at count zero, and the system is ready to start the encoding process. Each visible part of a horizontal line is 5Q-is long and is divided into 512 time slots, so that a nine-bit counter or register could be used to store any point on a horizontal scan across the screen. This determined the fundamental clock rate of 9.^50Mhz for the system. Since the total time for a horizontal scan, including retrace is 63.5M-S, a count of 600 from the 9«^5Mhz clock is required for one complete horizontal video line. The fixed 2:1 interlace causes every other field to start its scan in the middle of a horizontal line, therefore, the count of 300 must be detected. 8 H U d) -P u > a o o o •H M O o •p o tu 13 OJ •H F-4 This count of 300 from the 9«^50Mhz clock constitutes the main sync signal to the camera. Its repetition rate is 31.5Kh z - Figure 3 shows a block diagram of the camera synchronization scheme. The transmitter oscillator is fed into a divide by 300 counter whose output is then used to externally synchronize the camera. The external synchronization input on the camera did not function properly when used as it came from the factory. The input signal was effectively differentiated by a lOOpf input capacitor and then used to synchronize a multivibrator. Due to the differentiation, noise would also trigger the multivibrator causing it to behave erratically. This problem was corrected by bypassing the multivibrator and direct-coupling the 31.5Khz to the camera synchronization circuitry. A logic level shifter and a driver to drive a 75 ohm line were required to do this. The camera provides a horizontal drive signal which has a 15750 repetition rate and indicates the beginning of a horizontal scan to the rest of the system by clearing the master synchroni- zation counter. 2.3 Transmitter Synchronization All system synchronization signals are generated in the "master synchronization logic" card shown in Figure h. This card was designed with enough flexibility to be used in both the transmitter and the receiver. All timing signals are available in their true and inverted form. There are three basic time intervals in the operation of the transmitter. Horizontal blanking, horizontal scan and vertical blanking. Total horizontal line time is 63.5M-S, 13.5M-S of which is used for horizontal blanking (retrace) and 5Qas for actual displayed video, or horizontal scan. Vertical blanking consists of approx- imately 21 horizontal line times or 1335[J-s. Transmitter synchronization takes place during horizontal and vertical blanking times. Video processing takes 10 a < cc 2 x < o i r cr a: z uj o Ld K — *3 S < "= 2 g P v o Z 7 UJ o »" 2 3 ^ %. o / DIVII 300 « 5 o ° ? < > * o o _J N O X 2 cr Ld ? s 0> 5 o z CO o •H -P CO N •H O a c 03 CO 8 CO o no 0) •H 1*1 F.E. MASTER SYNCHRONIZATION LOGIC -155 A 11 x, >- Xs ^4 x a > X4>-§ x 5 >- X, >- x 6 >- L__JJ_. 13 I r~" 13 3T ©-: 12 2 10 6 9 12 5 12 d> ©- _QQ 12 H 21 3 ' H __AOJ ii ©- 131 12 I 11 12 10 12 ill I _8Q_J (i> 4| 7Q ©" 101 80! l___5Tj PARTS LIST 4 TRIPLE 3 INPUT NAND GATE SN74I0N. 4 QUAD. 2 INPUT NAND GATE SN7400N. ©TO PIN 7 OF ALL IC'j "2* T ^ 2.2^f Q> TO PIN 14 OF ALL IC $ x- 20 =♦ Nl i*Ni ■♦ N2 T — -► N2 N3 ^*N3 22 — < -5V ' ;^j GND Figure h. Master Synchronization Logic place during the rest of the time. The video is processed on a line by line basis consequently horizontal blanking time is used to prepare the system for video processing. This processing is also attempted during vertical blanking, but due to the absence of video during this time only "blank" lines are produced, of which some are used to generate vertical synchronization information for the receiver monitor. In particular, the vertical sync pulses are generated, and "odd" and "even" field information, to provide the correct interlace, is also generated. This information is coded into the first two "blanked" lines during the vertical blanking interlace. Normally a blank video line would consist of a plus five volt DC level. To indicate an even field this five volt level is pulled to zero volts during the first UOus of the first two lines during vertical blanking. To indicate an odd field, only the second line is pulled to ground. To do this one has to have the vertical and horizontal drive pulses from the camera, as shown in Figure 5. During an even field, the vertical drive pulse (VDgy^) starts at the same time as a horizontal drive pulse (at the beginning of a horizontal line), but during an odd field it starts half way between two horizontal drive pulses (VD ). A single shot of about TTM-s duration is now used to shorten the vertical drive pulse (Bg^,:^^). The logical AND of HD and B EVEN ,B 0Dr) will produce two pulses at the beginning of an even field and one pulse during the beginning of an odd field, (C____,C n ). These pulses are now lengthened to UOu.s each (D rrtrnT . T ,D ) and then used to pull the video level to ground during the first hvilN ODD two, or second line of vertical blanking, to indicate the beginning of an even or odd field respectively. The circuit that performs the above function and the gating of the logic signals to the D/A converter is shown in Figure 6. The remaining 19 lines of vertical blanking are not used, but could carry such 13 to to o •H -P aj U a; d a> o UJ Q > a a o a > z > UJ CD Q Q O CD UJ > UJ a Q O o z UJ > UJ o a o 11+ 4 4 AAA IO cm I A;;A;A A A n c\j 2 < £ -i z H ■) n ?■ (/) D CO •H Q •H 6 •H *H or CO x CD C\J tO GO Z GO GO X 17 video storage registers. N3 is then used to clear the video counters so that they can be filled again with counts during the following video line. The video registers need not be cleared since the transfer of new information into the registers during N2 automatically clears all previous information contained therein. In addition to the BW blanking signal there is another blanking signal (HB) available that is initiated at the same time as BW but lasts longer. It is used to blank out some noisy video at the beginning of a horizontal scan in the video to logic converter. This entire synchronization scheme is repeated every horizontal scan and is with the exception of the odd and even field coding independent of vertical synchronization. 2.h Video Encoding The encoding process in the transmitter takes place on a line by line basis. Each horizontal scan line is treated independently of all the others. As far as the processor is concerned, information is received serially from the camera, processed for 127us, and then passed on serially to the digital to analog converter which transmits it. The information or video received from the camera is redistributed in such a way that the band- width of the outgoing signal is less than that of the incoming signal. Consider Figures 8 and 9 and what happens in the transmitter during the entire encoding process of two horizontal line times (l27us). Let us assume that the camera has just completed a scan of the picture and is about to retrace to start a new scan. At this point the master synchronization logic has reset the thirty-two nine bit counters (with pulse N3) that is used to receive video information, and the thirty-two bit counter gate that sequentially stops each of the counters as video information (VID) is received, Q. 3 O 18 VI cr UJ 1- U cc or < >- UJ c/> QC c/> z ° 3 UJ ^^ < A o > V s CO h bO CO •H (M ro 9 BIT EGISTERS n o o H PQ QJ i r K •P •P ■H A > s G _j CO EH ° o • CO k o z o o -J o _i < o 2 19 » 45 MNc CLA CLOC« JTJ— i CL ©■ ©■ CL£U ukii rw CT» -CM— m vd «m MWC 1IT CTJTt==) ^> *.-«. V 8» 5ELCCT0K V BIT t •— • !!•- CM 2 vS 4> ^> {^ UM (IT 2 •IT • SI MT COUNTER

o t- s -I < to 3 Ql Z / > 00 UJ cc o > UJ cc 3 o ,c o CO a ■H o o fi w o •H > O H bO •H _p 22 line. For this example four intersections are being used. This means that the bandwidth selector will divide a horizontal line into four, eight, sixteen or thirty-two equal time periods. This is done by decoding the output of the bandwidth selector counter to give the appropriately spaced pulses. These pulses are then used as clock pulses for the thirty-two bit ring counter that "reads out" the storage registers. As the first (of the four pulses for this example) clock pulse from the bandwidth selector reaches the "read out" ring counter, bit one of the counter goes positive or to a logical one. This logical one is applied to a nine bit gate on register one of the thirty-two storage registers and causes the contents of this register to be connected (through an OR gate) to the digital to analog converter. The content of the register stays connected to the D/A converter until the second clock pulse from the bandwidth selector is received by the thirty-two bit ring counter. This second pulse causes bit one to go to a logical zero and bit two to go to a logical one until bit three is received, and so on. The contents of register one is now disconnected from the D/A converter and the content of register two is applied to this converter until bit three of the ring counter goes positive, and so on. This means that during each of the four equal time periods (of 12.5|J.s for four intersections) the contents of each of the first four storage registers was applied sequentially to the D/A converter. As we recall from an earlier explanation the contents of each of the storage registers corresponds to elapsed time (t,,t ,t ,t, ) or position (referenced from the left hand edge of the picture) of points of intersection that the scan made with the picture as shown in Figure 10B. The voltage output of the D/A converter during each of the four time periods then corresponds to the elapsed time (t ,t ,t ,t, ) of each intersection of the scan with the picture. Since t < t < t < t. , the 23 output voltages are V < V < V < V, . The output of the D/A converter is a. stairstep voltage with the amplitude of each voltage step corresponding to a point on the picture as shown in Figure IOC. Each time period is converted to a voltage level. The mapping of these times (or points of intersection) into voltages have the following limits. A point on the extreme left hand edge of the screen would correspond to a voltage near zero volts. A point at the extreme right hand edge of the screen would correspond to plus five volts. All points in between are linearly distributed from zero to plus five volts as the position of the points moves from the left hand edge of the picture to the right hand edge of the picture. The output of the stairstep function is then filtered to remove all high frequencies, and the remaining low frequency waveshape (dotted line in Figure IOC) is the actual transmitted video. Synchronization signals for the receiver monitor are also inserted at the transmitter. This is done in the D/A gate (Figure 6). For horizontal sync and correction signal to the 9.^5 MHz receiver clock, the output of the D/A converter is pulled to ground during each 13.5M-S horizontal blanking period. For vertical sync and odd and even frame information, the output of the D/A converter is pulled to ground during the first one or first two horizontal lines during vertical blanking respectively. 2.5 Horizontal Lines It was clear from the onset that the transmission of horizontal lines in the ORBIT system would be a problem. This is due to the nature in which information is detected. The detection mechanism relies on the scan of the vidicon intersecting a line on the drawing to be transmitted. This process works fine for vertical lines, well enough for slanted lines, but not at all for horizontal lines. At best only the initial white to black 2k transition of the horizontal line can be detected. The rest of the horizontal line is ignored. Furthermore the encoding process lends itself to a point by point type of encoding and does not lend itself to processing line segments. It was felt that the transmission of horizontal lines is a necessity in the final ORBIT system, so a solution had to be found. A multitude of ideas were pursued in an effort to come up with not only an elegant, but feasible scheme. The first idea that was investigated was to scan the picture alternately in two directions, one vertical and one horizontal. This, of course, would convert all horizontal lines during one scan to vertical lines on another scan and consequently encode the entire picture properly. Theoretically this scheme is very good, but practical implementation makes the task monumental. Difficulty arises in trying to scan a vidicon alternately in two directions. Special purpose deflection yokes would have to be built to accomplish this. Furthermore the synchronization scheme of the camera would have to be changed considerably. This would no longer make the system compatiable with standard broadcast television, which was an original intention. A far bigger stumbling block is encountered in trying to reconstruct the image. A television monitor with magnetic deflection uses resonant yokes to achieve this. To turn the scan by 90 degrees one would have to stop and start resonant circuits, a task that is not at all trivial. One could go to a different deflection system, but again this would mean special purpose equipment. The greatest problem, however, would be the alignment of the two images on the monitor. The linearity of a television monitor is at best three to four percent. To achieve acceptable alignment of the images to be trans- mitted, one would need .1 per cent linearity. Considering the problems involved it would hardly be worth while to use this avenue of approach without investigating other methods first. Since the presence of a horizontal line 25 can be detected without too much difficulty, it was thought to switch the system into a slightly different mode of operation when this occurred. A horizontal line can be sensed by a long continuous level of black in the video signal. A decision can be made that if a black level exists for more than 200ns it will be called a line. With this fundamental decision, two more methods of transmitting horizontal lines were developed. The first method transmitted the beginning and end point of a horizontal line. The part of transmitting the endpoints of the line were simple. All one had to do was treat the beginning and end of a line like they were normal points of inter- section. The difficulty was in knowing at the receiver which points were actual intersection points and which points were beginning and end points of line segments. The encoded video happens to be a monotone increasing stair- step function. That is, each step is longer than the previous one. This, of course, stems from the fact that each point of intersection is further from the left hand edge of the screen than the last one. If one were to alter this monotonicity in some way one could detect this and interpret it as the beginning of a horizontal line. This was precisely what was done. Each time a horizontal line was to be transmitted the beginning point of that was line was transmitted twice. The endpoint did not receive any special tag since it would logically follow that the next point would be the end of the horizontal line segment. The receiver upon encountering two successive identical voltage steps would then interpret this as the beginning of a horizontal line. This method of horizontal line transmission was implemented and tried for a while. Two problems came up, however, that made this scheme unattractive. First, noise in the video would from time to time incorrectly indicate that a point was the beginning of a line and consequently cause a line to be drawn from that point to the next one, or the edge of the screen. 26 Second, the D/A and A/D conversion would introduce a quantization error of one bit. This error can cause the receiver to treat two identical points (meant to indicate the beginning of a horizontal line) as two separate points. This, of course, would cause complete loss of a horizontal line. Although these two phenomena would not occur very often (three to five times per frame) their effect was most objectionable to the eye. Consequently this scheme was abandoned in favor of the last method, known as the video chopping technique. By now it had been observed that the system operated best when only points were transmitted. Errors would still occur, but a small point or points erroneously appearing on the screen were not nearly as objectionable as complete line segments. It was therefore decided to change horizontal line segments into a series of sequential points . Dependent on the spacing of these points, short or long line segments could be transmitted. Very long line segments could still not be transmitted but tilting the picture slightly would take care of that. The chopping of the video is done by a gated multivibrator whose output is a single pulse for input pulses of less than 200ns duration and a series of pulses for inputs of greater than 200ns. A schematic of this circuit is given in Figure 2. 27 3 . RECEIVER 3.1 Receiver Synchronization Synchronization of the transmitter to the camera and within itself was a relatively simple matter. The transmitter being the "master" has its own free running master clock from which all timing pulses are derived. A reasonable amount of care had to be taken to be compatible with the camera and standard broadcast television signals, but all things considered the matter was relatively straight forward. If the receiver was a separate free running system like the transmitter with only a television monitor to control, its complete synchroni- zation would also be straight forward. In order for the receiver to do its proper job, namely decoding the transmitted information, it must be in exact synchronism with the transmitter. That is, it must start a horizontal scan exactly at the same (relative) time that the transmitter starts a horizontal scan. A delay of several scan lines occurs, but synchronization is not lost if the delay is an integral number of scan lines. This means that a signal corresponding to the line repetition rate must be present in both the trans- mitter and receiver. Furthermore if the transmitter detects and transmits a series of points, they must occur in the same relative position in the receiver as in the original picture. This now means that the ^.h^Mhz clock in the receiver must be in step with that of the transmitter. The last thing that must be synchronized is the vertical frame rate. This is furthermore made more difficult by the two to one interlace which requires, odd and even field information. The problem in obtaining this synchronization information lies in the fact that the transmission link between the transmitter and receiver is bandwidth limited. This puts a few restrictions on the reception of horizontal 28 and vertical synchronization information. The synchronization pulses cannot have sharp and well defined edges, but must be nearly sinusoidal in nature. A zero crossing rather than an edge of a pulse is then detected. The main task lies in trying to synchronize the 9.^5Mhz clock. In fact it was considered to be a project in itself, and was undertaken by Edward Carr. The basic scheme for keeping the two 9.^+5Mhz master clocks in synchronization is as follows. The clock in the transmitter becomes the master clock and is crystal controlled for maximum stability. The receiver also has a very stable clock as close to 9.^5Mhz as possible (within a hundred hertz), and it can be varied over a few hundred hertz by a control voltage. The output of this clock is now fed into a divide by 600 counter to produce a series of pulses at the same rate as horizontal scan rate. This pulse train is then compared to the horizontal scan rate of the transmitter. An error voltage is then generated that is proprotional to the difference in horizontal scan rates of the transmitter and the receiver. This error voltage is integrated over several horizontal scan times and used to control the 9.^5Mhz receiver clock. This then corrects for any relative drift of the two clocks and guarantees mutual synchronism. Horizontal and vertical synchronization pulses for the receiver are obtained by checking when the incoming video goes to ground. The transmitter forces the video to ground at horizontal line and vertical field rate. By checking the relative appearance of this ground level, the receiver can generate a complete synchronization signal for the television monitor. Next, let us consider the synchronization for the receiver decoding mechanism. The scheme is quite similar to that of the transmitter; in fact, the same master synchronization logic card is being used. Video decoding is done on a line by line basis just as the encoding scheme is done. There is a subtle difference however. The transmitter goes through two distinctly 29 different systems in its encoding process: first, the thirty-two nine bit counter bank for receiving video information from the camera, and second, the thirty-two nine bit storage registers for transmitting information with a transfer of information taking place from the counters to the registers each horizontal line. The block diagram in Figure 8 shows this clearly. The receiver has two identical banks of storage registers alternately filling one with incoming information while decoding the other for display. This can be seen in the block diagram of Figure 11. A complete set of receiver timing signals is shown in Figure 12. HS indicates the beginning of a new scan line and is used to clear the receiver master synchronization counter. It also initiates the beginning of BW a 13.5us blanking signal. All bookkeeping and timing occurs during this 13.5|is interval and is done by the signals Nl, N2, N3 and 88. Signals Fl and F2 are the signals that alternate the operation of one section of the receiver with the other. Fl and F2 are generated on the bandwidth selector card and are triggered by Nl which also clears the bandwidth selector counter. N2 clears the thirty-two bit shift registers that store the incoming video information from the A/D converter in the sixty-four nine bit storage registers. N3 clears the thirty-two bit shift registers that read out the video information from the sixty-four nine bit storage registers. 88 indicates the end of BW, the horizontal blanking signal, and initiates the comparator readout scheme. The exact routing of all these timing signals can be seen in the detailed receiver block diagram shown in Figure 13. 3.2 Video Decoding The receiver decoding process is similar to the' encoding process of the transmitter in that the processing is done on a horizontal line by line basis. While one line is being received, another is being displayed. The 30 NPUT -* — W a/d CONVERTER 32 9 BIT REGISTERS MASTER CLOCK CONTROL LOGIC 9 BIT COUNTER <■ — ► 7> DIGITAL COMRftRATOR C MONITOR 1 32 9 BIT REGISTERS Figure 11. Receiver Block Diagram 31 -r rz ^ & CO u CO •H o tiD •H S •H EH > •H 0) o 0) K H P-4 J=f X CO CM CO GO 00 M CM U. Lu 32 {> •0 6 = <6 ! X •- d 4££ Be" i — ■ A I l o 8 g g Wftffi Id * Ja -0" sis -0 = Ul nil IB o o r-l u CD > •H t < wo ? 1- z o M o VIOEO CORRE TO AB L OUTF H* u CD 4-> , < 1 H I ? • Eh t3 / ^^ V / \ <■ en [ \ 10 CO V ) < Ul 00 UJ \. >- o UJ o CD •H > 0) \l / 3 3 o o ^»+-*S =a * - ^ uZ iZ 1 IO O *- CJ _ "*" «^ ^ i V > ^ "^T CM H *-4 l\ 1 \ •H 1 1 >s. ? 37 exponential to be within two-tenths of one percent of the final voltage 6.22 time constants must elapse. For the given example of four steps or points, this time is 12.5M-S. The RC time constant for this filter is then determined to be roughly 2us . The cutoff frequency for an RC filter with this time constant is in the neighborhood of 80Khz. This then represents a sizable bandwidth reduction of about 125 "to one. For thirty-two intersections or the maximum capacity of the system, the bandwidth reduction would be about one- eighth of the last figure or about fifteen to one. One should keep in mind that this is the bandwidth reduction for a simple RC filter whose character- istics are far from ideal. An ideal filter with zero phase shift, unity gain and infinite attenuation above its cutoff frequency would be best and would give the highest bandwidth reduction. Let us consider the sampling theorem which states, "if a signal whose highest frequency is W cycles has been sampled at a rate of 2W samples/sec, and the samples are in the form of impulses whose area is proportional to the magnitude of the sample at that instant, the sampled signal may be reconstructed by passing the impulse train through an ideal low-pass filter whose cutoff frequency is ¥ cycles." Now let us assume that each voltage V to V, is an impulse function and a sample of some function f(t) whose highest frequency component is UOKhz. The sample rate is once every 12.5us or 80Khz. If these samples are now passed through an ideal filter with ^OKhz cutoff (one half the sample rate) the resultant output function would still contain all the original information. A subsequent sampling of this waveform would then recover the original voltages V to V, . This then establishes a theoretical upper limit of the bandwidth compression possible. It would be about 250 to one for four points and approximately 30 to one for the maximum capacity of thirty -two points. Ideal filters, however, are difficult to obtain, so we must settle for a bandwidth reduction of somewhat less than the theoretical one. The RC filter as simple as it is, gives a surprisingly good result. In conclusion we can say that the highest bandwidth reduction using ideal filters and impulse functions can be as high as 250 to one for a simple four line drawing. With the more realistic RC filter and more complicated drawings with an average of twenty points of intersection per scan, a band- width compression of 25 to one is more realistic. 39 5. NOISE AND ERROR CONSIDERATIONS The ORBIT system, like any other signal processing system, will suffer from noise and errors that are introduced into the system during various steps of operation. Since the system is hybrid in nature, both digital and analog circuitry is used and each have their own peculiar noise and error properties. If one can eliminate or bypass either the digital or the analog processing in the complete system and still observe the operation of the systems, then one would observe which errors are due to noise in the digital systems and which errors are due to the noise in the analog processing of the system. It turns out that such an operation was designed into the system. It was not done to facilitate an error analysis, but to facilitate the troubleshooting of the digital system. By providing special known digital video signals to the processor, one could trace their encoding and decoding process with relative ease, since their behavior was well known and predictable, A picture which is rather random in nature (from a signal processing point) is difficult to trace through the system. The three main systems which have analog signals associated with them are the video to logic converter, the digital to analog converter and the analog to digital converter. The logic to video converter in the receiver is also a hybrid device that has an analog output, but this output is such that it remains for all practical purposes a digital signal. We can therefore eliminate this element from our discussion. The video to logic converter can be eliminated by substituting a known digital signal for its output. The most convenient signal to pick was 40 one of the bits from the master synchronization counter. This type of video signal produces a series of vertical lines on the monitor, whose spacing is a function of the bit chosen from the master synchronization counter. The digital to analog and the analog to digital converter can be eliminated by taking the digital input lines to the D/A converter and connecting them directly to the output points of the A/D converter. In this way the system can be operated in an entirely digital mode which not only facilitates trouble- shooting, but shows where errors occur in the system and if their origin is digital or analog. As one would expect, the digital system showed very high noise immunity and produced no noticable error in the entire encoding or decoding process. The TTL line of integrated circuits seems to have exceptional noise immunity. Even when oscilloscope traces would show that certain logic and noise levels could cause an error, no such errors occurred. This is partially due to ground noise being picked up by the scope that did not really exist at the points tested and also due to the conservative noise margin claimed by the manufacturer. The logical one level (ground) has a noise immunity of 2. h, volts. That is to say that the signal must be less than minus 2.4 volts before the logic circuit responds and switches. In the logical zero state (minus five volts) the noise immunity is ,k volts. The signal must be greater than minus 4.6 volts to cause a response in the logic circuits. This high noise immunity level then assures virtually errorless operation of the digital part of the system. The video to logic converter can now be connected, and all observable errors will be due to noise in the video signal and the video to logic converter. The first and most noticable error (if it can be called as such) was the quantizing error in going from an analog to digital signal. The smooth continuous lines on the drawing take on a rather jagged appearance in since the digitizing forces the lines to jump in discrete intervals. This, of course, is unavoidable and as such should not really be called an error. The phenomena that can be called an error is when the digital signal cannot make up its mind and jumps back and forth between one value and another. This phenomena is generally aggravated by the presence of white noise in the video. With a bandwidth of 20Mhz noise on the video signal is quite prevalent. This white noise constitutes about twenty percent of the total video voltage level, and as such contributes random points to the screen. Fortunately since these points do not occur at regular intervals or in great number (five to ten errors per frame) they do not contribute enough visual distraction to merit concern. Increasing the contrast of the picture increases the signal to noise ratio and reduces the number of errors. By far the most prevalent source of errors, and the most objectionable, is the D/A and A/D link. The accuracy of both converters is + — the least significant bit. So even with no noise on the analog signal an error in the least significant bit is expected and was noted. The effect of this error was to make the lines on the monitor fuzzy. Where before we had a relatively smooth curve with regular quantized increments as the line curved, we now have the line made up of points that would jump from their correct position by one bit from time to time. In order to prove that the error was within certain limits, like the least significant bit, the system was returned to an all digital mode. The least significant bit was then disconnected and driven by a noise source. This insured that the least significant bit was always in error. The resultant picture was somewhat worse than the picture sent through the D/A - A/D link. This indicates that the error in going through the analog link is somewhat less than the least significant bit. 1+2 Next let us consider noise on the analog signal. Since the position of the points on the screen becomes a function of the amplitude of the video signal any noise on this signal is very detrimental to the final picture. The accuracy of this voltage at any point must be .2 percent to insure the correct position of a point. The signal to noise ratio must therefore be kept in excess of 27db, a sizeable figure. Fortunately the bandwidth required for the transmission is low, so all high frequency noise (like car ignition) would not affect the picture quality. It is interesting to note that any constant error (DC) added to the signal will merely cause a displacement of the picture and will not distract from its visual appearance. The fact that high and low frequency noise have a minimal effect on the system may be due to the fact that the encoding process effectively averages high and low frequency information to obtain an overall lower bandwidth requirement. The last possible source of error is that caused by the filter. Again, an accuracy of .2 percent must be maintained. For the RC filter no difficulty arises as long as the time constant is not greater than 1/6.22 times the time slot allowed for that mode of transmission. If it is, a cummulative error will occur that will distort the right hand edge of the picture the most. The reason for this is that transmitted voltage has not yet reached its final value before it is incremented again. Consequently each successive step will be lower in value than it should be and will add its own error to the next step. The situation is further aggravated if the next line is much different than the previous one because the error is a function of the amplitudes of the step function. This again >would cause different errors to occur at different points which is most objectionable. If the time constant of the RC filter is decreased, the quality of the picture remains unaffected. h3 In conclusion we can say that the main source of error comes from the analog circuitry in the system. The analog transmission link is the worst offender requiring a 27db signal to noise ratio. The digital portion of the system is virtually error free suggesting perhaps that transmission should also be done in some digital form. 6. CIRCUITS 6.1 Dual Nine Bit Register -- 130A and Nine Bit Register -- 1U7 Both cards are essentially used as storage type registers for parallel nine bit digital information. The operation of each register card is identical. The reason for a dual and single nine bit register is the mode of operation in which each is used differs and the number of input pins which are needed on each card are different. In the receiver the input of each bit Q to Qo is tied together on all registers, while in the transmitter each input Q to Qq must be available separately on all registers. Due to the pin limitations on a printed circuit card a single nine bit register had to be built for the transmitter while a dual register could be built for the receiver. The circuits of each card are shown in Figure 15 and Figure l6. Figure 17 shows the operation of a single bit in the register. The digital signal Q to be stored is applied to D. When a positive transition takes place at CL the logical level at D is copied into Q and its inverse into Q. A negative transition has no effect on the operation of the storage element. The output Q is now indpendent of D and will not change until CL goes positive again, at which point the logical level at D is copied again. The preset (P) and clear (c) options on the storage element are not used during the operation of the circuit. Clear is permanently wired to a logical one. Preset is available for test purposes but not normally used. The inverted output Q is brought to a test point where the content of the storage element can be checked at any time, but is also not normally used. The output Q, of the storage element is connected to one input of a two input nand gate. The other input of the nand gate is used to control its output. When G is a logical zero the output of the nand gate (Q Q G) is always a logical one. J+5 o UJ 00 en _J Q UJ Lu I u | | " | u 1 ' ' I g I D | I g I o I ' bI'bI ail iB — -F= L - E »J OD E * = 0) +3 CO •H bD -p •H PQ cu •H H CO p no (2 lall E S GQ E r? En F.E. NINE BIT REGISTER- 147 0-if Q > ■0^3- B-i & °:> 1^6 &T: EHf rKD J- J 13 1 0- Q,>- CL Hi> L 3 - L — — J» ® EHf °i 4L r 00 [IHr IS r* 2 HH n> 0- HD _l t^D °>>7 1 • 101 _ k 121 L6L- i-.J» © EK^i °«>M- 0" CL 7 l r> 5 0- 0- 13 - 7 0-s ^8 [FJ- r® 8Q -»o,c B— 2 C -» OjC Q 4 C • O.C j ~ «9' Q.C Q 7 C 3 T "• O.C a> ai>t bi> O PRESET V -5TO- 5« >r GND> GNDO- 10O- 12 o- 13 ^ 14 O- 15 o- 17 O- 18 O-; 8Q I -E -0 ■Yl -0 ■0 !^_t "'" 7 0N ALL lC '* ® PIN 14 ON ALL IC'i .STORAGE /'ELEMENT CL A CL 3> A G OUTPUT GATE * GQ"o Figure 17. Basic Circuit of Digital Storage Register When G is a logical one the output of the nand is the inverted form of the stored logical level stored in Q. The reason the inverted output is wanted is to facilitate the use of nand elements in "oring" the output of many of these registers together. 6.2 Thirty-Two Bit Shift Register (Card 1 -- 131 and Card 2 -- 132) These two cards, shown in Figures 18 and 19, combine to form a thirty-two bit (or position) shift register which will successively shift a logical one level from bit one to bit thirty-two upon the application of thirty-two successive negative clock pulses. The circuit consists of thirty- two storage type registers which will copy the input at D (see Figures 18 and 19) when a positive transition takes place at CL. The output Q of each element is connected to the input D of the next element, so when a positive transition at CL takes place at each storage element it copies the content of F.E. 32-BIT SHIFT REGISTER (CARD l) -131 48 P ARTS LIST: 1 JK FLIP-FLOP SN7470N 8 DUAL D-TYPE EDGE TRIGGERED FLIP-FLOPS SN7474N Figure 18. Thirty -Two Bit Shift Register (Card l) ^9 F. E. 32-BIT SHIFT REGISTER (CARD 2) -132 -C28 R30 8 DUAL O-TYPE EDGE TRIGGERED FLIP-FLOPS SN7474N 1 TRIPLE 3 INPUT NANO GATE SN7010N , 2 DUAL 4 INPUT NANO BUFFER SN7440N Figure 19. Thirty-Two Bit Shift Register (Card 2) each preceeding storage element. A clear signal to C on all storage element puts a logical zero level into all Q, outputs, and a logical one into the Q output of a JTK flip-flop whose Q, output is connected to the D input of the first storage element. As the first clock pulse is applied to all elements, only the first one copies a logical one from the - ©- 0~ °o30A 5— Q 30B 10 Q.30A ®- -* Q^OB — 2 3OB OjlO j- Q,30A 0,10 j-* 0,30 A Q 4 30B Q«10 Q 5 30A ■ 0,308 9 DUAL 4 INPUT NAND BUFFERS SN7440N 3 QUAD 2 INPUT NAND GATE SN7400N Figure 20. Nine Bit Buffer input nand function. Card 1U3 may be (and is) used by itself as a thirty-two input nand if the four extension inputs (A, B, C, D on Figure 21) are tied to a logical one. The extender card, shown in Figure 22, contains the equivalent of four eight -input and gates, and can be used to extend the input range of the first card to kO, kQ, 56 or 6k inputs. The boolean description of the card is as follows. In the system, the cards are not actually used as a (Q x - Q 8 )(Q 9 - Q l6 ) . • • (Q 59 - % k ) = \VS • • . Q 6k nand function but are used as a sixty-four input or function. This can be done by using the inverted logic levels at the input and applying DeMorgan ' s theorem: Q X Q 2 Q 3 . . . Q n = Q 1 v Q 2 v Q 3 . . . v Q r W 3 ' * * Q n = \ - % - S ' * ' - Q n Because there are three levels of logic the delay of the entire nand gate is equivalent to three TTL delays. 6.5 Nine Bit Counter -- ±k6 This counter, shown in Figure 23, is capable of counting clock pulses at a 20Mhz rate. The counter is of the synchronous variety and consequently has no delay from stage to stage due to a "carry" condition. Both true and inverted outputs of all bits are available. The clock can be gated on or off by applying a logical one or zero on pin P respectively. Clear is independent of the clock, since the clear signal automatically gates off the clock. The counter stops counting and resets to zero as the clear signal goes RE. 32 INPUT NAND-143 53 i v^ 2 V 3> •>^ 5 V 6 V 7 V 8V4 9 V ioV 1 nV 1 >2V' 13>i 15 V* 16 V> 17 V 18 > 19 v 20 >-£. 2lV 22>-£-- 23 V 24 > 25 V 26 >-k| 2?> 28>- 29 V 30 >- 31>~4 32> 111 121 IE _i E J 2E _ 3E J ®— i ®_£ (D^ 1 G>- 6Q aV sV cV oV 5E t* 1-32ABCD ®" PIN 7 ON ALL IC't ®- 2.2 PIN 14 ON ALL IC't if J^ - -fe0 &&. u ¥ >j=0 i i i i i M3 S =^0 r : r^3 Gd< e^K s >feH ^ 3: ©=^: S ^0 S K3 iS5S£ ©^ ®- H=0 -0 >U3 i i i H3 i— -► |C £2 r: z z z z -31? tft •-• ■-« «-* E i a ia ^J n M ~i r O I M >£ K s « ^ V * « * 2 - 2 "■ 5 «* (o lis 2 '** © d © i "q" 1 „ • ; r ji «) Z O 1_> i__ __ (Si Kl s •> r» * G ) Z s ~ ? j? Q. a a A A > *- (St s. / v o o o Z Z o o -p •H PQ input on the and gate for each J and K input can be used to expand its input capabilities by using it in conjunction with a separate nand gate. Also it can sense the 57 the inverted output of a previous stage so that the true output will not be ' loaded too much by the subsequent stages. 6.6 Counter Extender and Decoder -- 219 This circuit, shown in Figure 24, is used to extend the nine bit counter shown in Figure 2 3 to a ten bit counter. Its operation is identical to all the stages of the nine bit counter. The J and K inputs have the logical and of Q Q to Q g of all previous stages tied to them, hence it will change state with every 2 9 clock pulse. The CLOCT and CLEAR signals must also be obtained from the nine bit counter. The circuit also has a decoding network that decodes the count of 300 of the master synchronization counter. This 300 count is used to synchronize the camera. 6.7 Master Synchronization Logic -- 15SA The outputs from this card are five synchronization pulses that determine the greatest part of the synchronization of the system. The card is essentially a decoding network whose inputs come from the ten bit master synchronization counter and the camera. Four of these pulses (HI, N2, N3, 88) are exactly two clock periods, or 212ns, long. The other one (BW) indicates the duration of horizontal blanking (l3.5us). The pulses Nl, N2, N 3 , and 88 occur at counts l6, 3 2, kQ and 88 of the master synchronization counter, w starts at count zero and ends with count 88. Decoding is done with nand gates only. The boolean equivalent of the four narrow pulses as generated on the card is given below in terms of the bits Q Q to Q 9 of the ten bit master synchronization counter. 58 CM I cc UJ Q O O UJ O CC UJ Q Z X UJ rr UJ "J) O o 1° A i .. : j ["&": A A. A I I 4 4 CD ID £ "E A aa A < m u — cvj V in O z z 2 8 o rj T T CO UJ 111 UJ K p p < 4 m .-H + 1 o < UJ Ql < < Z o < (X LU Cl O UJ CO •p H o > LTN H + 1 2 CD in depending on which R R of the input resistances R, -, . . ., -rrr are tied to minus five volts. A complete transfer function would then look as follows: 8 , Vr = V( n?0 J K )] where n is an integer representing the number (or binary bit) of a stage and 6k K is the binary zero or one for that stage n. V equals plus five volts but can be changed by changing the feedback resistance in the operational amplifier, Total conversion time of the digital to analog converter is determined by the speed of the operational amplifier. The Burr-Brown 15 10 amplifier used in this circuit has a large signal frequency response of 1.5Mhz. Operation of each switch for the binary resistance ladder is as follows. If a low voltage is applied to the 2N97& transistor it goes into conduction, saturates and pulls its collector to near ground. This establishes base current in the 2N709 transistor and puts it into saturation. This then clamps the binary weighted resistor to minus five volts as is necessary to have it contribute to the output voltage. When the input to the 2N976 goes to ground its collector gets pulled to minus ten volts. This causes the 2N709 to stop conducting and the binary weighted resistor is no longer tied to minus five volts, seeing an open circuit instead. At this point the collector of the 2N709 should return to ground rapidly, which it will if the resistor tied to it is small and can discharge the collector capacitance rapidly. For larger resistors (5K and higher) the RC time constant is long and it would impair the fast response of the converter. For this reason a 2N976 transistor is used to pull this point to ground actively. As the 2N709 stops conducting, the 2N976" goes into conduction and pulls its collector slightly above ground. The emitter is clamped to plus l.U volts, which puts the collector to about one volt. Since the summing node of the binary weighted resistors is at ground, the 1N91^ diode in series with the resistors becomes back-biased and looks like a very large impedance. In this way the binary weighted resistors get pulled to ground rapidly and still see an open circuit. ■ 65 6 . 10 Clock and Driver -- 169 The basic 9.^-5Mhz clock pulses are generated by this circuit shown in Figure 27. The circuit consists of three sections: a crystal controlled Colpitts oscillator formed by a 2N709 transistor and its bias network, a pulse shaping network, and an output buffer. Feedback in the oscillator is obtained by splitting the capacitor in its tank circuit and feeding the voltage developed across CI back to the emitter of the transistor. CI and C2 are in a ratio of about five to one so that about one fifth of the voltage developed across the tank is fed back to the emitter. Frequency stability is obtained by using a crystal in the feedback path. The pulse shaping network obtains a small portion of the voltage developed in the tank circuit by tapping a few turns into it. Each time the voltage goes negative the 2N976 turns on and supplies a square pulse at its collector. This in turn drives a TTL type buffer whose output is the desired clock signal. An inverted clock signal is also available. 6.11 Sixteen Bit Counter Gate -- 283 This card is used in the transmitter to turn the thirty-two video storage counters off sequentially. Operation of this card is essentially the same as that of the thirty-two bit shift register (Figures 18 and 19). Each stage contains a logical one at the beginning of a cycle. As clock pulses are applied, a logical zero is passed from the first stage to the last, turning a counter off with each clock pulse. If line LV is energized by a logical zero then this particular counter will pass the logical zero to the next two storage elements each time a clock pulse is received. This feature was used for experimental purposes only and is no longer operational in the system. LV is permanently tied to a logical one at this point. Another feature of this 66 CO i— t I (T UJ > a: Q < o o _1 u LU G o CVJ -vw- m u 0) !> •H a T3 £ o CD o 00 or < UJ Li. CO LU O LU Cl U z LU Z> O rH o >o o 0^ LU LU • If) m cr C"- u. OJ h- _i 1— _i ^ CD < $ q & _j bO Ho- or u •H CO o h Ph or o t- _l ■z. LU or co ^s LU CO _i u. Li. ir ( ) Q _i cr _i i^H o < o Li. LU 1- O 67 card is that as many cards as needed can be hooked in series to expand its length. For the transmitter only two cards are used. A schematic diagram of this card is shown in Figure 28. 6.12 Comparator -- 33^ This card, shown in Figure 29, is a nine bit digital comparator and also contains some logic needed in the receiver decoding process. The card consists of nine exclusive or circuits whose inverted outputs are anded together. At the time the card was built, no exclusive or function was available so it had to be built. Two input, two wide and-or-invert elements were used. Each input had to be inverted so that the exclusive or could be formed. Since no nine input and gates are available the nine input and is formed by taking three three-input and gates and anding their output together. The boolean equivalent for the logic function of the card is: CO = (R C o v R Q Co )(R l C l v R 1 C 1 ) ' * ' (R 8 C 8 v R 8 C 8 ) The outputs C01 and C02 are outputs that can be gated on or off by Fl and F2 respectively. Also the logic associated with them allows a narrow pulse (88) to be added to indicate an initial comparison output. This is necessary to start the receiver decoding process. Total delay of the comparator is either four or five TTL delays depending on which of the outputs is used. 6.13 Logic to Video Converter -- 336 This card, shown in Figure 30, takes the zero to minus five volt logic levels of the comparator and converts them to a video level for the television monitor. The output pulses from the comparator are about 106ns in length. For proper display on the television monitor the pulses should be 68 iss hi * til @ B-41> CD Xh & 3>H^> 5> Xh H> 3> ^ o a> 3> -0 a> 3> a 3 „' IS o -p o o -p •H pq CD 0) -P •rH ^>T =0 a>i s !fl> 5> a>i ^> 3> bi ft> -0 ^ a>i a 3>^ a a -a CO CM bO •H issfil 69 o •P o o ON CVJ bO •H p-4 > Q Q Z o z o CD cc < o S CO CC O CO Id CC d < 70 to I- UJ K u 8 8 s S z o o z CO CO cc o K CO CO z < cc CO u o o o -w — In 1 <- 1 (T> L o r 1 1 1 J — * cm «. Q Z o A A A * o CO > "0 AA/V 1 \aX »2 5h OJ -P 14 > c o o o o ■p o o o CD H cu CO •p id a CO PQ CD 5) •H 73 stages (bits) can be selected by gating the nand gates connected to them on (hL, 8L, l6L, 32L). The output of these nand gates is then fed into another four input nand gate, which performs an or function. This way a square wave of 12.5, 6.25, 3.12 and 1.56ns duration can be selected (RO and RO ) . In the receiver it is necessary that these pulses be delayed. This is accomplished with two single shots; the first of which determines the delay and the second determines the width of the final output pulse (RAD) . Furthermore these pulses are needed in two sections of the receiver, but only alternately every other horizontal scan time. A pulse (Nl) is sent to the clock of a JK flip- flop at horizontal line rate which then causes the Q or Q output of the flip- flop to be at a logical one every other line. These Q and Q outputs then control two nand gates which alternately gate the bandwidth selector output to the receiver (FIR and F2R). Nl is also used to clear the counter. Clear must occur while the clock is low. This is guaranteed during proper operation of the counter, since Nl occurs while the clock to the counter is gated off by BW. 6.15 P/A Gate -- U39 In order to send synchronization information to the receiver it is necessary to perform some gating operations on the D/A converter. The output of the D/A converter must be near ground during horizontal and part of vertical blanking. By applying all zeros to the digital input of the D/A converter its output can be pulled to ground. The digital signal is gated on and off with nine two input nand gates. The gating information is determined by the horizontal and vertical drive pulses from the camera. The input to the D/A converter is gated to all zeros during each horizontal blanking interval and during parts of the vertical blanking interval. Depending on the odd or 7k even field either the first or first two horizontal lines during vertical blanking respectively are pulled to ground. The odd or even field information is determined by the two single shots on the card and their associated logic. The exact operation is described in the transmitter synchronization section. Figure 6 shows the complete circuit configuration. 6.l6 Synchronization Converter II -- hk^ Three functions are performed on this card shown in Figure 32. All of them are essentially a conversion of signal levels to interface the camera with the TTL logic in the transmitter. The horizontal drive pulse (zero to minus four volts) is converted to a standard TTL logic level (zero to minus five volts) and made available in its true and inverted form. It is also used to form a narrow (200ns) pulse used in the master synchronization logic card (HS) and a horizontal blanking interval of 15U-S (HB). This is done with two single shots. Both true and inverted signals are available. Next the vertical drive pulse from the camera is converted to a TTL logic level and made available in its true and inverted form (VD, VD) . Both the horizontal and vertical drive pulse conversion is done by a 2N3905 transistor and two resistors as shown in the circuit diagram. Last a synchronization pulse from the camera synchronization counter must be lengthened to 300ns and level shifted to be compatible with the camera's external synchronization input. A single shot is used to lengthen the 50ns pulse. A 2N36"U2 and its bias net- work is used to shift the TTL signal to a ground to plus ten volts signal. The 2N36I42 and 2N3905 transistor combination is used as a complementary emitter follower to drive a 75 ohm cable to the camera. 75 „ o *3 o Z OS 2 : _l 8* ffi m t- ° fc ■-H z > en ffi 100 I I I Ix i r * — ii — +- ?■ « V -"W < r- Hi «» l< o ^ H" ^ A' o Q o l> A A (0 < o + OJ -P U OJ f> G O o a o •H -p CO N •H g CJ CD OJ m fo 16 6.17 Video to Logic Converter II -- kk9 This video to logic converter, shown in Figure 2, differs from an earlier model in that the video is not first differentiated. Using a high contrast video source allows one to eliminate most of the curvature in the video and one can perform a straight threshold detection on the video signal to detect any points of intersection or large areas of black. The video input to the circuit is buffered by a 2N36U2 transistor used as an emitter follower. Its output is fed to a 2N976" transistor which is used as the threshold device. The voltage on the emitter of the 2N97^ is the threshold reference voltage which is supplied by a 2Nl6l3 transistor. The reference voltage is variable from zero to plus 4.5 volts. The output of the 2N976 is then the "logic" video which is blanked by KB during horizontal blanking. The final output to the transmitter is V1D. The circuit as described this far will only detect leading edges of black. For a continuous black level (horizontal lines) one has the option of chopping the video to produce a series of points. This is done with the gated multivibrator shown in the drawing. The 2N97^ and 2N706 transistors are used to gate the multivibrator formed by the two 2N706 transistors on or off. If the input pulse to the gated multivibrator is less than 200ns then it produces a single 150ns output pulse. If the input pulse is greater than 200ns then a series of output pulses of 150ns duration and 150ns spacing are produced. The total number depends on the length of the input pulse. In this way horizontal lines can be approximated by a series of points. The last 2N706 transistor in the circuit is used as a pulse shaper and to drive the TTL nand gate that follows. 77 6.18 A/D Level Shifter The analog to digital converter used in this system has TTL type outputs that range from ground to plus five volts. The ORBIT system has TTL type levels that range from minus five volts to ground. To make the two systems compatible two types of level shifters had to be built. The first level shifter, shown in Figure 33, built around a 2N3905 transistor is used to shift ground to plus five volt TTL levels to ground to minus five volt TTL levels. The other level shifter built around the 2N36U2 transistor will shift minus five volts to ground TTL levels to plus five volts to ground TTL levels. Both circuits also invert the signal levels in a logical sense. A Beckman 805 -V"5 regulator is used to supply the plus five volts needed for the circuits. 6 .19 A/D Converter and Power This card contains the ten bit analog to digital converter needed in the receiver. It is a Varadyne type ADC-H-10B capable of making a ten bit conversion every microsecond. The least significant or tenth bit is not used. The converter uses three voltages that are not available in the system. Plus and minus fifteen and plus five volts are locally generated by three Beckman voltage regulators from plus and minus twenty-five and plus ten volts respectively. Circuit configuration of the card is shown in Figure 3^. u c/> > in + O if) CVJ to ro > + cvi 78 u. ~-\H> 4-S IB Z ,0 HN O c/) z o CD tr < o IT) CO or o I- c/> c/> UJ cr _i _i < -p •H (D > 0) 0O on > in pq 4. CVJ cvi H I? > IT) I Q 2 O uiinOSOOOOOOOOO 79 n Y > w 2 3a O tt -4 -< a 2 u a CO u •p i o o o a > z m o CM 1 o + 8o 7. SUMMARY ORBIT is a real time television bandwidth compression system that operates on a special class of black on white line drawings. It is compatible with standard 525 line broadcast television. Bandwidth compression is realized by redistributing areas with much information over areas with very little or no information. This effectively averages high bandwidth signals with low bandwidth signals to form an overall lower bandwidth signal. The bandwidth compression ratio is a function of the complexity or information content of a particular drawing. An average bandwidth compression ratio of twenty-five to one can be realized. Virtually all noise and errors occur in the analog portion of the transmission link, with the digital section only contributing a quantization error. A digital transmission link would probably have higher noise immunity than the present analog link. All digital processing was done with Texas Instrument TTL integrated circuits whose performance has been exceptionally reliable. 81 LIST OF REFERENCES 1. Ash, Robert. Information Theory . New York: John Wiley and Sons, 1965. 2. Beckman, Petr. Probability in Communication Engineering . New York: Harcourt, Bruce and World, Inc., 1967. 3. Cheng, David K. Analysis of Linear Systems . Reading, Massachusetts: Addi s on-We sley Publishing Co., I96I. k. Fink, D. G. Television Engineering . New York: McGraw-Hill Book Co., 1952. 5. Foy, W. H. "Entropy of Simple Line Drawings," IEEE Transactions on Information , Vol. IT-10 (April, 196k). 6. Goodall, W. M. "Television by Pulse Code Modulation," Bell Systems Technical Journal , Vol. 30 (January, 1951 )• 7. Hancock, John C. An Introduction to the Principles of Communication Theory . New York: McGraw-Hill Book Co., 196I. 8. Hohn, Franz E. Applied Boolean Algebra . New York: Macmillan Co., 1966. 9o Huang, T. S. "Digital Picture Coding," Proceedings of the National Electronics Conference , 1966. 10. Hurley, R. B. Transistor Logic Circuits . New York: John Wiley and Sons, 1961. 11. Joyce, M. V. and K. K. Clark. Transistor Circuit Analysis . Reading, Massachusetts: Addison Wesley Publishing Co., 1962. 12. Neuhausen, R. G. and L. D. Miller. "Beamlanding Errors and Signal Output Uniformity of Vidicons," Journal of the SMPTE , Vol. 67 (March, 1958). 13. Peterson, A. and E. Gross, Jr. Handbook of Noise Measurement . West Concord, Massachusetts! General Radio Co., 1963. Ik. Schwartz, Seymour. Selected Semiconductor Circuits Handbook . New York: John Wiley and Sons, i960. 15. TTL Integrated Circuits Catalog . Dallas, Texas: Texas Instruments, 1969. 16. Westman, H. P., ed. Reference Data for Radio Engineers . New York: ITT Corp., 196k. 82 VITA Peter Ernst Rudolf Oberbeck was born on January 5> 19^2 in Berlin, Germany, and entered the United States in 1956. In 1965 he completed his undergraduate studies at Worcester Polytechnic Institute and graduated with high distinction in Electrical Engineering. He has since worked in the Department of Computer Science at the University of Illinois where he receive his Masters in Electrical Engineering in 19&7* He is a member of Eta Kappa Hu and Sigma Xi. In AEC-427 I (6/68) =CM 3201 U.S. ATOMIC ENERGY COMMISSION UNIVERSITY-TYPE CONTRACTOR'S RECOMMENDATION FOR DISPOSITION OF SCIENTIFIC AND TECHNICAL DOCUMENT ( 5m Instruction* on Rtrvrm Sid* ) AEC REPORT NO. COO-1469-0178 2. TITLE ORBIT - ONLINE REDUCED BANDWIDTH INFORMATION TRANSMISSION TYPE OF DOCUMENT (Check one): PM a. Scientific and technical report I I b. Conference paper not to be published in a journal: Title of conference Date of conference Exact location of conference. Sponsoring organization □ c. Other (Specify) RECOMMENDED ANNOUNCEMENT AND DISTRIBUTION (Check one): Kl a. AEC's normal announcement and distribution procedures may be followed. ~2 b. Make available only within AEC and to AEC contractors and other U.S. Government agencies and their contractors. "2 c. Make no announcement or distrubution. REASON FOR RECOMMENDED RESTRICTIONS: SUBMITTED BY: NAME AND POSITION (Please print or type) Peter Ernst Rudolf Oberbeck Research Assistant Organization Department of Computer Science University of Illinois Urbana, Illinois 6l801 FOR AEC USE ONLY AEC CONTRACT ADMINISTRATOR'S COMMENTS, IF ANY, ON ABOVE ANNOUNCEMENT AND DISTRIBUTION RECOMMENDATION: PATENT CLEARANCE: □ a. AEC patent clearance has been granted by responsible AEC patent group. LJ b. Report has been sent to responsible AEC patent group for clearance. I I c. Patent clearance not required. APR 7 1 9 ? t