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LIBRARY OF THE 
 
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 UNIVERSITY OF ILLINOIS LIBRARY AT URBANA-CHAMPAIGN 
 
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Digitized by the Internet Archive 
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£fz- Report No. UIUCDCS-R-75-692 
 
 hu^ti 
 
 A FOUR FUNCTION CALCULATOR 
 
 by 
 
 MARY JANE IRWIN 
 
 January 1975 
 
 DEPARTMENT OF COMPUTER SCIENCE 
 
 UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN • URBANA, ILLINOIS 
 
Report No. UIUCDCS-R-75-692 
 
 A FOUR FUNCTION CALCULATOR 
 
 by 
 
 MARY JANE IRWIN 
 B.S., Memphis State University, 1970 
 
 Submitted in partial fulfillment of the requirements for the degree 
 of Master of Science in Computer Science in the Graduate College of the 
 University of Illinois at Urbana-Champaign, and supported in part by 
 National Science Foundation Grant No. GJ 38204. 
 
 January 1975 
 
Ill 
 
 ACKNOWLEDGMENT 
 
 The author would like to express her sincere gratitude to 
 her thesis adviser, Professor James E. Robertson, for his guidance, 
 aid, and encouragement in the preparation of this paper. 
 
 The author also wishes to thank Professor Michael Faiman for 
 allowing the use of his EXCEL equipment for the implementation of the 
 test machine. 
 
 Finally, the author is grateful to her husband, Vernon Irwin, 
 and son, John, without whose love, support, and constant encouragement 
 this paper might have never been completed. 
 
IV 
 
 TABLE OF CONTENTS 
 
 ACKNOWLEDGMENT iii 
 
 1. INTRODUCTION. . . . ' 1 
 
 2. DESCRIPTION OF THE ALGORITHMS . k 
 
 2.1. Division 5 
 
 2.2. Multiplication 7 
 
 2.3. Natural Logarithm 10 
 
 2.k. Exponential Ik 
 
 3. DETAILS OF THE LOGIC DESIGN 19 
 
 3.1. Control Design 19 
 
 3.2. Register Bank Layout 25 
 
 3.3. Register Bank 1 25 
 
 3.1+. Register Bank II 32 
 
 h. CONCLUSIONS 35 
 
 4.1. Hardware Requirements 35 
 
 k.2. Speed Achieved 36 
 
 4.3. Limitations and Extensions 37 
 
 APPENDIX kl 
 
 A.l. Operation of the Test Machine kl 
 
 A. 2. Some Machine Examples k2 
 
 LIST OF REFERENCES 52 
 
1 . INTRODUCTION 
 
 In 1970, Bruce Gene DeLugish published a Ph.D. thesis entitled 
 "A Class of Algorithms for Automatic Evaluation of Certain Elementary- 
 Functions in a Binary Computer." He had developed algorithms whereby, 
 using a continued product notation, a large class of functions could be 
 computed on essentially the same hardware. As far as is known, his theory 
 has remained just that, theory. The final statement of his thesis is a 
 challenge for someone to implement his algorithms in an actual working 
 machine. On a limited scale, the author has attempted to do that. Within 
 these limitations, the machine is built and working on Computer Science 
 265, Logic Laboratory, equipment. Except for two barrel shifters, the 
 only hardware used was that available on this equipment. A RAM was used 
 in place of the specified ROM merely for the reasons of expense and 
 delivery time . 
 
 The calculator performs four functions. 
 
 DIVISION 
 MULTIPLICATION 
 LOGARITHMS 
 EXPONENTIATION 
 
 It is the purpose of this paper to explain the derivation of the algorithms 
 
 used here and to explain in detail the logic design employed. A layout 
 
 of the card arrangement in the two EXCEL boxes is shown in Figure 1. 
 
 Figure 2 shows the functional layout of the cards. 
 
CO 
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 Figure 1. Card Layout 
 
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 Figure 2 . Functional Layout 
 
2. DESCRIPTION OF THE ALGORITHMS 
 
 The fundamental technique used in developing the algorithms 
 is the "normalization" of a given operand. This is accomplished by 
 means of a continued product or continued summation with easily generated 
 terms. The procedure consists of the following operations: (l) choice 
 of an appropriate function of a given operand to he normalized; (2) 
 approximation of that function by a continued product or continued sum 
 whose terms are easily chosen; (3) utilization of those terms to form 
 the desired function; (h) determination of a rule for selecting those 
 terms; and (5) scaling of the operand so that the selection rule is the 
 same for every step in the recursion. 
 
 When analyzing each of the following algorithms, several other 
 generalizations may also be made. In every case, the recursion formulas 
 operate on the fractional part of each operand 
 
 X - x • 2 
 
 Y = y • 2^ 
 
 a 
 
 C£, j3 integers 
 
 where 
 
 x e [1/2, 1) 
 y e [1/2, 1) , 
 
 since the exponents present no problem. It is assumed that all answers 
 and operands lie within machine range . 
 
Both continued product or sum forms, that of the operand and 
 that of the function, may be formed simultaneously and independently. 
 Also, it can be proven in each case (see DeLugish's paper) that the 
 algorithms produce M correct function bits in (M + l) steps, with the 
 error being less than 2 ^ ' neglecting round-off. 
 
 2 .1. Division 
 
 To form the recursive formulas for division, multiply both 
 the divisor and the dividend by a sequence of non-zero constants (d.} 
 chosen so that the resulting divisor goes to unity. 
 
 M 
 y n d. 
 
 . i M 
 
 TT A 1=0 
 
 x il dj_ 
 1=0 
 
 M 
 
 n 
 
 i=0 
 
 dj_ = 1 
 
 It is easily seen that 
 
 x. n = x A II d • -• x, d, , x_ = x 
 k+1 . n i k k '0 
 i=0 
 
 q k + i = q o . n n d i = Vk > ^o = y 
 
 1=0 
 
-k 
 
 where d, = 1 + S, 2 , 1 < k < M. The initial multiplier d^ is chosen 
 k k — — 
 
 in a special way as described later. 
 
 It is necessary to represent the divisor x by 
 
 K. 
 
 and scale down by a factor of two in order to bound | u |< 1 throughout 
 the entire procedure. Now u is the operand upon which the actual 
 normalization is performed. As u goes to zero, x goes to one. And 
 d is now d = 1 + S 2~^ . Using the selection rules 
 
 K K K 
 
 1 if u k < - 3/8 
 
 S, = 4 otherwise 
 k 
 
 1 if u k > + 3/8 
 
 maintains u, as u, < 1 f or k = 1, .... M and each u, can be represented 
 
 k ' k 1 ' ' k 
 
 with only a sign bit to the left of the binary point . 
 
 Upon expansion, the recursion formulas necessary to implement 
 division become 
 
 \ + i ■ 2 \ + \ + s k \ 2 " k 
 %* -\ + \ \ 2 " (k+1) • 
 
 With the selection rules chosen, the probability of S being zero is 2/3 
 and the shift average is 3*00. This holds true for all of the algorithms 
 Note that when S, = no addition is performed in either formula for 
 recursion k. 
 
The initial multiplier d must be chosen so that x = x d 
 lies in a range symmetric about unity. This can be accomplished by setting 
 
 d o = 
 
 2 if 1/2 < |xj < 3/k 
 
 - ' 
 
 l if 3/h < |x.| < l . 
 
 - ' o 
 
 Then, 
 
 x i = x o d o 
 
 * x o " x 
 
 \ - 2 ( x o d o - 1} 
 
 q i = % d o 
 
 % = y 
 
 Having indicated an initialization step, the algorithm for 
 division is completely specified. A block diagram indicating the flow 
 of information is shown in Figure 3- 
 
 2 .2 . Multiplication 
 
 To form the recursive formulas for multiplication, use the 
 
 additive scheme 
 
 M M 
 p = yx = y (x - Z m. + E m. ) 
 
 T 
 
 i=0 i=0 
 
 where 
 
 M 
 x - Z m. = 
 i=0 x 
 
 and 
 
 M 
 P = y Z m 
 i=0 
 
U kM (S k *0) 
 
 FULL ADDER 
 
 U k 2" k A t 2U * + 
 
 S k 
 
 SHIFTING 
 NETWORK 
 
 s k u k 
 
 COMPLEMENTING 
 CIRCUIT 
 
 TT 
 
 (S k =0) 
 
 ONE-BIT 
 SHIFTER 
 
 REGISTER 
 U k 
 
 q k+1 (S k *0) 
 I 
 
 s k <U 2 
 
 
 
 
 FULL ADDER 
 
 -(k + l)' 
 
 i 
 
 N 
 
 
 
 SHIFTING 
 NETWORK 
 
 k + l 
 
 T ll 
 
 S k Qk 
 
 COMPLEMENTING 
 CIRCUIT 
 
 S k 
 
 n 
 
 i -i 
 
 i I 
 
 MINI- ADDER I 
 I I 
 
 I J 
 
 r 
 
 i 
 i 
 i 
 
 L. 
 
 I 
 
 i 
 
 ONE-BIT 
 SHIFTER | 
 
 I 
 
 (S k *0) 
 
 (S k =0) 
 
 REGISTER 
 
 T 
 
 Figure 3« Block Diagram for Division 
 
Here the operand is being forced to zero rather than unity. It is seen 
 that 
 
 k-1 
 
 x, - = X-. - Z m. - m, = x. - m, , x_= x 
 
 k+1 ._ 1 k k k ' 
 
 k-1 
 
 P k+1 = y .^ m i + y.m k =p k + ym k , p = 
 
 1=0 
 
 -k 
 where m, = 1/2 S, 2 , 1 < k < M. Again, the initial multiplier m^ is 
 k ' k ' — — 
 
 chosen in a special way 
 
 Lr 
 
 By letting u, =2 x, , u < 1 and the recursion formulas 
 j ° k k' ' k 1 
 
 become 
 
 U k+1 = 2u k " S k 
 
 P k+1 = P k + S k ^ 
 
 -(k+1) 
 
 where the selection rule for S, is 
 
 k 
 
 1 if u fe < -3/8 
 
 S = / otherwise 
 
 1 if u. > +3/8 . 
 
 In multiplication, an extra register is required to hold the original 
 multiplicand throughout the procedure . 
 
10 
 The initial multiplier m n is chosen so that x, = x~ - m lies 
 in a range symmetric about zero. The choice of 
 
 1/2 if 1/2 < |xj < l/k 
 
 m Q = < 
 
 - '~0 
 
 l if 3/k < |x Q | < l 
 
 does this and the initialization equations are 
 
 x i = x o " m o ' x o = x 
 
 ^ = 2 (x Q - m Q ) 
 
 P l = P + ^0 ' P = ° 
 
 The algorithm for multiplication is now completely specified. 
 A block diagram indicating the flow of information is shown in Figure h. 
 
 2.3- Natural Logarithm 
 
 As in the division algorithm, the recursive formulas for natural 
 logarithm are formed by multiplying the operand x by a sequence of constants 
 {Jc.} while dividing x by the same continued product. 
 
 M 
 
 x n &. 
 
 i*0 X 
 x = 
 
 M 
 
 n i. 
 i=o x 
 
 where & = 1 + S. 2 -(i , 1 < k < M, and i_ = d_, the same constant 
 k k * — — ' 0' 
 
 as in division. Now, if 
 
P k+1 (S k *0) 
 
 11 
 
 I 
 
 
 1 
 
 FULL 
 
 1 
 
 1 
 
 1 
 
 ADDER I 
 1 
 
 J 
 
 FULL ADDER 
 
 
 
 Pk 
 
 : 
 
 S k Y2 
 
 (k + 1) 
 
 
 
 1 
 
 1 
 1 
 1 
 
 1 
 
 i 
 i 
 
 1 
 1 
 
 1 
 
 
 
 
 1 " 1 
 
 SHIFTING 
 NETWORK 
 
 L _ 
 
 
 SHIFTING 
 NETWORK 
 
 
 
 K+1 1 's h Y 
 
 
 
 i COMPLEMENTING 
 
 CIRCUIT 
 
 1 
 
 L_ J 
 
 
 COMPLEMENTING 
 CIRCUIT 
 
 
 U k+1 (S k *0) 
 
 s 
 
 < 
 
 ' 1 
 
 1 
 
 
 
 
 T 
 
 
 
 
 
 
 
 MINI- ADDER 
 
 
 1 1 
 
 1 1 
 I MINI-ADDER i 
 1 1 
 1 1 
 
 r ~1 
 
 ONE-BIT 
 
 SHIFTER 
 
 | — j 
 
 
 s* 
 
 f J^s k *o 
 
 
 ,=0) 
 
 
 
 Y 
 
 
 
 
 
 ONE-BIT 
 SHIFTER 
 
 
 
 
 / 
 
 i 
 
 
 (S k ^0) y^ (S k =0) 
 
 
 
 
 
 
 Y 
 
 
 
 
 
 
 REGISTER 
 
 
 
 REGISTER 
 Pk 
 
 
 
 REGISTL^ 
 Y 
 
 
 i 
 
 \ 
 
 
 
 
 1 
 
 i 
 
 
 
 
 
 — 1 
 
 Figure k. Block Diagram for Multiplication 
 
12 
 
 M M 
 
 In x = In (x H I.) -In (nl) 
 i=0 i=0 x 
 
 M M 
 
 = In (x n *.) + Z (-In £ ) 
 
 1=0 x i=0 
 
 where 
 
 when 
 
 M 
 
 In (x n i. ) = 
 i=0 
 
 M 
 
 x n 4. = l , 
 i=o x 
 
 then, 
 
 M 
 
 In x = Z (-In I.) 
 l 
 1=0 
 
 !t can be seen that 
 
 k+l . . i k k ' 
 i=0 
 
 1=0 
 
 = L k + (-in f k ) , L Q = 
 
 The precomputed values of {-In £ }, k = 1, . .., M must be stored in a 
 read-only memory. 
 
 By representing x by 
 
 K. 
 
13 
 
 so that I u, | < 1, the selection rules are 
 
 1 if u, < - 3/8 
 
 S, = s otherwise 
 k 
 
 1 if u k > + 3/8 . 
 
 As u, goes to zero, x, goes to one as desired. The recursion formula 
 k k 
 
 for u is identical to that for division, namely 
 
 K. 
 
 \+i = 2 \ + s k + s k\ 2 
 
 The other recursion relation is a continued summation of the set of 
 stored constants. 
 
 K^ = K + Mn d + S t 2^ k+l) )] 
 
 k+l " "k 
 
 The initialization process is also identical to that of division 
 
 That is 
 
 4) - d o - 
 
 2 if 1/2 < x Q < 3/h 
 1 if 3/k < x Q < 1 
 
 and 
 
Ik 
 
 x i - x o £ o ' x o " x 
 
 \ - 2 < x o l o - 1} 
 
 L = -In I , -In 1 = 
 
 - In 2 = -0.693 • 
 
 The algorithm for natural logarithm is now completely specified. 
 A block diagram indicating the flow of information is shown in Figure 5. 
 
 2 .k. Exponential 
 
 To form the recursion formulas for exponentiation apply the 
 dual of the procedure used in natural logarithm. Let 
 
 M M 
 
 x = x - In ( K e . ) + In ( II e . ) 
 i=0 x i=0 x 
 
 where e = 1 + S. 2~( k+1 > } 1 < k < M. Then 
 
 K K. — ~~ 
 
 M M 
 
 (x - Z In e. ) In ( II e. ) 
 
 x i=0 i=0 
 
 e = e • e 
 
 M 
 (x + E -In e. ) 
 
 = e 1 "° .(He.). 
 
 i=0 x 
 
 By choosing the multiplier constants so that 
 
 M 
 x + Z (-In e. ) = , 
 i=0 X 
 
 then 
 
15 
 
 
 u 
 
 k + 1 
 t 
 
 (S k 
 
 i 
 
 #0) 
 
 
 
 FULL ADDER 
 
 
 s 
 
 i 
 <U k 2 _k 
 
 ' 
 
 2U k + 
 
 Sk 
 
 
 
 
 
 
 SHIFTING 
 NETWORK 
 
 
 
 k 
 
 _J ' 
 
 1 
 SkU k 
 
 
 
 
 COMPLEMENTING 
 CIRCUIT 
 
 
 
 s k 
 
 f \ 
 
 ' 
 
 
 
 
 
 
 
 
 
 
 
 
 
 MINI-ADDER 
 
 
 Sk 
 
 _3 
 
 ' 
 
 k(S k #0 
 
 ' (s k 
 
 = 0) 
 
 
 
 / 
 
 
 
 
 ONE -BIT 
 SHIFTER 
 
 
 
 j 
 
 1 
 
 
 
 
 r 
 
 
 REGISTER 
 
 u k 
 
 
 
 
 
 I 
 
 i 
 
 
 
 L k+1 (S k *0) 
 
 A 
 
 FULL ADDER 
 
 n 
 
 i 1 
 
 SHIFTING 
 NETWORK | 
 
 L J 
 
 1 T 
 
 j COMPLEMENTING ] 
 
 CIRCUIT 
 
 I 1 
 
 I I 
 
 I MINI-ADDER • 
 I I 
 
 I 1 
 
 ONE- BIT 
 SHIFTER 
 
 ± 
 
 REGISTER 
 
 READ ONLY 
 MEMORY 
 
 TT 
 
 k+1 S„ 
 
 .J 
 
 Figure 5 . Block Diagram for Logarithm 
 
M 
 e X = n e. 
 i=0 ' 
 
 16 
 
 It is seen that 
 
 where 
 
 \+l 
 
 x + Z (-In e ) 
 i=0 
 
 x = x 
 
 = x R + (-in e ) 
 
 k 
 
 E. , = II e. 
 k+1 i=0 X 
 
 = E. + S. E, 2 
 k k k 
 
 (k+i: 
 
 > E o =1 
 
 1 if x, < - 3/8 
 
 S. = C otherwise 
 
 1 if x > + 3/8 
 
 k i 
 
 By making the transformation u = 2 x , so that |u, | < 1, 
 
 k k k 
 
 k = 1, ..., M, the recursion formulas become 
 
 U k+1 = 2 [u k + ^ (~ ln (1 + S k 2_(k+l) ))^ 
 
 E. ,, = E, + S, E. 2 
 k+1 k k k 
 
 (k+1) 
 
17 
 Initialization of the exponential algorithm is based on the 
 
 analysis of five ranges of x. 
 
 *o fo lne o 
 
 [1/2, In 2) e 1 / 2 1/2 
 
 [lA, 1/2) e 1 ^ 1/U 
 
 [-1/4, lA) 1 
 
 [-1/2, -1/10 e" 1 ^ -1/1+ 
 
 (-In 2, -1/2) e' 1 / 2 -1/2 
 
 Then, 
 
 x i = x o - ln e o 
 
 u i = 2 ( x o " ln e o^ 
 
 E i = e o 
 
 The algorithm for exponentiation is completely specified. A 
 block diagram indicating the flow of information is shown' in Figure 6. 
 
18 
 
 Uk»i(S k #0) 
 
 Ek + i(Sk*0) 
 
 READ-ONLY 
 
 MEMORY 
 
 1 f 
 
 k+i Sl 
 
 k+i 
 
 FULL ADDER 
 
 SHIFTING 
 NETWORK 
 
 COMPLEMENTING 
 CIRCUIT 
 
 I 1 
 
 I I 
 
 I MINI-ADDER | 
 I I 
 
 U J 
 
 S k E k 2 
 
 -lk*i) 
 
 FULL ADDER 
 
 i n 
 
 SHIFTING 
 NETWORK 
 
 k + 1 
 
 Sk^k 
 
 COMPLEMENTING 
 CIRCUIT 
 
 1 1 
 
 I I 
 
 I MINI-ADDER I 
 I I 
 
 1 
 
 
 
 ONE-BIT 
 SHIFTER 
 
 
 i 
 
 i 
 
 
 REGISTER 
 
 
 i 
 
 i 
 
 
 (S k #0) 
 (S k = 0) 
 
 r 
 
 I 
 
 i 
 
 ONE -BIT 
 SHIFTER 
 
 f 
 
 (S k *C 
 (S k = C 
 
 REGISTER 
 Ek 
 
 Figure 6 . Block Diagram for Exponentiation 
 
 
19 
 
 3- DETAILS OF THE LOGIC DESIGN 
 
 Having analyzed each of the algorithms, the logic design of 
 the test machine may now be examined in detail. The data in the test 
 machine is in the form of one sign "bit to the left of the binary point 
 and seven bits to the right. Recall that both register banks operate 
 simultaneously and independently to form the continued products or sums. 
 
 After each recursion, a new value for S. is determined, defining the 
 
 ' k ' 
 
 new continued product term and enabling the machine to perform the next 
 recursion. This continue until M + 1 (8) steps have occurred or until 
 u = 0. At this point, the value present in the function register is 
 the answer, correct to M places. Examination of the design may be broken 
 down into three sections: the control; register bank I (the u register); 
 and register bank II (the function register). 
 
 3»1. Control Design 
 
 Three control switches are used to designate the operation code. 
 
 CLO CL1 CL2 Operation 
 
 111 Division 
 
 Oil Multiplication 
 
 10 1 Logarithm 
 
 110 Exponentiation 
 
 These control signals gate the proper data through a number of two and 
 three-way selectors (AND-OR gates). See Figures 7 and 8. The op code 
 switches are set prior to entering the initial data and are left set 
 throughout the entire procedure . 
 
20 
 
 DIVISION 
 
 MULTIPLICATION 
 
 d o = < 
 
 2 if 1/2 < |x Q | 
 1 if 3/k < |x Q | 
 
 < 3A ' 
 
 < 1 
 
 m = < 
 
 1/2 if 1/2 < |x Q | < 3 A 
 
 i if 3A S l x l < x 
 
 "l- 
 
 - < x o d o - 1} • 
 
 X Q = X 
 
 u i = 2 ^ X " m (P » 
 
 X Q = X 
 
 *1 = % d o 
 
 q = y 
 
 P l = p o + y m o 
 
 p o = ° 
 
 LOGARITHM 
 
 EXPONENTIATION 
 
 
 *» 
 
 
 *o fo 
 
 lne Q 
 
 ^0 = ' 
 
 2 if 1/2 < x Q < 3/h 
 
 1 if 3/1+ < x_ < 1 
 I J/ - 
 
 M/M) i 
 
 [-1/2,-l/if) e' 1 ^ 
 (-ln2,-l/2) e" 1 / 2 
 
 o 
 
 -1/4 
 -1/2 
 
 u l- 
 
 ■ ( x o ~ ' 
 
 X Q = X 
 
 u i = 2 ( x o " ln e o^ » 
 
 x Q = X 
 
 L l = ■ 
 
 ■ In i 
 
 -ln2 
 
 - In 1=0 
 = -0.693 
 
 E i= e o 
 
 
 Table 1. Initialization Procedures 
 
21 
 
 Before loading the initial data into the main registers, an 
 initialization step must be performed by hand. The step used depends 
 upon the particular algorithm and the range of the operands. Initialization 
 is necessary to force the initial operand to lie in a range symmetric 
 about unity (division, logarithm) or zero (multiplication, exponentiation) . 
 See Table 1 for the specific steps to use. In a practical model, this 
 initialization step would become an integral part of the machine design, 
 whereas in a test machine it only tends to cloud the issue. So, in this 
 test machine initialization is done by hand. A switch, INIT, in conjunc- 
 tion with a clock pulse loads the initial data, via the initialization 
 switches provided, into the registers. INIT is active high and should 
 be on only for this loading. 
 
 The main function register and the u register are loaded after 
 each recursion (and during initialization) by a clock pulse (0-*l) generated 
 by a switch. In this way, each step of the operation may be examined. 
 In a practical application, the clock pulse would be internal and would 
 operate at maximum speed, limited by the ROM access time. 
 
 After loading the registers, a combinational network determines 
 
 S, in a sign and magnitude form, S . and S , based upon the value of u, . 
 k ° ^ ' sign mag' * Tc 
 
 fk 
 
 S . 
 
 sign 
 
 S 
 mag 
 
 
 
 
 
 
 
 +1 
 
 
 
 1 
 
 -1 
 
 1 
 
 1 
 
 d.c. 
 
 1 
 
 
 
22 
 
 
 
 
 
 
 DIVISION 
 
 MULTIPLI- 
 
 
 
 
 
 
 LOGARITHM 
 
 CATION EXPO- 
 
 u o • 
 
 u l 
 
 U 2 
 
 U 3 
 
 RANGE 
 
 
 NENTIATION 
 
 S . 
 sign 
 
 S 
 mag 
 
 s s 
 
 sign mag 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 < + 3/8 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 1 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 1 
 
 > + 3/8 
 
 1 
 
 1 
 
 
 
 1 
 
 
 
 1 
 
 1 
 
 
 
 
 
 
 
 
 
 
 1 
 
 1 
 
 1 
 
 
 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 
 
 1 
 
 
 
 
 
 
 1 
 
 
 
 1 
 
 
 
 < - 3/8 
 
 
 
 1 
 
 1 
 
 1 
 
 1 
 
 
 
 1 
 
 1 
 
 
 
 
 
 
 1 
 
 1 
 
 
 
 
 
 
 
 
 
 
 1 
 
 1 
 
 
 
 1 
 
 
 
 
 
 
 1 
 
 1 
 
 1 
 
 
 
 > - 3/8 
 
 
 
 
 
 
 
 
 
 1 
 
 1 
 
 1 
 
 1 
 
 
 
 
 
 
 S sign = (u O U 2 U 3 v U U 1 } (CL ° CL2) v ( Vl " U U 2 U 3 ) (CL0 CI2) 
 
 mag 
 
 " Vl v Vl v U U 2 U 3 v U U 2 U 3 
 
 Table 2. S. Selection Analysis 
 
23 
 
 Since in every algorithm u, is compared to + 3/8 and zero, the selecti 
 
 procedure need be based only upon the first four bits of u. Table 2 
 
 shows the values of S based upon the values of u . Analysis of this 
 
 k k 
 
 table leads to the following equations for S . and S 
 
 D ^ sign mag 
 
 on 
 
 S sign = (V2 U 3 - U U 1 } ( C L0-CI2) 
 v (uq^ v u q u 2 u 2 ) (CLO * CL2) 
 
 S mag = Vl v Vl ^ V2 U 3 " U 0^^3 
 
 The values of S, are used to gate information and to invert bits in 
 k 
 
 advance of two's complement subtraction. See Figures 7 and 8. 
 
 Two up counters maintain the values of k and k + 1, the present 
 and next recursion steps. Upon initialization, the counters are set to 
 one and two, respectively. The same clock pulse which loads the registers 
 also causes the counters to increment. When the k + 1 counter reaches 
 eight, the operation is complete. The counts control the barrel shifters 
 (a combinational shift network which automatically shifts an operand x 
 number of places, < x < 7) and is used to address the ROM- The ROM 
 contains the values 
 
 - In (1 + S k 2~ (k+l) ) 
 
 for use during logarithm as described in the section on bank II. See 
 Table 3 for these values. 
 
2U 
 
 ROM 
 
 ADDRESS 
 
 S . k2 kl kO 
 sign 
 
 -In (1 + S k 2 _(k+l) ) 
 
 DECIMAL 
 VALUES 
 
 BINARY 
 VALUES 
 
 OOOO 
 1 
 10 
 11 
 10 
 10 1 
 110 
 111 
 10 
 10 1 
 10 10 
 10 11 
 110 
 110 1 
 1110 
 
 1111 
 
 -0.223ll| 
 
 -0.11778 
 -0.06062 
 
 -0.03077 
 
 -0.015^9 
 -0.00777 
 -0.00388 
 
 +0.28768 
 
 +0.13353 
 +0.06U5U 
 
 +0.03175 
 +0.0157*+ 
 +0.00783 
 +0.00390 
 
 1.1100011 
 1.1110001 
 1.1111000 
 
 1.1111100 
 
 1.1121110 
 
 1.1111111 
 0.0000000 
 
 0.0100101 
 0.0010001 
 0.0001000 
 0.0000100 
 0.0000010 
 0.0000001 
 0.0000000 
 
 Table 3. ROM Values 
 
25 
 
 3.2 . Register Bank Layout 
 
 Comparing the block diagrams in Chapter 2 and the bank 
 layouts in Figures 7 and 8, reveals many similarities. In the bank 
 layouts, double lines depict the flow of eight bits of information and 
 single lines depict control signals. Variables near double lines entering 
 selectors indicate the signals which control the gating of those eight 
 bits through the selector. Only one control signal is allowed to be high 
 at any one time for each selector. 
 
 3-3- Register Bank I 
 
 Following is a description of the elements contained in bank I 
 (Figure 7)- It computes the recursive formulas. 
 
 Division 
 Multiplication 
 Logarithm 
 Exponentiation 
 
 Vi = 2 \ + s k + s kV k 
 \ + i = 2 \ - s k 
 
 -k 
 
 u. , _ = 2u, + S, + S. u. 2 
 k+1 k k k k 
 
 k+1 
 
 (k+1) 
 
 2 [^ + 2* (-m (1 + s k 2~ vm; ))] 
 
 The eight bit register holds u which tends toward zero for 
 
 K. 
 
 most operations. It is loaded after each recursion by CP1 (the clock 
 pulse) with the output of a three-way selector. The selector chooses 
 the output of the adder when S, 4 ° a nd INIT = 0, or the output of the 
 
 K. 
 
 initialization switches when INIT = 1, or the output of a one -bit left 
 
 shifter (to form 2u, ) when S, = and INIT = 0. Note that if S, =0 
 
 k' k k 
 
 \+l = 2 \ 
 
26 
 
 FULL ADDER 
 (A + B) 
 
 2-WAY SELECTOR 
 
 BO r ■ 
 
 A 
 
 BO ' 1 
 
 CL2 
 
 77 
 
 B 
 
 2-WAY SELECTOR 
 
 B1...B7 
 
 CL2 IT 
 
 CL0©CL2 
 
 CL2S, 
 
 SHIFTING RIGHT 
 NETWORK 
 
 77 
 
 COMPLEMENTING 
 CIRCUIT 
 
 If 
 
 ONE-BIT LEFT 
 SHIFTER 
 
 It 
 
 o 
 
 DISPLAY 
 
 IX~ 
 
 8-BIT 
 REGISTER 
 
 Su* a INIT 
 
 3-WAY SELECTOR 
 
 — 7T 
 
 77 — 77 
 
 SmacINIT 
 
 INIT 
 
 INITIALIZATION 
 SWITCHES 
 
 CARRY. IN * S SlGN CLO CL2 
 
 PRESET 
 CONSTANTS 
 
 1 [ 
 
 COUNTER 
 
 SsiGN 
 
 CP1 v CP2 
 SO 
 
 S, 
 
 Figure 7 . Register Bank I 
 
27 
 
 
 
 
 
 
 
 CARRY IN « 5 SIGN - CL1 
 
 
 FULL ADDER 
 (A + B) 
 
 
 
 
 
 S$ION 
 
 K 
 
 COUNTER 
 
 A 
 
 B 
 
 
 """ 
 
 ', 
 
 2 -WAY SELECTOR 
 
 
 
 
 
 
 4 
 
 \ 
 
 S. 
 
 
 f 
 
 
 CL1 
 
 CLISmao 
 
 ROM 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 SHIFTIN 
 NETV 
 
 G RIGHT 
 VORK 
 
 — i 
 
 
 
 
 
 
 K + l 
 COUNTER 
 
 
 
 , 
 
 \ 
 
 
 
 
 
 
 
 
 
 
 
 
 COMPLEMENTING 
 CIRCUIT 
 
 
 SsiON 
 
 
 2 -WAY SELECTOR 
 
 
 
 4 
 
 ,' 
 
 . 
 
 
 
 
 CLO 
 
 
 
 CLO 
 
 Y REGISTER 
 SWITCHES 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 DISPLAY 
 
 
 
 ' !' 
 
 , 
 
 
 
 
 
 
 
 
 8-BIT 
 REGISTER 
 
 
 
 CP1 
 
 * >. 
 
 f 
 
 3-WAY SELECTOR 
 
 
 s MM r 
 
 MIT f 
 
 . 
 
 . 
 
 [ Skui 
 
 •TnTt 
 
 
 
 
 
 
 
 
 INIT 
 
 
 
 
 
 INITIALIZATION 
 SWITCHES 
 
 
 Figure 8. Register Bank II 
 
28 
 
 in all cases. There is also a provision to allow the 8-bit register 
 to perform a one-bit left shift in the case of exponentiation. As 
 indicated by the u equation for exponentiation, the addition (S 4 0) 
 
 K K. 
 
 is performed before u is doubled. This is done to keep u, from going 
 out of range. So during exponentiation, after the register is loaded 
 with the output of the adder, SO is set to one and CP2 is pulsed to shift 
 the contents left one bit. This is the only time SO and CP2 are used 
 with SO = CP2 = at all other times. 
 
 The one-bit left shifter and mini-adder are accomplished by 
 
 u o 
 
 <— 
 
 U l 
 
 u i 
 
 *- 
 
 "2 
 
 U 2 
 
 - 
 
 U 3 
 
 u± *- . 
 
 A simple analysis (see Table h) reveals that the mini-adder, one which 
 
 either adds or subtracts one, simply calls for an inversion of the 
 
 sign bit. 
 
 The complementing circuit inverts the output of the register 
 
 depending on whether S is +1 or -1. If S = -1, it inverts in preparation 
 
 for subtraction by the adder. This is easily accomplished using exclusive- 
 
 or gates with S . as the controlling signal, 
 sign to to 
 
29 
 
 u o • 
 
 u l 
 
 U 2 
 
 u 3 
 
 DIVISION 
 LOGARITHM 
 
 MULTIPLICATION 
 EXPONENTIATION 
 
 \ 
 
 2 V\ 
 
 s k 
 
 2 v\ 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 
 1 
 
 
 1 
 
 
 
 
 
 1 
 
 
 
 
 10 
 
 
 10 
 
 
 
 
 
 1 
 
 1 
 
 
 111 
 
 
 111 
 
 
 
 1 
 
 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 1 
 
 -1 
 
 1 
 
 +1 
 
 1 
 
 
 
 1 
 
 1 
 
 
 
 
 10 
 
 
 10 
 
 
 
 1 
 
 1 
 
 1 
 
 
 Oil 
 
 
 Oil 
 
 1 
 
 
 
 
 
 
 
 
 10 
 
 
 10 
 
 1 
 
 
 
 
 
 1 
 
 
 10 1 
 
 
 10 1 
 
 1 
 
 
 
 1 
 
 
 
 +1 
 
 110 
 
 -1 
 
 110 
 
 1 
 
 
 
 1 
 
 1 
 
 
 111 
 
 
 111 
 
 1 
 
 1 
 
 
 
 
 
 
 
 
 
 
 
 1 
 
 1 
 
 
 
 1 
 
 
 10 1 
 
 
 10 1 
 
 1 
 
 1 
 
 1 
 
 
 
 
 
 110 
 
 
 
 110 
 
 1 
 
 1 
 
 1 
 
 1 
 
 
 111 
 
 
 111 
 
 For S 4 ° 
 
 u, 
 
 
 
 "l 
 
 1 ' "2 
 
 y - u 3 
 
 u 
 
 u 
 
 3 
 
 u 
 
 h 
 
 Ui 
 
 u r 
 
 "7 
 
 U 5 
 u 6 
 
 *7 
 
 Table h. Mini-Adder Analysis 
 
30 
 The shifting network shifts the input k places to the right. 
 It is a combinational right barrel shifter which propagates the sign 
 and operates without a clock pulse. Controlling the number of places 
 shifted is the three bit output (k2, kl, and kO) of the k counter, 
 1 < k < 7. 
 
 Finally, the eight-bit full adder (A + B) completes the 
 
 recursion (S 4 0) by adding the output of two selector circuits. The 
 
 pi 
 
 selector feeding input A of the adder chooses between u for exponentiation 
 or 2u + S , the output of the one-bit left shifter and mini-adder, for 
 other operations. The selector circuit feeding input B selects the 
 preset constants during exponentiation when S. f 0. These constants 
 represent 
 
 2 k (- m (i + s k 2-( k+1) )). 
 
 The constants could have also been stored in a ROM and addressed as in 
 bank II, but the limitation on hardware prevented this. In any case, 
 the preset constants are easily formulated as seen in Table 5. They are 
 
 B n = S . 
 sign 
 
 B 1= l 
 
 B 2 = B 3 = 
 
 Bi, = S . k2 kl kO 
 
 4 sign 
 
 B c = k2 kl kO v S . k2 kl kO 
 5 sign 
 
 B 6 = k2 kO 
 B = k2 KL kO 
 
31 
 
 
 
 
 
 2 k [-In (1 + £ 
 
 3 2 ~(k+l))] 
 
 k 
 
 DECIMAL 
 
 BINARY 
 
 s . 
 sign 
 
 k2 
 
 kl 
 
 kO 
 
 VALUES 
 
 VALUES 
 
 
 
 
 
 
 
 
 
 — 
 
 
 
 
 
 
 
 
 
 1 
 
 -0.4463 
 
 1 . 1000110 
 
 
 
 
 
 1 
 
 
 
 -0.47 11 
 
 1 . 1000100 
 
 
 
 
 
 1 
 
 1 
 
 -0.4850 
 
 1.1000010 
 
 
 
 1 
 
 
 
 
 
 -0.4923 
 
 1.1000001 
 
 
 
 1 
 
 
 
 1 
 
 -0.4957 
 
 1.1000000 
 
 
 
 1 
 
 1 
 
 
 
 -0.^973 
 
 1 . 1000000 
 
 
 
 1 
 
 1 
 
 1 
 
 -O.4966 
 
 1.1000000 
 
 1 
 
 
 
 
 
 
 
 -- 
 
 -- 
 
 ! i 
 
 
 
 
 
 1 
 
 0.5754 
 
 0.1001010 
 
 I 1 
 
 
 
 1 
 
 
 
 0.5341 
 
 . 1000100 
 
 ; l 
 
 
 
 1 
 
 1 
 
 O.5163 
 
 0.1000010 
 
 i 1 
 
 1 
 
 
 
 
 
 O.5080 
 
 0.1000001 
 
 '■ l 
 
 1 
 
 
 
 1 
 
 0.5037 
 
 0.1000000 
 
 i i 
 
 1 
 
 1 
 
 
 
 0.5011 
 
 . 1000000 
 
 ] l 
 
 1 
 
 1 
 
 1 
 
 0.4992 
 
 0.1000000 
 
 BO = 
 
 s . 
 
 sign 
 
 Bl = 
 
 1 
 
 B2 = 
 
 B3 = 
 
 B4 = 
 
 S k2 kl kO 
 sign 
 
 B5 = 
 
 k2 kl kO n/ S . 
 
 sign 
 
 b6 = 
 
 k2 kO 
 
 B7 - 
 
 k2 kl kO 
 
 k2 kl kO 
 
 Table 5« Preset Constant Formation 
 
32 
 where k2, kl, and kO are the three bits from the k counter. During 
 other operations, the selector feeding input B of the adder selects 
 the output of the right barrel shifter. In the case of multiplication, 
 it is in reality selecting zero. This becomes evident in Figure 9- 
 The carry in of the adder must be a 1 if S, = -1 to complete the 
 subtraction in the case of division and logarithm. 
 
 3 .h. Register Bank II 
 
 Following is a description of the elements contained in bank II 
 It computes the recursive formulas 
 
 Division 
 Multiplication 
 Logarithm 
 Exponentiation 
 
 -(k+1) 
 
 l k+l 
 
 'k+1 
 
 k+1 
 
 \ + \\ 2 
 
 o-(k+l) 
 p k + V 2 
 
 L k + (-m(i + s k 2- (k+1) )) 
 
 E 
 
 k+1 
 
 E. + S. E. 2 
 k k k 
 
 -(k+1) 
 
 The eight bit function register holds the number which tends 
 
 toward the answer. After eight recursions, this register should hold 
 
 the answer correct to seven bits. It is loaded after each recursion by 
 
 CP1 with the output of a three-way selector. The selector chooses either 
 
 the output of the adder when S 4 ° an(i INIT = 0, or the output of the 
 
 initialization switches when INIT = 1, or the output of the register 
 
 when S, = and INIT = 0. Note that in this last case, when S, = 0, no 
 k ' k ' 
 
 action need be taken on the contents of the register. That is 
 
 f = f 
 k+1 k 
 
33 
 
 PRESET CONSTANTS 
 "CL2 
 
 CL2 
 CLO 
 
 CLO 
 
 CL2 
 
 SELECTOR OUTPUT 
 
 
 
 
 
 NOT ALLOWED 
 
 
 
 1 
 
 
 
 1 
 
 1 
 
 BARREL SHIFTER 
 
 1 
 
 
 
 PRESET CONSTANTS 
 
 Figure 9« Adding Zero During Multiplication 
 
3^ 
 The complementing circuit inverts the output of a two-way- 
 selector depending on whether S is +1 or -1. If S = -1, it inverts 
 in preparation for subtraction by the adder. This is accomplished by 
 
 using exclusive-or gates with S . as the controlling signal. In the 
 
 sign 
 
 case of multiplication, it inverts the multiplicand rather than the 
 register. The multiplicand is gated through the selector by CLO. 
 
 The shift right network shifts the input (k + l) places to 
 the right. It is a combinational right barrel shifter which propagates 
 the sign and operates without a clock pulse. The three bit output of 
 the (k + l) counter, kk2, kkl, and kkO, signal the number of places 
 shifted, 2 < k+1 < 7- 
 
 Finally, the 8-bit full adder completes the recursion operation 
 by adding the contents of the function register and the output of a 
 selector. The selector chooses between the contents of the ROM during 
 natural logarithm if S =[ (see Table 3) or the barrel shifter for 
 other operations . The carry in of the adder must be a 1 if S, = -1 to 
 
 K. 
 
 complete the subtraction for operations other than natural logarithm. 
 
35 
 
 k . CONCLUSIONS 
 
 k.l. Hardware Requirements 
 
 The test machine operates on 8-bit words, one sign bit to 
 the left of the decimal point and seven working bits to the right . It 
 can be easily expanded to any number of bits desired with an accompanying 
 increase in hardware . The basic layout and components remain the same : 
 two main registers and a method for initializing them and displaying 
 their contents; a multiplicand register; two complementing circuits 
 (exclusive- or s) ; two right barrel shifters capable of shifting x bits, 
 where x is the number of bits in the word, while propagating the sign; 
 two full adders; and a number of two and three way selectors. 
 
 The basic components of control remain two ROMs capable of 
 storing 2x-2 words of x bits each, two counters which can be initialized 
 and can count up to x and x+1, an S, selection network, a handful of 
 NAND, NOR, and inverter gates, and a number of control switches. The 
 ROMs are loaded with the binary values of 
 
 - In (1 + S, 2" (k+l) ) 
 
 k 
 
 2 k (-In (1 + S R 2" (k+l) )). 
 
 When S, =0, the above become 
 
 k ' 
 
 - In (1) = 
 
 2 k (-In (1)) = 0. 
 
36 
 
 Therefore, only the constants for S = +1 and 1 < k < x need be stored. 
 For a UO bit word, 2 ROMs of 78 words each are required. Alternatively, 
 only one ROM may be employed and a left barrel shifter used to form 
 2 (-In (1 + S, 2~^ ')) for use during exponentiation. Some loss of 
 
 K. 
 
 accuracy results from using this method. For higher values of the counter, 
 the constants become -l/2 for S = +1 and +1/2 for S = -1 almost regardless 
 of the exact count. So the method used in the test machine could be the 
 best. The combinational circuits used to hard wire the constants are 
 much faster than the access time of the ROMs and also require less hardware 
 Some slight adjustments were made in the test machine values in order to 
 simplify the Boolean equations required and, thereby, simplify the hardware 
 
 An additional warning should be made in reference to the right 
 barrel shifter. It must propagate the sign. Some barrel shifters on the 
 market do not do this. The shifter for the test machine was built out of 
 four k to 1 selectors (7^LS153) and two 2 to 1 selectors (7U157). 
 
 k.2 . Speed Achieved 
 
 The only clock dependent circuits in the machine are the two 
 
 main registers and the two counters. The rest of the circuitry is 
 
 combinational. The limitation on the speed of the clock pulse in loading 
 
 the registers is dependent on the access time of the ROM. This is the 
 
 main limiting factor on the speed of the machine, the ROM access time . 
 
 Part of the address of the ROM word to be used is available immediately 
 
 upon the determination of the new S, values. The rest of the address 
 
 k 
 
 comes from the k counter values formed when the register is loaded. 
 
37 
 The number of recursions (i.e. clock pulses) needed to produce 
 an answer correct to M bits is M + 1, with the error being less than 
 2 neglecting round-off. So when working with seven bits plus a 
 sign bit, it takes seven clock pulses beyond initialization to reach the 
 correct answer. It is strongly believed that the hardware calculator 
 is considerably faster than software routines that are now often used. 
 
 k.3' Limitations and Extensions 
 
 The test machine does have certain limitations. One of these 
 is the range on allowable numbers. These ranges are listed for each 
 algorithm in Table 6. It is shown in DeLugish's paper that these ranges 
 are sufficient, in combination with some simple operations, to cover 
 a much larger range of numbers. For example, during exponentiation if 
 
 X X l 0g2 e • log e 2 
 e = e 
 
 m e (l+f ) In 2 
 
 where 
 
 then 
 
 X = x • 2 a 
 
 X log 2 e = I+f 
 
 I = integer 
 
 -1 < f < + 1 , 
 
 X I In 2 f In 2 
 
 e = e e 
 
 = 2 1 e X 
 
38 
 
 DIVISION 
 
 MULTIPLICATION 
 
 q = y/k 
 |y| e [1/2, i) 
 
 |x| 6 [1/2, 1) 
 
 q e (-1, +1) 
 
 p = y x 
 |y| e [1/2, i) 
 
 |x| E [1/2, 1) 
 
 P € (-1, +1) 
 
 LOGARITHM 
 
 EXPONENTIATION 
 
 L = In x 
 
 X € [1/2, 1) 
 
 L e (-In 2, 0) 
 
 E = e 
 
 x e (-In 2, 0) 
 
 E 6 [1/2, 1) 
 
 Table 6. Range of Numbers Allowed 
 
39 
 
 where 
 
 x = f In 2 
 
 - In 2 < x < + In 2 
 
 Therefore, 
 
 e X = e X 2 1 , e X € [l/2, 2) 
 
 and it takes three basic steps to do the operation: (l) identify I and 
 f by multiplying X by the stored constant log e; (2) generate x by 
 multiplying f by the stored constant ln2; and (3) evaluate e via the 
 main algorithm. In a practical application the above and other simple 
 operations for the remaining algorithm would be done by the machine . 
 
 Another limitation arises during division. If l/2 < |x | < 3/^> 
 then d = 2. At the same time |y| € [l/2, l) and shifting y left one bit 
 will put y out of the range of the machine. If this is the case, that is 
 if d = 2, use the initial equation 
 
 q l = *0 = y o 
 
 and at the end of the operation shift the function register left one bit 
 to restore the answer. This too is easily internalized into the machine. 
 
 A last limitation cannot be provided for, that of round-off error 
 It comes about when bits are shifted right, out of the register. Recall 
 that the round-off error is at most 2 ^ ' after M+l recursions have 
 been performed. 
 
UO 
 
 With additional hardware, the calculator can be expanded to 
 include square root, tangent, cotangent, sine, cosine, arctangent, 
 arcsine, and arcosine . In this case, a third register bank to hold the 
 imaginary part of the complex exponential would be required and a more 
 involved initialization network would be needed. 
 
APPENDIX 
 
 A.l. Operation of the Test Machine 
 
 Outlined below is the series of steps required to cause the 
 proper operation of the test machine. 
 
 STEP 1: Set OP CODE switches 
 
 CP1 = CP2 = INIT =0 , SO = 1. 
 
 STEP 2: INITIALIZATION STEP 
 Set INIT = 1 
 Set INITIALIZATION switches for 
 
 u register 
 
 function register 
 
 y (multiplicand) register 
 (during multiplication) 
 Toggle CP1 (0 -> 1 - 0) 
 
 The display should reflect the contents just loaded into 
 the register during initialization. 
 STEP 3: Set INIT = 
 
 Toggle CP1 (0 -* 1 -* 0) until k COUNTER contains 111 (seven) 
 (During exponentiation when S ^ 
 
 Toggle CP1 (0 -* 1 -» 0), 
 
 Set SO = 0, 
 
 Toggle CP2 (0 - 1 -» 0), 
 
 Set SO = 1.) 
 
 After the seventh count, the function register contains the 
 answer . 
 
U2 
 A. 2 . Some Machine Examples 
 
 The following examples are listings of the results obtained 
 from running some problems on the test machine. 
 
EXAMPLE 1: DIVISION 
 
 h3 
 
 0.0101011 = 1/3 = q = 
 
 x. 
 
 l/k 0.0100000 
 
 3A " o.nooooo 
 
 d = 1 
 
 k+1 
 
 u, 
 
 1 
 
 
 2 (3/4 • i - i) = 
 
 -1/2 
 
 
 
 
 + 1 
 
 1.1000000 
 
 
 
 0.0100000 
 
 2 
 
 
 1.0000000 
 
 
 
 0.0100000 
 
 
 
 + 1 
 
 
 + 
 
 0.0001000 
 
 
 
 + 1.1100000 
 
 
 
 0.0101000 
 
 
 
 
 1.1100000 
 
 
 
 
 3 
 
 + 1 
 
 1.1000000 
 
 
 
 0.0101000 
 
 1+ 
 
 
 1.0000000 
 
 
 
 0.0101000 
 
 
 
 + 1 
 
 
 + 
 
 -0000010 
 
 
 
 + 1.1111000 
 
 
 
 0.0101010 
 
 
 
 
 1.1111000 
 
 
 
 
 5 
 
 
 
 1.1110000 
 
 
 
 0.0101010 
 
 6 
 
 
 
 1.1100000 
 
 
 
 0.0101010 
 
 7 
 
 + 1 
 
 1.1000000 
 
 
 
 0.0101010 
 
 STOP 
 
 
 
 
 ANSWER 
 (ROUND -OFF ERROR) 
 
EXAMPLE 2: DIVISION 
 
 kk 
 
 1.0001101 Z -9/10 = 
 
 y o 
 
 q = — = 
 
 x o 
 
 1+5/6U 
 -25/32 ' 
 
 0.1011010 
 1.0011100 
 
 d o= - 1 
 
 
 
 k+1 
 
 \ 
 
 1 
 
 
 2 (-25/32 ' (-1) -1) = 
 
 -7/16 
 
 
 + 1 
 
 1.1001000 
 
 1.0100110 
 
 2 
 
 
 1.0010000 
 
 1.0100110 
 
 
 
 + 1 
 
 + 1.1101001 
 
 
 
 + 1.1100100 
 
 1.0001111 
 
 
 
 
 1 . 1110100 
 
 
 3 
 
 
 
 1.1101000 
 
 1.0001111 
 
 k 
 
 
 
 1.1010000 
 
 1.0001111 
 
 5 
 
 + 1 
 
 1.0100000 
 
 1.0001111 
 
 ! 6 
 | 
 
 
 0.1000000 
 
 1.0001111 
 
 i 
 
 
 + 1 
 
 + 1.1111110 
 
 i 
 
 
 + 1.1111101 
 
 1.0001101 
 
 i 
 
 + 1 
 
 1.0111101 
 
 
 ! 7 
 
 
 0.1111010 
 
 1.0001101 
 
 
 
 + 1 
 
 1.1111111 
 
 STOP 
 
 
 + 1.1111110 
 
 1.0001100 
 
 
 
 
 1.1111000 
 
 ANSWER 
 (ROUND -OFF ERROR) 
 
EXAMPLE 3: DIVISION 
 
 k5 
 
 n inmnA1 ~ n/ , A y o 9/16 O.IOOIOOO 
 0.1101001 = 9/10 = q = — = ^±r = n.iminnn 
 
 x Q ~''~ 11/16 "" 0. 
 
 1011000 
 
 d Q = 2* 
 
 k+1 
 
 \ 
 
 1 
 
 
 2 (11/16 • 2 - 
 
 1) = 3/h 
 
 
 
 - 1 
 
 0.1100000 
 
 
 0.1001000 
 
 2 
 
 
 
 1.1000000 
 
 - 1 
 
 - (0.0110000) 
 
 0.0010000 
 
 
 0.1001000 
 - (0 .0010010) 
 0.0110110 
 
 3 
 
 
 
 0.0100000 
 
 
 0.0110110 
 
 1+ 
 
 - 1 
 
 0.1000000 
 
 
 0.0110110 
 
 5 
 
 
 
 1.0000000 
 
 - 1 
 
 - (0.0000100) 
 
 1.1111100 
 
 
 0.0110110 
 - (0.0000001) 
 0.0110101 
 
 6 
 
 
 
 1.1111000 
 
 
 0.0110101 
 
 7 
 
 
 
 1.1110000 
 
 
 0.0110101 
 SHIFT 
 
 STOP 
 
 
 
 
 0.1101010 
 
 ANSWER 
 (ROUND-OFF error) 
 
 *Use d = 1 for computing q , and correct at the end! 
 
46 
 
 EXAMPLE 4: MULTIPLICATION 
 
 O.lOOllOO Z 605/1024 = p = y x = ll/l6 * 55/64 = 0.1011000 . O.11O1110 
 
 "0 
 
 m Q = 1 
 
 k+1 
 
 u, 
 
 1 
 
 
 
 2 (55/64 - 1) = 
 1.1011100 
 
 -9/32 
 
 0.1011000 
 
 2 
 
 - 1 
 
 1.0111000 
 
 
 0.1011000 
 
 3 
 
 
 
 0.1110000 
 
 - 1 
 
 1.1110000 
 
 
 0.1011000 
 - (0.0001011) 
 0.1001101 
 
 4 
 
 
 
 1.1100000 
 
 
 0.1001101 
 
 5 
 
 - 1 
 
 1.1000000 
 
 
 0.1001101 
 
 6 
 
 
 
 1.0000000 
 
 - 1 
 
 0.0000000 
 
 STOP 
 
 
 0.1001101 
 
 - (0.0000001) 
 
 0.1001100 
 
 ANSWER 
 
 1 
 
EXAMPLE 5: MULTIPLICATION 
 
 hi 
 
 l.iooiooi = - 55/128 = p = y n -x n = 5/8 • (-11/16) = 0.1010000 • 1.0101000 
 
 
 
 m = -1/2 
 
 k+1 
 
 \ 
 
 1 
 
 
 2 (-11/16 - (- 
 
 1/2)) = 
 
 -3/8 
 
 0+y (-l/2) 
 
 
 
 
 1.1010000 
 
 
 
 1.1011000 
 
 2 
 
 - 1 
 
 1.0100000 
 
 
 
 1.1011000 
 
 3 
 
 
 0.1000000 
 
 - 1 
 
 
 
 1.1011000 
 - (0.0001010) 
 
 
 - 1 
 
 1.1000000 
 
 
 
 1.1001110 
 
 1+ 
 
 
 1.0000000 
 
 - 1 
 
 
 
 1 . 1001110 
 - (0.0000101) 
 
 
 
 
 0.0000000 
 
 
 
 1.1001001 
 
 
 
 STOP 
 
 
 
 ANSWER 
 
EXAMPLE 6: LOGARITHM 
 
 In x = In 23/32 = In 0.1011100 = -0-330 = 1.1010110 
 
 *o = 2 
 
 hQ 
 
 k+1 
 
 \ 
 
 ( 
 
 1 
 
 
 2 (23/32 • 2 - 1) = 
 
 - +7/8 
 
 - In 2 
 
 
 - 1 
 
 0.1110000 
 
 
 1.0100111 
 
 2 
 
 
 1 . 1100000 
 
 - 1 
 
 - (0.0111000) 
 
 
 1.0100111 
 0.0100101 
 
 1.1001100 
 
 
 
 
 0.0101000 
 
 
 
 I 3 
 
 - 1 
 
 0.1010000 
 
 
 1.1001100 
 
 1. 
 
 
 
 1.0100000 
 
 - 1 
 
 - (0.0001010) 
 
 0.0010110 
 
 
 1.1001100 
 
 0.0001000 
 
 1.1010100 
 
 5 
 
 
 
 0.0101100 
 
 
 1.1010100 
 
 ! 6 
 
 - 1 
 
 0.1011000 
 
 
 1.1010100 
 
 7 
 
 
 1.0110000 
 - 1 
 
 
 1.1010100 
 0.0000001 
 
 ; stop 
 
 
 
 - (0.0000001) 
 0.0101111 
 
 
 1.1010101 
 
 ANSWER 
 
 (round-off error) 1 
 
 _ 1 
 
EXAMPLE 7: LOGARITHM 
 
 In x = In 7/8 = In O.lllOOOO = -O.I3I+ = 1.1101111 
 
 V 1 
 
 h9 
 
 k+l 
 
 \ 
 
 1 
 
 
 2 (7/8 ' 1 - 1) = 
 
 -1/1* 
 
 
 
 
 
 1.1100000 
 
 
 0.0000000 
 
 2 
 
 + 1 
 
 1.1000000 
 
 
 0.0000000 
 
 3 
 
 
 
 1.0000000 
 
 + 1 
 
 + 1.1110000 
 1.1110000 
 
 
 0.0000000 
 1.1110001 
 1.1110001 
 
 k 
 
 
 
 1.1100000 
 
 
 1 . 1110001 
 
 5 
 
 + 1 
 
 1.1000000 
 
 
 1.1110001 
 
 6 
 
 
 
 1.0000000 
 
 + 1 
 
 + 1.1111110 
 1.1111110 
 
 
 1.1110001 
 1.1111110 
 1.1101111 
 
 7 
 
 
 
 1.1111110 
 
 
 1.1101111 
 
 STOP 
 
 
 
 
 ANSWER 
 
EXAMPLE 8: EXPONENTIATION 
 
 50 
 
 x -5/8 
 e = e ' 
 
 = e 
 
 0.1010000 
 
 e„ = 
 
 In e^ = 
 
 E = 0.535 a 0.1000101 
 
 -1/2 
 e ' = 0.1001110 
 
 -1/2 = 1.1000000 
 
 k+1 
 
 1 
 
 
 2 (-5/8 - (-1/2)) = 
 
 -1/k 
 
 
 
 
 
 1.1100000 
 
 
 . 1001110 
 
 2 
 
 - 1 
 
 1.1000000 
 
 
 0.1001110 
 
 3 
 
 
 
 1.1000000 
 
 + 0.1000100 
 
 0.0000100 
 
 0.0001000 
 
 
 0.1001110 
 - (0.0001001) 
 0.1000101 
 
 k 
 
 
 
 0.0010000 
 
 
 0.1000101 
 
 5 
 
 
 
 0.0100000 
 
 
 0.1000101 
 
 6 
 
 + 1 
 
 0.1000000 
 
 
 0.1000101 
 
 7 
 
 
 0.1000000 
 + 1.1000000 
 
 
 0.1000101 
 0.0000000 
 
 
 
 
 0.0000000 
 
 
 0.1000101 
 
 
 
 STOP 
 
 
 ANSWER 
 
EXAMPLE 9: EXPONENTIATION 
 
 e x = e -H/32 m e 1.1010100 = E m 0>?13 = . 1011011 
 
 -1/k 
 
 e Q = e ' = O.llOOlOO 
 
 In e = -1/k = 1.1100000 
 
 51 
 
 k+1 
 
 \ 
 
 1 
 
 
 
 2 (-11/32 - (-1/U)) = 
 1.1101000 
 
 -3/16 
 
 0.1100100 
 
 2 
 
 
 
 1.1010000 
 
 0.1100100 
 
 3 
 
 - 1 
 
 1.0100000 
 
 0.1100100 
 
 k 
 
 - 1 
 
 1.0100000 
 
 + 0.1000010 
 
 1.1100010 
 
 1.1000100 
 
 0.1100100 
 - (0.0000110) 
 0.1011110 
 
 5 
 
 
 
 1.1000100 
 0.1000001 
 0.0000101 
 0.0001010 
 
 0.1011110 
 - (0.0000010) 
 0.1011100 
 
 6 
 
 
 
 0.0010100 
 
 • 0.1011100 
 
 7 
 STOP 
 
 
 
 0.0101000 
 
 0.1011100 
 
 ANSWER 
 (ROUND -OFF ERROR) 
 
52 
 
 LIST OF REFERENCES 
 
 DeLugish, B. C, "A Class of Algorithms for Automatic Evaluation of 
 Certain Elementary Functions in a Binary Computer," Ph.D. 
 Dissertation, Department of Computer Science Report No. 99 > 
 University of Illinois at Urbana-Champaign, Urbana, Illinois, 
 June 1970. 
 
 Faiman, M., "EXCEL: Experiments in Computer Electronics and Logic," 
 Manual for Computer Science 209B, Second Edition, University of 
 Illinois at Urbana-Champaign, Urbana, Illinois, September 1972. 
 
 Robertson, J. E., "A New Class of Digital Division Methods," Department 
 of Computer Science Report No. 82, University of Illinois at 
 Urbana-Champaign, Urbana, Illinois, March 5, 1958. 
 
 Robertson, J. E., "introduction to Digital Computer Arithmetic," 
 
 Department of Computer Science File No. 599? University of Illinois 
 at Urbana-Champaign, Urbana, Illinois, June 5? 196^. 
 
 Robertson, J. E., "A Method of Decimal Division Based on the Use of 
 
 Continued Products, " Class Notes, Department of Computer Science, 
 University of Illinois at Urbana-Champaign, Urbana, Illinois. 
 
BLIOGRAPHIC DATA 
 EET 
 
 1. Report No. 
 
 UIUCDCS-R-75-692 
 
 3. Recipient's Accession No. 
 
 Title and Subtitle 
 
 \ Four Function Calculator 
 
 5- Report Date 
 
 January 1975 
 
 6. 
 
 Whor(s) 
 
 4ary Jane Irwin 
 
 8. Performing Organization Rept. 
 No - UIUCDCS-R-75-692 
 
 Performing Organization Name and Address 
 
 Jniversity of Illinois at Urbana-Champaign 
 department of Computer Science 
 Jrbana, Illinois 61801 
 
 10. Project/Taslc/Wotk Unit No. 
 
 11. Contract /Grant No. 
 
 NSF GJ 38201* 
 
 Sponsoring Organization Name and Address 
 
 National Science Foundation 
 L800 G Street, N.W. 
 Washington, D.C 20550 
 
 13. Type of Report & Period 
 Covered 
 
 Master of Science Thesi;; 
 
 14. 
 
 Supplementary Notes 
 
 Abstracts 
 
 'he algorithms developed by DeLugish for performing multiplication, division, 
 .ogarithm, and exponentiation are explained. The fundamental technique used in 
 ,he algorithms is normalization of the operands through the use of continued 
 iroducts or sums. The test machine which implements these algorithms is explained 
 .n detail. Layouts and examples are provided. 
 
 Key Words and Document Analysis. 17a. Descriptors 
 
 ontinued product, continued sum, recursion, normalization selector, barrel 
 hifter, ROM 
 
 <■ Identifiers Open-Ended Terms 
 
 I (OSATI F 
 
 e Id/Group 
 
 lAvailability Statement 
 
 Release unlimited 
 
 19. Security Class (This 
 Report) 
 
 UNCLASSIFIED 
 
 20. Security Class (This 
 Page 
 
 UNCLASSIFIED 
 
 21. No. of Pages 
 
 5h 
 
 22. Price 
 
 -M NTIS-35 (10-70) 
 
 USCOMM-DC 40329-P7I 
 
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 To 
 
 5C 
 
 * j> 
 
 $iJl 
 
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BSfl 
 
 fflmm 
 
 nni OF ILL ,NO,S.URBANA 
 S'OMlieflno COO? MHl.| N|lm 
 
 "•port . 
 
 ,3 0112 08840166.? 
 
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