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Digitized by the Internet Archive 
 in 2013 
 
 http://archive.org/details/slidescannerinpu249ryan 
 
-J^.iy-f Report No. 2*+9 
 
 ?7UUf 
 
 H*** 
 
 A SLIDE SCANNER INPUT FOR PARAMATRLX 
 
 by 
 
 LAWRENCE D. RYAN 
 
 September 20, I967 
 
 THE LIBRARY OF THE 
 
 1 lu xc ldB8 
 
 UNIVERSITY OF ILLINOIS 
 
Report No. 2*+9 
 
 A SLIDE SCANNER INPUT FOR PARAMATRIX 
 
 by 
 
 LAWRENCE D. RYAN 
 
 September 20, 1967 
 
 Department of Computer Science 
 University of Illinois 
 Urbana, Illinois 6l801 
 
 This work was submitted in partial fulfillment of the requirements for 
 the degree of Master of Science in Electrical Engineering, September, 1967 , 
 and was supported in part by the Office of Naval Research, Contract No. 
 N00014-67-A-0305-0007 . 
 
Ill 
 
 ACKNOWLEDGEMENT 
 
 The author wishes to express his appreciation to his thesis 
 advisor, Professor W. J. Poppelbaum, whose support and good counsel 
 have made this thesis project possible. Thanks are also extended to 
 Professor Louis van Biljon, whose suggestions and encouragement were 
 very helpful. 
 
 The author is further grateful to the many members of the 
 research group who gave freely of their time and experience. Finally, 
 the author thanks Mrs . Jonnie Hudspath and Mrs . Joyce Porter for their 
 excellent typing of the thesis. 
 
iv 
 
 TABLE OF CONTENTS 
 
 ACKNOWLEDGEMENT .......................... iii 
 
 LIST OF FIGURES ........................... v 
 
 1. INTRODUCTION .......................... 1 
 
 1.1 Paramatrix System ...................... 1 
 
 1.2 Basic Slide Scanner System ................. 3 
 
 2o COMPLETE SYSTEM AND CIRCUIT DESCRIPTION ............. 6 
 
 2.1 Complete Slide Scanner Layout ................ 6 
 
 2.2 Cathode -Ray Tube and Photomultiplier Specifications ..... 13 
 
 2.3 Differential Amplifier - Linear Analysis .. ......... 17 
 
 2.X Gating Pulse Generator . . . „ ............ ........ 25 
 
 2.5 Linear Ramp and DC Balance ................. 29 
 
 2.6 Oscillator and DC Balance ................. 31 
 
 2.7 Detection Circuit for Protective Unblanking System ..... 33 
 
 2.8 Photomultiplier Detection Circuit .............. 35 
 
 3. CONCLUSION ........................... 38 
 
 BIBLIOGRAPHY ............................ 1*1 
 
LIST OF FIGURES 
 
 v 
 
 FIGURE 
 
 PAGE 
 
 1. Simplified Version of Paramatrix Slide Scanner . . 
 
 2. (a) . Horizontal Deflection Waveform . « . . . . , 
 ("b) . Vertical Deflection Waveform. . . • . . . . . . , 
 
 3> Complete Slide Scanner Layout ........... 
 
 k. Timing Diagram for Clock, Gating Pulse / ; and Ramp 
 
 5 . CRT Circuit .................... 
 
 6. Photomultiplier Circuit .............. 
 
 7. Differential Amplifier for Linear Analysis . . . , 
 
 8. Differential Amplifier for Slide Scanner . . . . , 
 9° Gating Pulse Generator .............. 
 
 10. Linear Ramp and DC Balance ............ 
 
 11. Oscillator and DC Balance ............. 
 
 12. Detection Circuit for Protective Unblanking System 
 
 13. Photomultiplier Detection Circuit ......... 
 
 1^. (a) . Experimental Setup ............. 
 
 (b) . Typical Output Pattern . . 
 
 « o • o 
 
 . k 
 . 8 
 . :8 
 . 10. 
 . 11 
 . ik 
 . 16 
 . 18 
 . 26 
 
 • 27 
 . 30 
 . 32 
 . ^ 
 
 • 39 
 
 • 39 
 
1 . INTRODUCTION 
 
 1.1 Paramatrix System 
 
 Paramatrix is a hybrid analog-digital graphical processor 
 designed and built by members of Task 15 under the direction of 
 Professor W, J. Poppelbaum, It is capable of performing the following 
 operations on an input pattern: translation and magnification of the 
 pattern in the horizontal and vertical directions, rotation through 
 360 , thinning 'cloudy' portions of the input pattern, and filling in 
 gaps that appear in the pattern (the location of the gaps must be 
 manually indicated to the processor by the operator) . The resultant 
 output pattern is displayed on a two-dimensional 32 x 32 array of 
 light bulbs . 
 
 Every clock cycld the Paramatrix system generates a pair of 
 
 quantized analog voltages (x., "y.).» i* J - 0, > < . , 31. representing the 
 
 ■*- J 
 
 spatial co-ordinates of one of 1,02^ points of intersection in the output 
 matrix, Each pair of these analog voltages is fed to the Transformer 
 section of Paramatrix where it undergoes an inverse transformation 
 consisting of rotation, demagnification, and translation. The resulting 
 analog voltages, called X. . and Y. ., refer to the spatial co-ordinates 
 of a test point on the original input pattern, and are related to. x . and 
 y. by the following equations: 
 
 X. . = - (X. cos0 - y. sine) - a (1.1) 
 
 ij m 1 j 
 
¥. . = - (x, sine - y. cose) -b (l.2) 
 
 ij n i J 
 
 ■where — and — are the magnification factors; a and b are the trans- 
 m n 
 
 lation components; and 9 is the angle of rotation. If the test point 
 (X. . , Y. .) is a part of the input pattern, then the light bulb corres- 
 ponding to the analog levels (x. , y.) is lit. If the test point (X. ., Y. .) 
 
 i J ij i«] 
 
 is determined not to be a part of the input pattern then the light bulb 
 corresponding to (x., y.) is not lit. In this manner, all 1,02^ points 
 of intersection in the output matrix are interrogated and appropriate 
 bulbs are lit resulting in the transformed pattern being displayed on 
 the output matrix. 
 
 The slide scanner described in this thesis was designed 
 specifically as an efficient and flexible method for providing Paramatrix 
 with an input pattern. It consists of a CRT which is used to scan the 
 slide input pattern, a photomultiplier to detect the presence of light 
 behind the slide, and the necessary control circuitry. The pattern on 
 the slide is made up of transparent lines on an opaque background. This 
 type of slide was favored over dark lines on a clear background because 
 the detection circuit that resulted was of simpler design. 
 
 Prior to the development of the slide scanner, the input 
 pattern to Paramatrix was provided by four profiles of F(x) versus X, 
 each profile consisting of thrity-two variable voltages stored on 
 potentiometers for equal increments of X. This method of transmitting 
 an input pattern to Paramatrix was deemed inadequate due to the difficulty 
 
of manually adjusting many potentiometers each time a new pattern was 
 to be displayed o The slide scanner was designed to alleviate this 
 problem. 
 
 1.2 Basic Slide Scanner System 
 
 In order to acquaint the reader with the fundamental design 
 ideas that resulted in the Paramatrix slide scanner, a simplified 
 version of the scanner system is shown in Figure 1. A detailed block 
 diagram of the entire slide scanner system is discussed in Section 2.1. 
 
 The method of scanning which is employed makes direct use of 
 the fact that X. . and Y. ., the analog outputs of the Transformer, 
 correspond to the spatial co-ordinates of a test point on the input 
 slide. To determine whether or not this point is a part of the input 
 pattern, amplified versions of X. . and Y. . are fed to the horizontal 
 and vertical deflection plates of the CPT to deflect the electron beam 
 to the appropriate point on the slide . Thus the presence of light 
 behind the slide would indicate that the test point is a part of the 
 input pattern. Alternatively, the absence of light behind, the slide 
 would mean that the test point is not a part of the input pattern „ 
 
 As indicated in Figure 1, positive transitions of the clock 
 are differentiated and used to reset the R-S flip-flop at the beginning 
 of every clock cycle. The presence of light behind the slide causes a 
 negative going pulse to appear at the output of the photomultiplier • 
 This pulse is shaped and inverted by the detection circuit and is 
 
X 
 
 cc 
 
 < 
 
 2 
 
 1 
 
 
 _,_,_ 
 
 
 >- 
 
 
 _l 
 
 
 Z 
 
 K 
 
 o 
 
 O 
 
 6 
 
 z 
 
 
 o 
 
 h- 
 
 
 Z 
 
 1- 
 
 LU 
 
 cn 
 
 oe 
 
 z 
 
 u 
 
 < 
 
 u. 
 
 o: 
 
 u. 
 
 i- 
 
 Q 
 
 <n 
 
 
 o 
 
 
 0. 
 
 
 ** 
 
 T 
 
 o 
 o 
 
 1 
 
 o 
 
 CO 
 
 <u 
 
 •H 
 H 
 
 co 
 
 X 
 •H 
 
 o3 
 
 Ph 
 
 Ch 
 O 
 
 O 
 
 •H 
 
 ra 
 
 *H 
 
 > 
 
 <D 
 
 •H 
 
 =h 
 •H 
 rH 
 
 s 
 
 •H 
 
 co 
 
 H 
 
 •H 
 Pn 
 
used to set the R-S flip-flop. The inverted output of the flip-flop 
 is one input to a NOR circuit in Paramatrix. The second input to the 
 NOR circuit is the clock which is a logical "1" during the first half 
 of each cycle and a logical "0" during the second half. Thus, during 
 the second half of each clock cycle, the clock input to the NOR circuit 
 gates the inverted output of the R-S flip-flop. The signal ("0" = light 
 the bulb, "1" = do not light the bulb) transmitted by this gate triggers 
 the flip-flop which controls the lighting of the bulb located at the 
 point (x. ,y.) in the output matrix. 
 
 It may be pointed out here that the present slide scanner 
 does not deliver signals to drive either the Interpolator or Gap Filler 
 circuits of Paramatrix. This is because the operation of these circuits 
 requires that the input pattern be represented by four profiles of 
 F(x) versus X, each profile consisting of voltages set on 32 potentio- 
 meters. 
 
 The ultimate solution to the problem of providing Paramatrix 
 "with an input pattern thus reduces to that of having 1.28 autonomous 
 analog storage cells feeding the diamond gates of the Interpolator. 
 The slide input pattern would be scanned column oy column and, using 
 counters, D/A converters, and associated switching circuitry, the 
 voltages corresponding to the y co-ordinates of points on the pattern 
 would be sent to the appropriate storage cells. At the present time 
 such a system is not considered economically feasible. 
 
2. COMPLETE SYSTEM AND CIRCUIT DESCRIPTION 
 
 2 . 1 Complete Slide Scanner Layout 
 
 In addition to scanning the input pattern point by point 
 (as described in Section 1.2) , it was desired to incorporate into the 
 scanner system variable horizontal and vertical sensitivity controls. 
 In this manner analog levels (X. ., Y. .) that correspond to points 
 "near" line segments of the input pattern would be considered as being 
 part of the input pattern. 
 
 There were several reasons for developing this feature of 
 the slide scanner. First, because the resolution of the output matrix 
 is 32 lines, it is reasonable to adjust the photomultiplier gain and 
 the beam intensity so that the maximum thickness of any line segment in 
 the output pattern is one line (of light bulbs) . It is clear that some 
 parts of the output pattern could correspond to points between adjacent 
 light bulbs and thus would not appear on the output matrix. Increasing 
 the sensitivity in the horizontal and 'or vertical directions would 
 insure that the entire output pattern be displayed. 
 
 Second, it was felt that a device for thinning and thickening 
 the lines in the output pattern would be a desirable feature. Variable 
 sensitivity controls (as described above) would accomplish this aim. 
 
 Last, small gaps in the output pattern could be filled in by 
 adjusting the horizontal and/or vertical sensitivity controls (also 
 resulting in thicker lines) . 
 
The variaDle sensitivity in the horizontal direction is 
 achieved by superimposing a linear ramp waveform, symmetric about 
 volts, on the amplified version of X. , . A linear ramp was chosen in 
 preference to other waveforms, such as sinusoids, so that the CRT 
 beam would spend the same amount of time traversing a line segment 
 regardless of which part of tne ramp corresponded to the line crossing. 
 In this manner a uniform light output was assured for all possible 
 line interceptions by the CRT beam, 
 
 The vertical sensitivity is implemented by superimposing a 
 high frequency sinusoid on the amplified version of Y. . . The frequency 
 of the sinusoid (approximately h- MHz) and the thickness of the focused 
 spot (approximately °03") is such that when both the horizontal and 
 vertical sensitivities are set at some non-zero value, the CRT beam 
 completely sweeps out a rectangular area symmetric about the point 
 {X. .0 Y, .)• Typical horizontal and vertical deflection waveforms 
 (with non-zero horizontal and vertical sensitivities) are given in 
 Figure 2 . 
 
 It was anticipated tnat the undeflected CRT beam would not 
 
 fall on the geometric center of the CRT screen . Thus it became necessary 
 
 to add adjustable DC voltages to both horizontal and vertical deflection 
 
 waveforms c The horizontal DC balance is first added to the ramp waveform 
 
 by means of a simple resistor summing circuit, and the result is added 
 
 to X.. and amplified by a differential amplifier. A similar procedure is 
 1 J 
 
 followed to obtain the vertical deflection waveform* The complete 
 
(a) 
 
 GO 
 
 u 
 
 1) 
 
 U 
 
 t 
 
 VI 
 
 Figure 2<, (a) Horizontal Deflection Waveform 
 (b) Vertical Deflection Waveform 
 
layout of the slide scanner system, including the deflection circuitry 
 already discussed , is shown in Figure 3° 
 
 The interval during each clock cycle in which the ramp is 
 initiated and cut off is subject to several restrictions. First, it is 
 clear that the ramp must finish its excursion before the end of the 
 first half of each clock cycle since information as to whether or not 
 light was detected behind the slide must be sent back to Paramatrix 
 prior to the start of the second half of each clock cycle. 
 
 The earliest time after the start of each clock cycle that 
 the ramp can be initiated depends on how fast X. . stabilizes to its 
 
 new value. First, there is a 600 ns delay between the fall of the i 
 
 th 
 digital gating pulse to the i Transformer diamond gate and the rise 
 
 of the i + 1 digital gating pulse to the i + 1 Transformer diamond 
 
 gate. This delay is to insure that two adjacent Transformer diamonds 
 
 do not try to switch different voltages on the common Transformer bus 
 
 at the same time* The end result is that it takes approximately 600 ns 
 
 after the start of each clock pulse for X. . to begin to approach its 
 
 new value . 
 
 The second factor affecting the initiation of the ramp is 
 
 the rise (or fall) time of X. . to its new value. This time is greatest 
 
 ij 
 
 when the inputs to Paramatrix are such that X. . changes its value by 
 
 ■*- J 
 
 the maximum amount of 20 volts. This takes approximately 1.8 us. Thus 
 we see that it requires a delay of about 2,k us after the start of 
 each clock cycle before we are assured that X. , is stabilized at its 
 new value . 
 
10 
 
 •p 
 
 g 
 
 >> 
 
 0) 
 
 g 
 
 o 
 
 (D 
 
 ■d 
 
 •H 
 
 H 
 
 CO 
 
 0) 
 
 -p 
 
 H 
 
 ft 
 
 o 
 
 CO 
 
 •H 
 
11 
 
 The preceeding discussion indicates the need for a circuit 
 that can produce a delayed gating pulse of appropriate width every clock 
 cycle to initiate and turn off the ramp= This circuit is called the 
 gating pulse generator in Figure 3' In addition there was need to delay 
 the start of the ramp some 150 ns beyond the leading edge of the gating 
 pulse. The reason for this will "be given when the unblanking system 
 is discussed. 
 
 The time relationship of the clock, the gating pulse, and 
 the ramp is shown in Figure h. 
 
 Paramatrix 
 Clock 
 
 Gating 
 Pulse 
 
 Linear 
 Ramp 
 
 -5 
 
 
 -5 
 +2 
 
 Figure ^ Timing Diagram for Clock, Gating Pulse and Ramp. 
 
12 
 
 It Is possible, for certain combinations of inputs to Para- 
 matrix, for X. . and Y. . to be bumped to + 10 volts for many clock cycles. 
 Since the Pl6 phosphor used in the CRT scanner is easily burned, 
 precautions had to be taken to blank the electron beam "whenever the 
 voltages at the deflection plates remained constant for more than a 
 specified number of clock cycles. This protective unblanking system 
 is shown in Figure 3* 
 
 The detection circuits sense the voltage at each of the 
 deflection plates and produce a logical "l" if the respective voltage 
 is changing and a logical "0" if it is not changing. Thus, if one or 
 more of the detection circuits is in the "l" state, the output of the 
 NOR circuit they feed is a "0". This "0", as input to the second NOR 
 circuit, gates the output of the gating pulse generator to the unblanking 
 amplifier. The output of the amplifier is AC coupled to the control 
 grid of the CRT. Under these circumstances, the beam is on when the 
 gating pulse is at -5 volts and off -when the gating pulse is at volts. 
 
 Now it can be seen why the start of the ramp must be delayed 
 approximately 150 ns beyond the leading edge of the gating pulse. This 
 Is because there is a cumulative 150 ns delay between the leading edge 
 of the gating pulse and the turn on of the electron beam. 
 
 If all of the detection circuits are in the state, the 
 gating pulse is inhibited and the output of the unblanking amplifier 
 remains constant. The control grid of the CRT returns to its DC value, 
 which is beyond cut off, and the beam is off. 
 
13 
 
 The circuitry to detect light behind the slide, shown in 
 Figure 3> is exactly as described in Section 1.2. 
 
 2.2 Cathode-Ray Tube and Photomultiplier Specifications 
 
 The particular requirements of the Paramatrix slide scanner 
 system dictated many of the features of the cathode-ray tube. Because 
 of the relatively high scanning rate of Paramatrix (10 us per position 
 when the scanner provides the input pattern) , a short persistence 
 phosphor was required. Pl6 phosphor, with a time constant after aging 
 of 50 ns, was used. Since the deflection waveforms contained high 
 frequency components (a 1.5 us ramp and a k- MHz sinusoid), electron- 
 static deflection was favored over magnetic deflection. 
 
 Most "standard" flying-spot scanner tubes have spot sizes 
 of the order of several mils. Such high resolution was not necessary 
 since the resolution of the Paramatrix output pattern is 32 lines. 
 In fact, it was found that the majority of the single gun 5 inch 
 oscilloscope tubes had adequate resolution for the scanner system. 
 However, electrostatically deflected oscilloscope tubes have 
 noticeable deflection defocusing at the periphery of the useful 
 screen area. For this reason a tube with a large useful screen area 
 was desired so that scanning could be done easily and reliably in a 
 relatively small central portion of the useful screen area. 
 
Ik 
 
 -1245 v ■» 
 
 PIN NO. 
 1 - HEATER 
 2— CATHODE 
 3— CONTROL GRID 
 4— FOCUSING ELECTRODE 
 5— DEFLECTING ELECTRODE D4 
 
 7— PATTERN ADJUSTMENT ELECTRODE 
 
 8— DEFLECTING ELECTRODE D3 
 
 9— ACCELERATOR 
 
 10- DEFLECTING ELECTRODE Dl 
 11— ASTIGMATISM ELECTRODE 
 12- DEFLECTING ELECTRODE D2 
 14— HEATER 
 
 Figure 5. CRT Circuit 
 
15 
 
 The 5D3P-16 meets all of the above requirements in addition 
 to having a small deflection factor (25 to 35 volts DC/inch) , permitting 
 fully transistorized deflection circuitry. The complete layout of the 
 CRT is shown in Figure 5. 
 
 The CRT employs a linear post-accelerator (a spiral resistance 
 •winding) which is set to +3^25 volts. The cathode is held at -1175 volts, 
 giving a total accelerator potential of hGGO volts. Both the positive 
 and negative high voltage supplies exhibit excellent regulation and low 
 ripple. The three independent +500 volt supplies, which are used for 
 the accelerator, pattern adjustment, and astigmatism electrodes, are 
 obtained from the +3^-25 volt supply through three resistor divider 
 networks . 
 
 The unblanking pulse is AC coupled to the control grid of 
 the CRT through the ,01/< f capacitor and the 20 k resistor. The 
 intensity of the unblanked spot is adjusted with the wiper arm of the 
 25 k potentiometer. 
 
 The choice of Pl6 phosphor in the CRT had a direct effect 
 on the type of light detector used. The sensitivity of semi-conductor 
 light detectors in the vicinity of 3&00A. (the wavelength of peak 
 spectral-energy emission of Pl6 phosphor) is only a small fraction of 
 their peak sensitivity. Consequently, because of their poor response 
 to the blue rich Pl6 phosphor, semi-conductor devices were ruled out. 
 
 Photomultiplier tubes were considered next. The wavelength 
 of maximum spectral response of photomultipliers varies from 3300 A. 
 
16 
 
 ANODE 
 
 CATHODE 
 
 20 K 
 45 v 
 
 16 K 
 
 33 K 
 
 33K 
 
 33K 
 
 33K 
 
 33K 
 
 33K 
 
 33K 
 
 33K 
 
 33 K 
 
 TO 
 DETECTION 
 
 10 K CIRCUIT 
 1/4 W 
 
 T 
 
 .01 /tf 
 
 ALL RESISTORS 1/2 W , 
 5% CARBON UNLESS 
 OTHERWISE SPECIFIED 
 
 Figure 6. Photomultiplier Circuit. 
 
17 
 
 (S-19) to 8000 A. (S-l) . Spectral response type S-U was deemed the 
 closest match to the spectral-energy emission type Pl6. Of the tubes 
 having this type of response, the RCA 931A was selected as suitable for 
 the slide scanner system. The complete layout of the photomultiplier 
 is shown in Figure 6. 
 
 The positive high voltage terminal is grounded in order that 
 the output signal will be developed between the anode and ground. This 
 method prevents power supply fluctuations from being coupled directly 
 into the output circuit. 
 
 The voltage at the photocathode is -1170 volts. The successive 
 
 stages of the photomultiplier are operated at voltages increasing in 
 
 th 
 equal steps from the photocathode to the 9 dynode. The voltage 
 
 between the 9 dynode and ground is 60 volts. This insures that the 
 
 th 
 voltage between the 9 dynode and the anode will be just sufficient 
 
 to give anode current saturation. This point on the anode character- 
 istic curve corresponds to a voltage of about 50 volts. Low operating 
 
 th 
 voltage between the 9 dynode and the anode reduces the dark current 
 
 due to leakage paths and also reduces the ion bombardment of the 
 
 dynodes. As a result, the operating stability of the photomultiplier 
 
 is improved without sacrifice in sensitivity. 
 
 2.3 Differential Amplifier - Linear Analysis 
 
 The basic topology of the differential amplifier is shown in 
 Figure 7. It is a standard NPN differential amplifier with a constant 
 
18 
 
 V,» 
 
 Figure 7. Differential Amplifier for Linear Analysis 
 
 current sink used to improve the drift and the common-mode rejection 
 ratio. A common emitter resistor, R , has been inserted to provide an 
 efficient method of gain adjustment. 
 
 A variable gain control "was desirable for two reasons. First, 
 ■with the inputs to Paramatrix set so that magnification = 1 and trans- 
 lation and rotation = 0, the raster pattern on the CRT tube face is to 
 be 2" x 2" (since the input slides are 2" x 2") . Thus, standard 
 resistance values could be used for R and r with the required gain 
 precisely attained by adjusting R . Second, if it were necessary to 
 replace the CRT, it is likely that the new CRT would have slightly 
 
19 
 
 different deflection factors. The small gain change could be made by 
 
 resetting R . 
 g 
 
 In the following linear analysis we assume ideal transistors 
 (a = 1 and v = 0) in order to derive general circuit equations and to 
 determine the constraints that are to be met at various points in the 
 circuit. 
 
 The voltage transfer equation is easily derived „ From 
 Figure 7: 
 
 \ + r(i l " V " r(i 2 + ± r ) + V 2 = ° 
 
 (2.1) 
 
 l 
 
 (v x - v 2 ) 
 
 g R 
 
 (2,2) 
 
 X l + X 2 = L 
 
 (2.3) 
 
 Combining equations (2,1) and (2.2) we obtain 
 
 X l - X 2 
 
 1 2 
 
 T + R 
 
 (v x - v 2 ) 
 
 (2.U) 
 
Considering the collector circuit, 
 
 v Q = -Ri + E - E + Ri 
 
 Thus, from equations (2^) and (2.5) ve have 
 
 -R . 2R 
 
 20 
 
 v Q = E{± 1 - i 2 ) (2.5) 
 
 *o-<f*r> (v i' v 2 ) < 2 - 6 > 
 
 The constant current sink is provided by an NPN transistor 
 vith a constant base-emitter bias. To insure a distortion-free output 
 ve must guarantee that v is above the base-emitter bias for all 
 possible input combinations. From Figure '(: 
 
 v = -r(i. - i ) + v. (2.7) 
 
 r 1 g 1 
 
21 
 
 Using (2,2), (2.3), and (2.4), equation (2.7) becomes 
 
 » r -5<*i + ' 2 >-r (2 ' 8) 
 
 Thus, the minimum value of v will occur at 
 
 ' r 
 
 v = - (v + v ) - — (2.9) 
 
 r min 2 K 1 2 ; min 2 v y > 
 
 Transistors T, and T~ are operated in the active region. 
 We first investigate the conditions under -which T (or T ) can be cut 
 off. Because of symmetry ve consider only i.. . Equations (2.3) and 
 
 (2.4) yield 
 
 Gb + y<'i- T 2> (2 - 10) 
 
 I 
 
 11 - * - -* 
 
 The minimum value of L occurs vhen v_ = v n . , v^ = v^ , and 
 
 1 11 mm 2 2 max 
 
 R = R . . Thus, equation (2.10) becomes 
 g g min 
 
 i + fe + rVlW-ia-'a-J (2 - u) 
 
 1 min 
 
 g mm 
 
22 
 
 Using equations (2.6) and (2.9)., we may express the double-ended 
 voltage gain of the differential amplifier as a function of R, R , 
 
 o 
 
 I, (v n + v ) . , and 
 '1 2 mm 
 
 r mm 
 
 R 
 
 « 
 
 v n + vj . - 2v 
 1 2 mm r mm 
 
 2 
 
 (2.12) 
 
 The ratio, , indicates the degree to -which the voltage 
 
 mm 
 
 gain may be varied by the potentiometer, R . From equations (2.9) > 
 (2.11), and (2.12) we obtain 
 
 max 
 
 mm 
 
 r 2i . - I 
 
 1 mm 
 
 v, . - v_ 
 
 . 1 mm 2 max _ 
 
 [rr^r 
 
 ~^J~. r ~2v' ~T" R 
 2 mm r mm g max 
 
 (2.13) 
 
 Voltages v and v observe the following inequalities: 
 
 ■10 < v ± < 10 
 
 -2 < v 2 < 2 
 
 (2.14) 
 
23 
 
 The lowest practical base -emitter bias for the constant current sink 
 
 is -20 volts, using established Paramatrix voltages. Thus, ve have 
 
 for v n , v_ , v_ , and v . : 
 1 mm' 2 max 2 mm' r mm 
 
 v- „ = -10 
 1 mm 
 
 2 max 
 
 v = -2 
 2 min 
 
 v . = -18 
 
 r mm 
 
 Current i n , is set to 1 ma -. 
 1 mm 
 
 Equation (2,13) raay nov he rewritten as 
 
 (2.15) 
 
 G 
 
 To get a feeling for how the ratio , varies -with the 
 
 mm 
 
 constant current, I, ve set R = «>, Table 1 lists values of 
 
 g max 
 
2h 
 
 max 
 
 G . 
 
 mi a 
 
 as a function of 1, including the corresponding values of r and 
 
 R . as calculated from equations (2.9) and (2.1l) 
 g min 
 
 I (ma) 
 
 C 
 
 max 
 
 G . 
 min 
 
 r (kfi) 
 
 R . (k fi) 
 
 g mm 
 
 5 
 
 1.20 
 
 i+,8o 
 
 ^8.0 
 
 7 
 
 1.43 
 
 J>M 
 
 16 c 
 
 10 
 
 1,60 
 
 2M 
 
 8.00 
 
 15 
 
 l^k 
 
 1.60 
 
 k-57 
 
 20 
 
 1,80 
 
 1.20 
 
 Jc00 
 
 50 
 
 1.37 
 
 „8o 
 
 1.85 
 
 50 
 
 1.92 
 
 .h8 
 
 17.03 
 
 Table 1. Effect of Constant Current on Gain Variation. 
 
 It -was decided that a constant current of 20 ma provided 
 good gain variation while at the same time not causing excessive power 
 to be dissipated. For a CRT accelerating potential of ^600 volts it 
 was found that a gain of approximately 3°5 was needed to obtain a 
 2" x 2" raster pattern on the CRT tube face. 
 
25 
 
 With R implemented by a 3k resistor plus a 5k potentiometer, 
 
 D 
 
 it may be verified with equation (2,6) that setting R = 2-7" k "Will 
 result in a gain variation of about 3 "to h . The supply voltage, E, 
 required to prevent saturation of T, (or T ) is determined as 
 follows: 
 
 E - Ri n > 10 
 
 1 max — 
 
 E > 10 + (2.7 x 10 5 ) (19 x 10" 5 ) 
 
 E > 6l.k volts 
 
 A supply voltage of 75 volts "was chosen for the amplifier. A schematic 
 of the complete differential amplifier used in the slide scanner system 
 is given in Figure 8. 
 
 2 A Gating Pulse Generator 
 
 It was pointed out in Section 2.1 that there was need for a 
 circuit capable of generating a delayed gating ;pulse to" switch the 
 ramp on and off. This circuit, shown in Figure 9, produces a 2 us 
 pulse every clock cycle approximately 2.5 us after the clock has gone 
 from a "0" (-5 volts) to a "1" (0 volts). The reader is referred back 
 to Figure h for a timing diagram of the clock, gating pulse, and ramp. 
 
26 
 
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 T 3 : 2N1613 
 
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 Figure 8. Differential Amplifier for Slide Scanner. 
 
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 Assume that the clock has "been at -5 volts for several 
 microseconds. The base of T has been brought below 10 volts and 
 T is on. The collector of T has risen to 6 volts causing T to 
 turn off. The base of T, sees -25 volts through 27 k so T. is 
 saturated. Thus the output is at volts. 
 
 When the clock goes from -5 volts to volts, the "base of 
 T rises to 11. h volts and T is cut off. With both T and T off, 
 the 510 pf capacitor charges from 6 volts to -25 volts through the 
 5.1 k resistor and the 25 k potentiometer. It takes 2.5 yus for the 
 base of T to reach volts at which time T saturates. The 
 collector of T abruptly changes from -10 volts to volts and 
 this 10 volt change is transmitted across the 250 pf capacitor to 
 the base of T. . T. is turned off and the output goes to -5 volts. 
 Simultaneously, the 250 pf capacitor charges from 10 volts to 
 -25 volts through the 27 k resistor. In approximately 2^s the base 
 of T, reaches volts, thus saturating T, . The output then returns 
 to volts. 
 
 When the clock goes from volts to -5 volts, T is turned 
 on, the collector of T rises to 6 volts, and T„ is cut off. The 
 collector of T heads toward -10 volts with a time constant determined 
 by the 250 pf capacitor and the 1 k resistor. This negative change 
 does not affect the base of T, and the output remains at volts. 
 
29 
 
 2.5 Linear Ramp and DC Balance 
 
 In order to provide for variable sensitivity in the horizontal 
 direction, a circuit was designed which generates a linear ramp (symmetric 
 about volts) -whose magnitude is continusously adjustable from volts 
 to a -2 volt to a +2 volt swing. The output of this circuit is added 
 to a. DC voltage through a resistor summing network, and the sum is 
 fed to one of the inputs of a differential amplifier (for horizontal 
 deflection.) The DC balance is used to center the raster pattern in the 
 horizontal direction. The complete linear ramp and DC balance circuit 
 is shown in Figure 10 . 
 
 The input to the circuit is the gating pulse which switches 
 from volts to =5 volts to initiate the ramp and from -5 volts to 
 volts to terminate the ramp. If the gating pulse has been at volts 
 for several microseconds, the base of T p nas risen above -5 volts and 
 T_ is saturated. The constant current of 1.5 ma supplied by T, 
 flows through T p , Thus, the output of Tk is slightly below -5 volts. 
 A fraction of this voltage (as determined by the 10 k potentiometer, 
 the horizontal sensitivity control) is added to the DC balance voltage 
 (set by the 1 k potentiometer) and the sum (attenuated by a factor of 
 1/2) feeds the emitter follower T . 
 
 If the gating pulse switches from volts to -5 volts, the 
 base of T p tries to go to -8 volts. However, because of the relatively 
 long storage time of the 2N1308, T does not turn off until about 
 200-300 ns after the gating pulse has gone from volts to -5 volts. 
 
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 Thus the start of the ramp is delayed some 200-300 ns after the leading 
 edge of the gating pulse. This delay is necessary and is explained in 
 Section 2.1 The delay was shown in Figure 3 as being separate from 
 the ramp and DC balance circuit for the sake of clarity. 
 
 With T turned off the constant current of 1.5 ma switches 
 from T and begins to charge up the 150 pf capacitor. The capacitor 
 voltage increases linearly from -5 volts until T, saturates. The 
 voltage at which T, saturates is adjusted by the 250 potentiometer 
 so that the ramp swing is symmetric about volts. 
 
 If the ramp circuit input switches from -5 volts to volts, 
 T saturates as explained previously and the output of T, returns to 
 -5 volts. 
 
 2.6 Oscillator and DC Balance 
 
 Variable sensitivity in the vertical direction is achieved 
 by superimposing a h MHz sinusoid on Y. . . A free running Colpitts 
 oscillator, shown in Figure 11, generates the sinusoid. The output 
 of the oscillator is added to a DC offset voltage and the sum is fed 
 to one of the inputs of a differential amplifier (for vertical 
 deflection) . The DC balance centers the raster pattern in the 
 vertical direction. 
 
 The Colpitts oscillator is of the tuned collector type, with 
 emitter feedback through the 1 k potentiometer to the capacitor divider 
 
32 
 
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 network. Both the capacitors together determine the effective capacity 
 against which the 18 p.h inductor resonates. The output, is taken off the 
 secondary winding on the tuned collector. The loop gain is varied by 
 the 1 k potentiometer to obtain optimum linearity. 
 
 2.7 Detection Circuit for Protective Unb tanking System 
 
 It was mentioned in Section 2.1 that the Pl6 phosphor used in 
 the slide scanner CRT could be easily burned if the spot remained in 
 any position for many clock cycles. For this reason, the detection 
 circuit shown in Figure 12 was designed to indicate whether or not the 
 voltages at the deflection plates of the CRT were changing. There are 
 four such detection circuits, one for each deflection plate. Normally, 
 at least one of the four deflection plate voltages will undergo a 
 3 volt (or more) transition every 320 us (corresponding to one column 
 scan) . This circuit responds to negative going transitions of 2 volts 
 or more . 
 
 Emitter follower T_ buffers the detection circuit from the 
 
 i 
 
 deflection plate. The base of T is DC biased above -15 volts and T 
 
 remains saturated and T, is off. The base of T. sees 25 volts through 
 
 3 n 
 
 several k so T. is saturated. Thus, the output is at -5 volts. 
 
 If a negative transition occurs, a short negative pulse 
 appears at the base of T . Ihis turns off T for a few microseconds 
 and T saturates, thereby cutting off T, . The base of T sees 10 volts 
 
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 through 20 k so TV is saturated. Thus the output goes to volts. After 
 
 the negative pulse at the base of T p has passed, T„ saturates, cutting 
 
 off T, . The .1 uf capacitor charges from -10 volts to 25 volts through 
 3 
 
 the 1 k resistor and the 25 k potentiometer - The 25 k potentiometer 
 is set so that the base of T. would reach -5 volts in approximately 
 350 us. If the input does not experience another negative going tran- 
 sition within 350 us, T. saturates and the output goes to -5 volts. 
 However, if this change does occur, T is again turned off and T sat- 
 urates, bringing the base of T, down to -10 volts before Tj. saturates. 
 The output remains at volts. 
 
 2.8 Photomultiplier Detection Circuit 
 
 Light inpinging on the photo sensitive cathode of the 931A 
 photomultiplier tube generates current in the anode output circuit. 
 In this manner incident light produces negative voltage pulses across 
 the 10 k load resistor, as shown in Figure 6, These voltage pulses 
 are AC coupled into the detection circuit given in Figure 13 . 
 
 Transistors T and T serve to amplify the input signal 
 by a factor of 3 and tend to isolate the base of T from spurious 
 low level input signals generated by small amounts of ambient light. 
 The Ml uf capacitor across the 1 k resistor holds the emitter of 
 T, fixed at -.8 volts as far as pulses are concerned. The collector 
 of T, is normally at about 1 volt. 
 
36 
 
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 A negative pulse at the base of T, cuts T off and the 
 
 3 3 
 
 collector rises to 10 volts. Transistor T_ is quite sensitive, and 
 any noise that appears at the base of T causes small positive pulses 
 to be present at the collector . For this reason diode D and the 10 k 
 potentiometer are used to form an amplitude-discriminating circuit 
 for the pulses at the collector of T,. The -wiper arm of the potentio- 
 meter is set to approximately 5 volts, thus rejecting all small 
 positive pulses that appear at the collector of T . The 6.2 volt 
 Zener diode level shifts the pulses which exceed 5 volts to provide 
 for proper triggering of the flip-flop. 
 
 The memory is a standard flip-flop with catching diodes to 
 form a compatible logical output . A positive trigger at the base of 
 T. turns T. off, and the output signal to Paramatrix goes to -5 volts. 
 As mentioned in Section 1.2, a logical "0" means light the bulb. 
 
 The clock input is differentiated by the high-pass RC circuit, 
 and the negative peaks are clipped off by diode D , Thus, only the 
 positive triggers reach the base of T , resetting the flip-flop at the 
 beginning of every clock cycle. 
 
38 
 
 3. CONCLUSION 
 
 A special purpose flying- spot slide scanner has been designed 
 to provide an efficient and flexible means for transmitting an input 
 pattern to Paramatrix. Voltages generated by the Paramatrix computer 
 position the light spot cf a CRT opposite a test point on the slide, 
 and hybrid circuits are used to sweep the spot over a rectangular 
 area symmetric about the test point. The size of the rectangle can 
 be varied by horizontal and vertical sensitivity controls. The 
 presence of light behind the slide is detected by a photomultiplier, 
 and an appropriate logic signal is generated which is used to either 
 light or not light a bulb in the output matrix. 
 
 The slide scanner system presented in this thesis has been 
 built and is operating well. By adjustment of the horizontal and 
 vertical sensitivity controls, the slide input pattern can be displayed 
 and manipulated on the output matrix with a minimum of flicker. 
 Photographs of the experimental slide scanner set up are shown in 
 Figure ik. 
 
 It was mentioned in Section 1.2 that the ultimate solution to 
 the problem of providing an input pattern for Paramatrix reduces to 
 that of having 128 autonomous analog storage cells which receive their 
 analog information from a slide scanning system. Currently under 
 development by members of Task 15 is a reliable, low cost analog storage 
 

 Figure lU. a.) Experimental Setup 
 
 Figure Ik. b.) Typical Output Pattern 
 
>+0 
 
 system called Phastor. The storage element is a monostable multivibrator 
 ■which is triggered by the coincidence of the analog voltage to be 
 stored with a sawtooth ramp voltage. It is felt that in the near 
 future the Phastor system of analog storage may result in a realization 
 of the ultimate solution for" providing an input pattern to Paramatrix . 
 
Ul 
 
 BIBLIOGRAPHY 
 
 G.E. Transistor Manual , Cleary, J. F., Editor. General Electric 
 Company, I96U. 
 
 "Graphical Processing Using Hybrid Analog-Digital Circuitry", 
 
 Casasent, D. P., Report No. 187, Department of Computer 
 Science, University of Illinois, Urbana, Illinois, 
 August 30, 1965. 
 
 "Hybrid Circuits for the Paramatrix System", Prozeller, E. F., 
 
 Report No. 188, Department of Computer Science, University 
 of Illinois, Urbana, Illinois, September 7, 19&5 • 
 
 Phototubes and Photocells , Technical Manual PT-60, Radio Corporation 
 of America, 1963. 
 
 Pulse, Digital, and Switching Waveforms , Millman, J., and Taub , H., 
 McGraw-Hill, 1965. 
 
 "Quarterly Technical Progress Report", (Circuit Research Program), 
 Department of Computer Science, University of Illinois, 
 Urbana, Illinois, April-June, 1966. 
 
 "Quarterly Technical Progress Report", (Circuit Research Program), 
 Department of Computer Science, University of Illinois, 
 Urbana, Illinois, October-December, 1966. 
 
 "Quarterly Technical Progress Report", (Circuit Research Program), 
 Department of Computer Science, University of Illinois, 
 Urbana, Illinois, January-March, 1967. 
 
 "Quarterly Technical Progress Report", (Circuit Research Program), 
 Department of Computer Science, University of Illinois, 
 Urbana, Illinois, April- June, 1967. 
 
 Semiconductor Circuit Design , Watson, J., D. Van Nostrand Company, Inc., 
 1966. 
 
 _o 
 
 "A Transistor Coincidence-Discriminator Circuit for 10 Second 
 
 Pulses", Baker, S. C, Nuclear Instruments and Methods, 
 Volume 12, I96I. 
 
Unclassified 
 
 Securitv Classification 
 
 DOCUMENT CONTROL DATA - R&D 
 
 (Secunly cUmmlHcmllen of Mil*, body ot abstract and „■«*»«.,.« anno-nt,on must be entered «hen the overall report ,. cla«t.f..dj 
 
 I ORIGINATIN G ACTIVITY (Corporefe author) 
 
 Department of Computer Science 
 
 University of Illinois 
 
 Th-bana, Illin ois 6l801 
 
 3 REPORT TITLE 
 
 Z« »epor t security classification 
 
 Unclassified 
 
 Zb group 
 
 A SIXDE SCANTIER IHPUT FOR PARAMATRIX 
 
 4 DESCHlPTIVE NO T ES (Type of report and inclusive dates) 
 
 te chnical Report 
 
 S AUTHOR^ fi.»si nam? Hral n«i», Initial) 
 
 Ryan, Lawrence 
 
 6 REPO RT DATE 
 
 August, 196T 
 
 8a CONTRACT OR CfiANT NO 
 
 1 » ^OTAL NO OF PAGES 7b. NO. OF REFS 
 
 Nonr 183^ (15) 
 
 6. PROjECT NO . 
 
 -^ 
 
 JUL 
 
 9a. ORIGINATOR'S REPORT NUMBERfS) 
 
 9 6. OTHER REPORT f40(S) (A ny other numbers ttiat may be assigned 
 th>3 report) 
 
 None 
 
 10. AVAILABILITY/LIMITATION NOTICES 
 
 11 SUPPLEMENTARY NOTES 
 
 Hone 
 
 I 12 SPONSORING MILITARY ACTIVITY 
 
 Office of Naval Research 
 J 219 South Dearborn Street 
 Chicago, Illinois 6o6C4 
 
 13 ABSTRACT 
 
 A special purpose flying-spot slide scanner has been designed to provide an 
 efficient and flexible means for transmitting an input pattern to Paramatrix, a 
 pattern processing computer. The light spot of a CRT is positioned by the "hori- 
 zontal" and "vertical" outputs of the Paramatrix Transformer opposite a test 
 point on the input slide. The presence or absence of light behind the slide is 
 detected by a photomultiplier, and an appropriate logic signal is generated -which 
 is used to' either light or not light a bulb in the output matrix. 
 
 Variable horizontal and vertical sensitivity controls have been incorporated 
 into the scanner system. In this manner test points that are "near" line seg- 
 ments of the input pattern are considered to be part of the input pattern. This 
 feature allows for thinning and thickening the lines of the output pattern. 
 
 
 Unclassified 
 
 Security Classification 
 
Unclassified 
 
 Security Classification 
 
 14 
 
 KEY WORDS 
 
 LINK A 
 
 ROLE «T 
 
 LINK C 
 
 Paramatrix 
 
 Slide Seamier Input 
 
 Variable Gain Differential Amplifier 
 
 INSTRUCTIONS 
 
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 c :*.. /-l„...,:f:~«ti^-_ 
 
 =ZJ