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Report No. 30I 
 
 
 1 
 
 - * 
 
 FUNCTIONAL DEVICE MODELS AND COMPUTER AIDED CIRCUIT DESIGN 
 
 by 
 Gary R. Guth 
 
 December 1, 1969 
 
 LIBRARY OF: THE 
 
 NOV 9 1972 
 
 UNIVERSITY Of (IXWOI'-- 
 AT UR9Af- »<MG^ 
 
 DEPARTMENT OF COMPUTER SCIENCE 
 UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAI 
 

Report No. 361 
 
 FUNCTIONAL DEVICE MODELS AND COMPUTER AIDED CIRCUIT DESIGN* 
 
 by 
 Gary R. Guth 
 
 December 1, 1969 
 
 Department of Computer Science 
 University" of Illinois 
 Urbana, Illinois 6l801 
 
 This vork was submitted in partial fulfillment of the requirements for 
 the degree of Master of Science in Electrical Engineering, January 1970. 
 
iii 
 
 2- ACKNOWLEDGEMENT 
 
 The author acknowledges with pleasure the assistance and 
 encouragement of Professor Thomas A. Murrell whose suggestions 
 contributed much to this thesis project. 
 
 Thanks are also due to the secretarial staff of the Department 
 of Computer Science for typing the manuscript and to the drafting staff 
 for drawing the figures. 
 
TABLE OF CONTENTS iv 
 
 Page 
 
 1. INTRODUCTION 1 
 
 2. TRANSISTOR MODELS 5 
 
 3. SINGLE TRANSISTOR CIRCUIT 15 
 
 U. MULTIPLE TRANSISTOR CIRCUITS 3^ 
 
 5. THE EFFECT OF ADDING TEMPERATURE k"J 
 
 6. A GENERAL LINEAR CIRCUIT ANALYSIS PROGRAM 52 
 
 7. A GENERAL NON -LINEAR CIRCUIT ANALYSIS PROGRAM TO 
 
 8. CONCLUSIONS 86 
 
 LIST OF REFERENCES 89 
 
 APPENDIX 90 
 
1. INTRODUCTION 
 
 The transistor and all other semiconductor devices are 
 essentially non-linear devices. These non-linear characteristics 
 can be shown to be functionally dependent on variables which are 
 external to the device itself. These external variables may be the 
 terminal voltages, the terminal currents, temperature and possibly some 
 of the other external phenomena such as light or gamma ray radiation. 
 Although it is possible to ignore the non-linearities and assume certain 
 quantities to be constant, any predicted results are likely to be 
 inaccurate. For reasonably complex circuits where results are not 
 extremely critical and the hand calculation time might make the non- 
 linear approach prohibitive, it is possible to use constant values of 
 the device parameters during design and provide some means of adjusting 
 the completed circuit to the desired operating point. However, as 
 techniques and the industry have progressed to new refinements such as 
 integrated circuits which operate with very small signals, more accuracy 
 has become necessary. 
 
 The widespread use of digital computers has resulted in a number 
 of circuit analysis programs being developed which are capable of some 
 modeling technique for semiconductor devices and other non-linear 
 devices. Although some of these programs allow only very limited model 
 simulating capabilities, others allow some extremely complicated models 
 to be simulated. Generally, the more complex a model becomes in terms 
 of non-linear interrelationships the more complex the method of solution 
 becomes, requiring larger, faster computers to implement them success- 
 fully. 
 
The purpose of this paper is to investigate an unusual approach 
 to the problem of modeling non- linear semi-conductor devices in a circuit 
 analysis program. In general solving a circuit containing non-linear 
 elements requires the solution of non-linear equations which is usually 
 a rather difficult process. On the other hand, the solution of linear 
 circuits requires solving linear equations which is a relatively easy 
 task. The method developed in this paper introduces the non-linear 
 characteristics in a subroutine isolated in such a way that the main 
 circuit analysis program can retain the simplicity inherent in a linear 
 network analysis routine. 
 
 There are two methods which can be used to model a device. 
 (The device may or may not include some external elements. ) The first 
 method might be termed the theoretical approach. In this approach, a 
 model is derived from the theoretical basis of the device. That is, 
 it may be known from the laws of physics that internally the Q value 
 is an exponential function of P + R. Therefore, the model may contain, 
 in addition to other factors, a Q value which is some exponential 
 function of P + R and possibly some constant. In theory, this type 
 of model should be excellent, but usually it is no better than the theory 
 behind the device. Naturally, it is best to be firmly grounded on the 
 theory of the device before any theoretical models are made for it. 
 The silicon transistor is a good example of this problem. From time 
 to time a new article appears to help explain the theory behind this 
 device which continues to work anyway. 
 
 On the other hand, the second method does not necessarily require 
 a good theoretical knowledge of the device. Instead the model is devised 
 
by observing the device in terms of its external environment. 
 Essentially, this method may be thought of as an "outside looking in" 
 model, whereas the theoretical model would be an "inside looking out" 
 model. For example, it may be observed that by counting the number 
 of cricket chirps in a minute (from a single cricket) on a summer 
 evening and then adding a predetermined constant to this, the tempera- 
 ture in degrees Farenheit may be determined with reasonable accuracy. 
 This is a purely empirical approach; the constant and hence the "model" 
 can be determined by observing crickets and counting chirps from a large 
 sample of crickets while simultaneously noting the temperature. It is 
 not necessary to dissect the cricket and from its internal structure 
 attempt to find a theoretical connection between the rate of chirping 
 and the temperature. On the other hand, some knowledge of the habits 
 of crickets and the chirping mechanism may be useful when a choice is 
 made of the appropriate mathematical expression relating the chirping 
 rate to the temperature. Once the choice has been made, the expression 
 is used empirically. 
 
 For the purposes of this paper the second modeling technique 
 will be used in an attempt to find a reasonable non-linear model for 
 the transistor. Once this model is determined and is reasonably well 
 defined the problem of solving the resulting non-linear equations will 
 be undertake 
 
 Rather than tackle the many problems which could arise by 
 attempting to produce immediately a generalized approach to. solving 
 
 non-linear equations, the task will be handled in progressive 
 steps. First, the problem will be studied for the simplest possible 
 
k 
 
 case to gain some insight into problems which can be expected when 
 further complexities are introduced. The next step will be to introduce 
 new complexities by handling more complicated and interdependent circuits. 
 Finally, generalization of the techniques will be accomplished. 
 
 Once the generalized solution is obtained, we will return to the 
 original model and attempt to refine it. With these new refinements the 
 generalized solution will be re-examined. 
 
2. TRANSISTOR MODELS 
 
 The transistor, like the vacuum tube, is a non-linear devic< 
 and since it is capable of gain it car. be defined as a "non-linear 
 active device". The purpose of a model or an equivalent circuit is to 
 provide a useful algorithm for the prediction of the performance of 
 the device. It follows that the degree of required complexity depends 
 primarily upon what sort of performance is to be predicted. 
 
 There are three different points of view influencing the choice 
 of models or equivalent circuits. First, the device designer wants an 
 equivalent circuit which he can relate easily to semiconductor physics. 
 Second, there is the device manufacturer who wants to use an equivalent 
 circuit whose parameters can be easily and inexpensively measured and 
 controlled in the manufacturing process. Third, is the circuits 
 engineer who must handle this equivalent circuit continually and who 
 naturally wants to use parameters fitting conveniently into his circuit 
 design. These parameters should be easy to measure and, if possible, 
 be readily obtainable from the commonly used graphical characteristics. 
 He is also interested in controls and limits to these parameters 
 relating directly to his circuit's performance. 
 
 As a result of these varying interests, several equivalent 
 circuits have been developed over the years. Some of these have 
 retained their importance in modern transistor circuit analysis, others 
 have become less used. The important thing is that each model attempts 
 to describe and accurately synthesize the semiconductor device it 
 represents operating in a given circuit application. The simplest 
 case is that of small-signal performance in the active region and at 
 
6 
 low frequency. Here, one can deal with linear parameters; the non- 
 linear properties of the device show up only as a dependence of the 
 numerical values of the parameters upon the d.c. operating point. 
 
 Next in complexity is the d.c. problem, that is, the calculation 
 of d.c. currents and voltages for a given bias circuit arrangement, 
 including the case of a direct-coupled amplifier. Here, one must in 
 some way take into account the non-linearity of the transistor. In 
 principle, a satisfactory solution to this problem can be extended to 
 the simple small- signal problem by straightforward means. 
 
 The most complex case is that of large- signal switching, 
 particularly when the range of operation swings from cut-off, through 
 the active region, and into the saturation region. Not only must the 
 model represent all three regions with sufficient accuracy, but one 
 must also take into account transient effects. This paper will consider 
 only the d.c. problem. Extension of the method to the switching 
 problem appears to be feasible. 
 
 To begin, consider the method of describing the h-parameter 
 equivalent circuit for small signals. This is essentially an attempt 
 at black box modeling, that is, treating the transistor as a two port 
 network and describing its contents by making a.c. measurements at 
 the terminals only. In general, these parameters are the most commonly 
 used for describing the small-signal characteristics of the transistor. 
 Referring to Figure 1, they are defined as: 
 
 V l " h ll h + h 12 V 2 
 
l 2 = h 2l l l + h 22 V 2 
 
 where the lower case v and i represent a.c. voltage and current. 
 
 The measurement of these parameters may be done as follows. When 
 the output terminals are shorted, Vp = and: 
 
 h ll = V 1 ! 
 
 h 21 = 
 
 A 
 
 Similarly, when the input terminals are open circuited i = and: 
 
 12 = V V 2 
 
 h 22 i - 
 
 ^ 
 
 u 
 
 ■EX 1 
 
 Figure 1. h-parameter equivalent circuit 
 
 If the common terminal of this model is considered to be the 
 
8 
 emitter of a transistor, the positive input to be the base, and the 
 positive output to be the collector, we have a familiar transistor model. 
 The IEEE standard nomenclature for the parameters, when used in the 
 common emitter configuration, renames the parameters as follows: 
 
 h. = h,. 
 ie 11 
 
 hre = h 
 
 12 
 
 h fe = h 21 
 
 h oe " h 22 
 
 When the model is used in the common base configuration the e's 
 change to b's and the values also change. The same comment holds true 
 if the model is used in the common collector configuration. However, 
 given a set of parameter values in one configuration, a set of transfor- 
 mations exist to obtain the parameters in either of the other two 
 configurations. Because these parameters are easily measured and 
 transformed, they are commonly given in transistor specifications. The 
 advantage in using this model lies in the ease of obtaining data. 
 Unfortunately, the model is essentially linear and is valid only under 
 small signal variations where the linear approximation is a reasonable 
 one. There are a number of other linear models which may be derived in 
 a similar fashion by working with impedance matrices, conductance 
 matrices, etc. These may be shown to be equivalent to the circuit of 
 Figure 1 and hence suffer the same shortcomings. 
 
I 
 
 I— 
 
 "le 
 
 v B 3 
 
 I 
 
 CD 
 
 fi'i 
 
 'oe 
 
 -o^- 
 
 U 
 
 V 
 
 cr 
 
 i 
 
 lr 
 
 Figure 2. Common emitter piecewise linear model 
 
 One of the simpler approximations for d.c. calculations is the 
 ewise linear model shown in Figure 2. The similarity to the small 
 signal circuit of Figure 1 is apparent. Two of the parameters, h. and 
 h , are usually taken to have the same value as the corresponding small 
 signal parameters. The d.c. voltage source, V„, is added to account 
 the fact that V , the total d.c. voltage, is much larger than 
 
 Dili 
 
 the product I h. , a consequence of the essentially exponential input 
 a le 
 
 characteristic. 
 
 There is some confusion about the remaining parameter, p*. 
 re are two distinctly different betas in common use. The first is 
 small signal version, measured as the short circuit a.c. current 
 amplification for a common-emitter amplifier. Representing a.c. currents 
 as lower case letters and i.e. currents and voltages as upper case 
 letters, this beta can be defined as: 
 
3 = h = -i 
 
 CE 
 
 3l o 
 
 CE 
 
 10 
 
 It can be shown to a very good approximation that: 
 
 3 - 
 
 a 
 
 1 - a 
 
 The second version of beta commonly found on transistor 
 specification sheets is just the ratio of the d.c. currents: 
 
 P DC ~ h fe " I 
 
 E 
 
 For the usual practical case, the numerical difference between 
 3 and 3 ~ is not great, although discrepancies of 10$ are found in 
 silicon. 
 
 Clearly, the beta of Figure 2 is neither of these. Considering 
 the output circuit: 
 
 \ ' V'h + Y cv*. 
 
 oe 
 
 from which we can obtain: 
 
 3' = 
 
 I V h 
 C CE oe 
 
 or: 
 
 3» = 3 
 
 V CE h oe 
 
 DC 
 
11 
 
 In spite of the apparent simplicity of the piecewise linear 
 
 model, it can be used for exact calculations only by overcoming some 
 
 awkward limitations. The beta can be made to agree with p (which is 
 
 usually available) only by replacing the normal h , typically 10 ' mho, 
 
 with something approaching an open circuit or around 10" mho. This 
 
 has the disadvantage of limiting the range over which the calculation 
 
 is usefully accurate, and does not remove the requirement that 3^_ 
 
 must be adjusted to the operating point, which is the value being sought. 
 
 Conditions at the input of the circuit are similar. The total voltage, 
 
 V p, varies with I in a nearly exponential way (see discussion of the 
 
 Ebers-Moll model below). Therefore, both V.. and h. must be adjusted for 
 
 accurate results. The difficulty can often be minimized by replacing 
 
 h. with a very small resistance, 0.1 ohm and concentrating on picking 
 
 the correct value of V by trial and error. For a number of packaged 
 
 B 
 
 computer programs, including ECAP used in this work, some small value 
 of h. (rather than a short circuit) is required, and similarly, h 
 cannot be replaced with an open circuit. 
 
 A more sophisticated approach to the d.c. problem introduces 
 explicitly the exponential relationships between currents and voltages. 
 The most widely used model in this category is the Ebers-Moll model 
 shown in Figure 3« The corresponding equations, written in terms of 
 the open-circuit saturation currents, !L-, n and I , are shown below with 
 the signs chosen to represent a pnp transistor: 
 
 h ' " Vc + ho < e ^ - « 
 
12 
 
 kt" 
 
 * V CB 
 
 h - " Ve + ho < e " V 
 
 If the parameters I -, I , a, , and ql are taken to be constants, 
 these equations represent the first-order theory developed by Shockley 
 in 19^9* Agreement with measured values is very good at low currents, 
 but the accuracy is less than satisfactory at higher currents. As an 
 alternative, the parameters can be adjusted for a better fit for the 
 region of interest, and the equations regarded as empirical. One 
 relation between the parameters can be used to reduce the number of 
 independent values to three: 
 
 "f^s " "e^s 
 
 where I__ and I__, are the short-circuit saturation currents related to 
 
 LjO Ob 
 
 the open-circuit parameters by: 
 
 ho " hs (1 " «fV 
 ^o ■ hs (1 - < W 
 
 For silicon transistors, a further improvement can be effected by 
 introducing a correction factor X, to account primarily for excess 
 generation and recombination in the space-charge regions. The two 
 exponential terms are replaced as indicated: 
 
 * V H> X * V EB 
 
 KT . KT 
 e -* e 
 
13 
 
 q.v 
 
 CB 
 
 KT 
 
 X ^CB 
 KT 
 
 The result of this approach is that V becomes a straight line 
 
 EB 
 
 function of log I . Beta however, is still approximately a constant. 
 
 q v EB 
 
 l' E = I E o(e KT 1) 
 
 Ir s Tr.o(e KT -l) 
 
 Figure 3* Ebers-Moll non-linear model 
 
 The point of view of this paper is based upon an empiric 
 
 of the preceding discussion. Experimental measurements of V 
 
 EE 
 
 show that it is, in fact, not a straight line function of log I.,, but has 
 a moaerat,e curvature. furthermore, it is standard practice for trans, 
 tor specification sheets to display beta plotted as a function of log T-. 
 
14 
 
 Both V^- and beta are functions of temperature. It is therefore 
 
 proposed to find a convenient method of representing V and beta in 
 
 EB 
 
 terms of polynomials of log I , and temperature. The following chapters 
 are devoted to the details of this representation. 
 
15 
 3. SINGLE TRANSISTOR CIRCUIT 
 
 There are two objectives in this part of the paper. The first 
 of these is to develop the loosely defined non-linear model we isolated 
 at the end of Chapter 2 into a more precisely defined model and examine 
 the range for which the model is valid. The second objective is to 
 attempt to use this model in the actual solution of a circuit and 
 hopefully to begin to formulate a method which can be used in any circuit 
 employing such a model. For the purposes of illustration and for the 
 natural simplifications which this arrangement provides, we shall limit 
 the study to that of a single transistor circuit without feedback. The 
 addition of more non-linear elements and the possibility of handling feed- 
 back will be considered in Chapter h. 
 
 The first question which arises in obtaining a more precise 
 definition of our model is whether to limit the model to that of second 
 degree polynomial (parabola) or to allow the polynomial to be of as many 
 terms as desired. To answer this question consider the following 
 arguments. First consider a first degree polynomial, i. e., a straight 
 line, and remember that only two points are needed to define it. The 
 reason is that there are only two coefficients to be evaluated. Simi- 
 larly, for a second degree polynomial we would need three points and so 
 on. Theoretically, to obtain an exact fit through n + 1 data points we 
 would need an n degree polynomial. 
 
 Consider the graphs in Figure h. The first graph is that of a 
 quadratic, the second is that of a quartic. Note that both of these 
 curves go through the same four points. If these are supposed to rep- 
 resent a transistor characteristic such as beta (at least on part of the 
 
16 
 curve) then it is extremely doubtful that the characteristic will contain 
 the dip at the top of the quartic, yet the four data points do lie on the 
 curve. Therefore, it is wiser to hedge in our attempts to carry out the 
 polynomial to a great number of terms to force the curve through a large 
 number of points. Instead, we use the methods of linear regression to 
 handle the curve fitting job after we select the simplest polynomial 
 adequate to simulate our model. For the range we are currently consid- 
 ering, the parabola, or at least a portion of a parabola, will suffice. 
 
 Figure h. Similar polynomials 
 
 If we are going to use linear regression to fit the polynomial 
 to ' ba values we may also take advantage of any data transformation: 
 to improve the fit of the model. Usually, the data given for 
 
17 
 transistors is displayed against the logarithm of the independent 
 variable, in order to display the characteristics over as wide a range 
 as possible while emphasizing the characteristics in the principal 
 operating range. In addition, consider Figure 5 where the base emitter 
 voltage is displayed as a function of both collector current and the 
 logarithm of collector current: it is easier to fit a parabola through 
 the logarithmic dependent function than through the non- logarithmic 
 dependent function. For further comparisons consider Figures 6, 7, 8, 
 and 9 in which the curves representing the measured or actual values of 
 3 and V for the Delco DS-67 are plotted as functions of I and log I , 
 along with the predicted values of (3 and V_,_ which were obtained by using 
 linear regression to find the best fit through the actual points given a 
 second degree polynomial equation. Clearly the fit is better on the 
 logarithmic dependent functions. For a more quantitative comparison, 
 consider Tables 3 -la, b, c, d which are the vital statistics obtained from 
 the linear regressions used for the predicted values in Figures 6, 7, 8, 
 and 9 respectively. Note that in Tables 3-lb and 3-ld where the 
 logarithmic dependence was used, the values for R and R squared are 
 significantly closer to 1.0 than the same values in Tables 3-la and 3-lc 
 which are the corresponding regressions for linear dependence. Similarly, 
 the logarithmic dependent models obtained residuals which were an order of 
 magnitude less than the linearly dependent models. It is obvious for this 
 particular case, that using the logarithm of the collector current results 
 in the better model. This result will not always be true, but what is 
 indicated is that the selection of a particular model can significantly 
 affect the accuracy of calculations made using that model. 
 
 For the transistor the fact exists that L is an exponential 
 
18 
 
 S § i 3 g 
 
 •— in 
 
 ISIS 
 
 6 
 
19 
 
 function of V and therefore I is close to being an exponential 
 
 Br, C 
 
 function of V according to the simple physical device model theories. 
 It follows then, that expressing V_„ as a function of log I„ is a 
 reasonably good choice. Using a second order function in log I takes 
 into account the discrepancies of the device from the simple theory. 
 The argument does not apply to beta at all; according to first-order 
 theory, beta should be a constant. However, the logarithmic dependence 
 of beta on collector current is well known in practice and most transis- 
 tor manufacturers use this method of display. With this consideration the 
 choice of expressing beta as a logarithmic function of collector current 
 is reasonable. 
 
 From the data in Table 1 the parameters of the model are: 
 
 3 = 88.56775 + 11.91306 Log(l c ) + O.56603 Log 2 (l c ) 
 
 V BE = ' 792kl + - 01782 ^ (V " •° 0059 L °g 2 ( I c ) 
 
 At this point we have effectively described a model for the 
 transistor which is similar to the usual non-linear models except that 
 two of the parameters are non-linear. The model is essentially true 
 to the real world over a collector current range of one tenth of a 
 milliampere to forty milliamperes for the DS-67 and this is probably a 
 reasonably good operating range if the transistor is indeed in its active 
 region of operation. Actually the model is oversimplified. Strictly 
 speaking we should also check to see whether or not our two non- linear 
 parameters are possible functions of other variables besides the 
 collector current. We should also check to see if any other parameters 
 are functionally dependent on these same variables. However, it is 
 
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28 
 possible to continue this argument into circles if we are not careful. 
 We might find that beta is a function of the collector to emitter voltage 
 and attempt to add this dependence to our modelo However, assuming that 
 emitter current and collector current are approximately equal we note 
 that the collector to emitter voltage then becomes a function of 
 collector current. 
 
 Now that we have essentially isolated our model we need only 
 figure out how to solve a circuit containing it using only linear 
 circuit analysis methods. From here on in, we will ignore the details 
 of obtaining the parameters of the model and instead concentrate on 
 the problems involved in solving various circuit configurations. For 
 the remainder of this chapter we shall consider a basic common- emitter 
 amplifier. 
 
 The circuit to be considered is shown in Figure 10. We shall 
 assume the transistor to be a Delco DS-67 with a beta of about fifty 
 and a base-emitter voltage of about seven tenths of a volt. This is 
 the transistor we have just modeled and hence we can use the parameter 
 values we just calcaulated. The values of the components in the 
 circuit were calculated using the normal type of analysis, i.e., picking 
 an operating point on a load line, selecting a certain stability factor 
 and so on. Remember, the purpose of the model is for use on a computer 
 in aiding circuit analysis, not circuit synthesis. For this reason we 
 still design the circuit in the usual way. The purpose of the analysis 
 is to offer a detailed study of a given circuit subject to such things 
 as variations in circuit resistances or transistor variations. 
 
29 
 
 E« + 18 E« + 18 
 
 12KSR, R r S 330ft 
 
 4.7K | R 2 R E | 220ft 
 
 Figure 10. Common Emitter amplifier 
 
 If we inserted our model and momentarily regard beta and the "base 
 emitter voltage as constants, we would find: 
 
 p [e- v BE a + yH 2 )] 
 
 c (i + a)R e (i + lyiy + r 1 
 
 where P = P DC = h^ 
 
 This equation is a non-linear relationship since 3 and V__ are both 
 quadratic functions of log I ; therefore a direct linear solution is 
 out of the question. 
 
 Usually when equations of this type are to be solved on a computer, 
 there are two possible methods of solution. One method is the strict 
 
30 
 application of numerical analysis, for example, the Newton-Raphson method 
 or a similar iterative method, and the other would be one of the methods 
 of methodical guesswork, i.e., keep plugging in values of the unknown 
 until the right one turns up. Either method, however, must begin with 
 some sort of approximate result and then work from there toward the 
 actual solution. 
 
 Now glance again at the equation we are trying to solve. It is 
 an equation for I . If we needed an approximation from which to start a 
 solution of either type, we could plug in the nominal values of beta and 
 the base emitter voltage which would give us a nominal collector current. 
 From here we could proceed to use either method outlined previously. For 
 either method, the most likely next step is to check to see what values 
 we would get for beta and the base emitter voltage if we calculate their 
 values with the I~ we just calculated. If the values are the same as the 
 ones we originally used, we have a solution for I_. If not, we use these 
 new values to calculate a new I and try again. Hopefully the process 
 will converge to a solution. The process is generally referred to as 
 the method of successive approximation and is sometimes used to solve 
 simultaneous linear equations where it is impractical to use normal 
 matrix methods. The process as it applies in this case is outlined in 
 the flowchart of Figure 11. 
 
31 
 
 TSTART ) 
 
 Obtain circuit parameters and nominal 
 values of beta and the base emitter 
 voltage 
 
 z 
 
 Calculate a nominal solution for the 
 collector current 
 
 I 
 
 Calculate the beta and base emitter 
 voltage corresponding to the 
 present value of the collector 
 current 
 
 I 
 
 Calculate a new solution for the 
 collector current 
 
 YES 
 
 Print the current solution as the 
 final solution 
 
 I 
 
 Cej 
 
 Figure 11. Flowchart of successive approximation 
 
 The question which now arises is whether the method will always 
 converge to a solution. The question has even more significance when 
 the possibility of adding more transistors exists since circuits are 
 often designed to be self-regulating. These types of circuits, however, 
 usually employ feedback and this topic is investigated in the next 
 chapter. 
 
 The equation under question is of the form: I = f(l r ). For 
 the method of successive approximation to converge, the necessary and 
 
32 
 sufficient condition for convergence is that: 
 
 f'|(l c )| < 1 
 
 in the neighborhood of the root. Unfortunately, even for the relatively- 
 simple circuit under consideration here, the resulting expression for 
 f (I ) is too complicated to spend considerable time evaluating. An 
 easier test for convergence is to try the method on a computer. 
 
 Another interesting question which arises is, "how important are 
 the initial values chosen for the parameters?" To answer this question 
 the program which was written to test the successive approximation 
 approach was written to do the following: start the method with an 
 initial beta cf 10, 20, 30, 1+0 and 50; count the number of iterations 
 required to converge and display the results. There was no need to 
 vary V^- as well, its range of .575 to .725 against a larger voltage 
 won't have nearly as large an effect as varying beta. The results are 
 displayed in Table 3-2. Putting it bluntly, it doesn't appear to matter 
 where you start from. 
 
 P v BE i c f> v BE i c P v^ i c 
 
 no no 700 6 878 20.00 .700 9.651 30.00 .700 1.1. 1^9 
 
 £28 : ? 690 J:3U9 fc*! .69? ^69 %•% •£* *-*g 
 
 k7 lb 70U 12 555 U7.21 .70^ 12.559 ^7.2^ .10k 12.560 
 
 k 7 '26 *70U ll\ Ui U7 26 .70U 12.561 U7.26 .70U 12.561 
 
 .{0U 12.561 U7.26 .70U 12.561 U7.26 .T0U 12.561 
 
 i+o.oo .700 12.087 50.00 .700 12.730 
 
 U7 00 .701. 12.5^8 **7. 36 .705 12.566 
 
 U7 26 .10k 12.561 ^7.27 .70U 12.561 
 
 1+7 '.26 .701+ 12.561 ^7.26 .70U 12.561 
 
 Tnble 3-2. Results of varying initial value of beta 
 
33 
 Simila. riments were tried with circuits operating at 
 different points in the range of the model. The method worked each 
 time, but remember tnat we are still at the single transistor circuit 
 level. In the next chapter, we will test the method on multi-transistor 
 circuits and see what modifications to the method may be required. 
 
& 
 
 k. MULTIPLE TRANSISTOR CIRCUITS 
 
 In the last chapter, we started from scratch to derive a 
 transistor model and some method of solving the resulting non-linear 
 circuit using linear methods. We mentioned at the end of Chapter 3 that 
 problems could arise if dc feedback was present. In this chapter we shall 
 first examine a small multi-transistor amplifier without feedback and then 
 follow up with a feedback circuit and see what problems do arise and how 
 they may be solved. 
 
 Let us first consider the cascaded R-C coupled amplifier shown 
 in Figure 12. It should be obvious that this circuit presents no 
 problems to our method of solution. The reason is that the capacitors 
 between stages are used to block the dc path between stages, hence each 
 stage is independent of any other stage and each stage can therefore be 
 adjusted without disturbing the existing state of an adjacent stage. 
 
 Figure 12. Cascaded R-C coupled amplifier. 
 
35 
 Now let us extend the problem and examine a direct coupled 
 circuit, again vithout feedback. This particular circuit is shown in 
 Figure 13 . This time there is no coupling capacitor to isolate the 
 transistors, hence the stages are no longer independent, but as we shall 
 see, this does not necessarily mean that we cannot solve each transistor 
 circuit independently. The first step is to apply Thevenin's theorem to 
 the base circuit of T , insert the model into the circuit and solve for 
 the base current of T . The modified circuit is shown in Figure Ik. 
 
 Figure 13 . Direct coupled amplifier 
 
 | VW- 
 
 E R 2 
 Rl *R 2 -J- to 
 
 R3 < R5 
 
 V B E1 B 1 ! B1 > VBE2 *&B2 
 
 ! e4<R 4 ! B2 
 
 o 
 
 Figure Ik. Modified direct coupled amplifier, 
 
36 
 
 We can easily -write: 
 
 E( R, + rJ " V BEI " W. 
 
 I 
 
 Bl HjR 
 
 E l + R 2 
 
 and since I__ = (l + f}_ )l_, we can rewrite as 
 El ^1' Bl 
 
 5-T-t; ^i ■ E( v% 5 - v bei - (1 + hKhi 
 
 E " V BE1 < x + h 
 
 I 
 
 Bl " R 
 
 V 1 + p i )(1 + $ + R i 
 
 and if I = P,I,, n we finally have for the collector current of T : 
 Ci. 1 Bl 1 
 
 p i [E - v bei ^ + rj 
 
 I 
 
 R : 
 
 2 
 
 CI R. 
 
 R^l + P 1 )(l + ^) + R 1 
 
 This is, of course, the same set of equations which were used 
 
 for the single transistor circuit of Chapter 3. The point is that T is 
 
 independent of T if and only if I_, n is independent of V D1 , even though 
 d. CI CD.L' 
 
 T is quite dependent on T . Therefore a stable solution can be found 
 first for T and then since T is not affected by T r , a stable solution 
 can be found for T . This is true for any topology of this general 
 nature as long as the solution is begun on the independent stage and the 
 
37 
 process works through successive dependent stages. Therefore, this type 
 of circuit is also no greet problem if this character istic is taken into 
 consideration. 
 
 Now examine the circuit of Figure 15. This circuit contains 
 feedback from the collector of T to the base of T through resistor R . 
 The method of starting from an independent stage and working through 
 successive dependent stages is not applicable since there is no independent 
 stage. This circuit is difficult to solve even without introducing non- 
 linearities unless matrix methods are used to solve the circuit with 
 loop or node equations. 
 
 E -l = 
 
 12. Uv 
 
 R E1 = ^ 
 
 E 2 = 
 
 13.3v 
 
 R E2 " 1T9 
 
 R l = 
 
 33K 
 
 ^3 = °' 68 
 
 R 2 = 
 
 10K 
 
 h = P 2 " 5 ° 
 
 R 3 = 
 
 1.2K 
 
 P 3 = 100 
 
 ^ " 
 
 ^7 
 
 V = V 
 BE1 BE2 
 
 R 5 = 
 
 1.5 
 
 V EE 3 = * 3V 
 
 ?-2 
 
 
 
 t 
 
 
 
 = .6V 
 
 Figure 15. Feedback amplifier 
 
38 
 
 To attempt to continue the use of the method previously used for 
 solving non-linear circuits, let us first write the equations for the 
 three collector currents of this circuit. This can be done after inserting 
 the transistor models by starting from T. and going toward T while 
 being very careful in developing Thevenin equivalent circuits along the 
 way. The three equations which can be derived are: 
 
 rI C3 R 5 
 
 X C1 " h 
 
 (r 2 + r 5 ) + (: 
 
 v (i + -2_ — 1 -i 
 
 BEV + R 
 
 R + R 
 l 5 ) + (l+P l )R El (l + "V- 1J 
 
 (U.l) 
 
 J C2 = P 2 
 
 E - V R - V 
 
 l ci 3 
 
 R + (1 + P )I^ 
 
 I 
 
 (h.2) 
 
 ^3 = P 3 
 
 I C2 R )4 
 
 V. 
 
 BE 
 
 R, + (1 + (3 ~)R 
 
 3' E3 
 
 (^.3) 
 
 If a value is assumed for I. , preferably close to its expected 
 
 ^3 
 
 value, it is possible to solve for I and then I and I r o« The new 
 value of I can be put back for I and the procedure repeated until the 
 solution settles down. This is successive approximation which is exactly 
 the same method used for handling the non-linearities. Therefore, it is 
 also prone to the same limitations and problems as were discussed in 
 Chapter 3. Now we have further compounded the problem because to use 
 successive approximation for both the non-linearities and the actual 
 solution will require four different sets of iterations. The remainder of 
 
39 
 this chapter will be devoted to three very similar ways of using 
 successive approximation to solve this type of problem. 
 
 As was pointed out in Chapter 3, we will not bother to derive 
 the equations for the transistor models and will instead just accept 
 them. Note, however, that there is a slight difference in the form of 
 the equations for beta. This difference has no effect other than to 
 increase the calculation time for beta. For this problem, T.. and T were 
 assumed to be identical transistors with the following parameter values: 
 
 P s = exp[U.528U + .17376 Log(l_.) + 3.9687 x 10~ 3 Log 2 (l_. ) ] 
 
 i = 1,2 (h.h) 
 
 V BEi = - 3895 + i- 6 ^ 1 * 10" 2 Log(l c .) - 7.1715 x 10" U Log 2 (l c .)] 
 
 i = 1,2 (k.5) 
 
 ?or the third transistor we have: 
 1 3 = exp[l.ll55 - .^2867 Log (I ) - 8.M*93 x 10" 2 Log 2 (l C3 ) ] (U.6) 
 
 'BE3 = - 2 " 37 + T ' 8399 x 10_3L og( I C3 ) " 9.3957 x lo" U Log 2 (l C3 )] (U.7) 
 
 The first method we will consider will be the use of four sets of 
 successive approximation iterations. While using this method we must 
 first keep in nind that for successive approximation we usually need a 
 reasonable starting point. This is of particular importance to us 
 because of the type of model we are using. A glance of Equation U.l 
 shows that if I is initially chosen too small, I will be negative, 
 therefore, when we calculate a new value of p, and V we will be 
 taking the natural log of a negative number as indicated in 
 
4o 
 
 Equations 4.4 and 4.5. Generally speaking, however, since circuit 
 analysis is to be performed on a previously designed circuit, the 
 designer should have some idea of the range of values of all the 
 relevant quantities. 
 
 The first step of the method is to select a suitable initial 
 value for I . Given I , and a nominal (3. and V__- , I_ n can be 
 
 LO ^0 1 aHiL CL 
 
 calculated and therefore a corrected 6., and V „„ can be found. This 
 
 K l BE1 
 
 process is to continue around T- until I„ settles down between two 
 
 1 CI 
 
 successive iterations. Using this value for I . , I can be calculated 
 
 U J- Lȣ- 
 
 and using I _ new values for P and V _ can be calculated. The process 
 02 2 BE2 
 
 for transistor 1 is then duplicated for transistor 2 until I ro settles 
 
 down between successive iterations. The identical procedure is then 
 
 used for transistor 3 until a stable value for I is obtained. This 
 
 to 
 
 value for I is then compared with the initial value selected for I . 
 
 If there has been a significant change in I,-,.-,, then the entire process is 
 
 repeated using the new value of I as the initial value of Ip,. On the 
 
 Co Co 
 
 other hand, if the two values of I are very close, the process is 
 completed and a stable solution for all three transistors and the circuit 
 has been found. The method is illustrated in a flowchart in Figure l6. 
 The results of using this process on the circuit of Figure 15 with the 
 parameters given in Equations h.k, 4.5, U.6 and 4.7 are shown in 
 Table 4-2. 
 
 The redundancy which seems to be present by having three 
 iterative loops contained -within a fourth loop suggests that there might 
 be an easier way to do the process with a smaller number of iterative 
 loops. The simplest process of all would be to do all of the work with 
 Just one iterative loop. Logically, this could only be the outermost 
 
kl 
 
 START 
 
 i 
 
 SELECT AN 
 INITIAL I 
 
 C3 
 
 t>* 
 
 CALCULATE AN 
 INITIAL I 
 
 CALCULATE NEW 0. , 
 
 bV* v BE] 
 
 NEW I c , 
 
 
 CALCULATE THE 
 CHANGE IN I 
 
 © 
 
 
 
 CALCULATE AN 
 LNIT1AL I C2 
 
 ©- 
 
 CALCULATE NEW , 
 V^g AND THEN 2 
 
 A NEW I 
 
 C2 
 
 CALCULATE THE 
 CHANGE IN I 
 
 © 
 
 
 
 CALCULATE AN 
 INITIAL I C3 
 
 0- 
 
 CALCULATE NEW 
 V__,_ AND THEN i 
 
 DC 5 
 
 A NEW I 
 
 Cl 
 
 CALCULATE THE 
 CHANGE IN I 
 
 CALCULATE THE 
 CHANGE FROM THE 
 SELECTED I TO THE 
 PRESENT Ij 3 
 
 Figure 16. Flowchart of method #1 
 
42 
 
 loop; the one which checks on the collector current in transistor 3 in 
 
 terms of the circuit. This would mean that every time it is required to 
 
 calculate a new collector current in the chain of Equations 4.1, 4.2 
 
 and 4.3, we would have to first calculate values for all the model 
 
 parameters in terms of the value of the currents presently available. 
 
 In other words select a value of I„ as before and then calculate I . 
 
 f irst using some rough value of I_. to calculate f3 and V . Then I 
 
 can be found in a similar fashion, then I and so on. Although the 
 
 C3 
 
 rough values originally chosen for I„, and I will probably result in 
 
 Ui. o<_ 
 
 odd values of the transistor parameters at first, the whole thing should 
 begin to converge after a few iterations. The flowchart for this method 
 is shown in Figure 17 and the results of actually trying it are shown in 
 Table 4-1. A quick glance at Table 4-1 shows that instead of converging, 
 the routine results in oscillatory divergence. One possible reason might 
 be that any initial error which occurs is "amplified" greatly before any 
 corrective action can be taken which might allow the method to continually 
 over -compensate for the initial error. 
 
 Before we attempt to find a third method, the one major short- 
 coming of method #2 should be considered. The problem is simply that 
 there is no inherent stability anywhere in the method. In method #1, 
 stability was demanded at every step along the way. In method #2, 
 stability was the end in itself. Just to see what effect the- initial 
 values of the parameters were, method #2 was repeated using the final 
 values of method #1 which are the values the method should converge to 
 when done. The results are the ones shown in Table 4-1. The results of 
 using arbitrary initial values were worse; the method diverged even 
 faster! 
 
 
»*3 
 
 C 
 
 START 
 
 ") 
 
 SELECT AN 
 INITIAL l e|l 
 
 IC2 AND I c3 
 
 CALCULATE VALUES 
 FOR $\, $z, flat 
 V B El. v BC2 ,and 
 V 8 ES 
 
 calculate a 
 
 NEW I CI , I C 2 
 AND I c3 
 
 CALCULATE THE 
 CHANGE IN la 
 
 Figure 17. Flowchart of method #2 
 
As a quick review, method #1 required each stage to stabilize and 
 then for the entire circuit to stabilize. On the other hand, method #2 
 required that the circuit stabilize but no stability restriction was 
 placed on the transistor parameters; the values of the parameters were 
 different during each iteration. Perhaps a compromise method could be 
 worked out which would also achieve stability but with less complexity 
 than method #1. 
 
 Towards this end, consider the following: assume initial values 
 
 for all three collector currents, preferably reasonable ones; calculate 
 
 the values of the 3's and the V_. 's using the present values of the 
 
 an, 
 
 collector currents; while holding all the parameters constant at the 
 values just calculated, iterate through Equations U.l, k.2. and U.3 until 
 a stable value of I , is found; if this value is not different from the 
 starting value for I , then the process is complete, otherwise, using 
 the present stable values of the collector currents, calculate new 
 parameters and try again. The flowchart of this method is given in 
 Figure 18 and the results are listed in Table k-2 alongside the results 
 of method #1. These results were obtained by starting with perfectly 
 ridiculous values for the collector currents. 
 
 It should be mentioned that methods #1 and #3 are not immune 
 to divergence, but from other tests these methods appear to be as stable 
 as the circuit which they attempt to solve. Actually, there is a definite 
 
 significance to the differences between methods #1 and #3 a nd this is 
 explained in Chapter 7. 
 
^5 
 
 ( 9IAKT } 
 
 OBTAIN A NOMINAL 
 
 sour 
 
 YES 
 
 CALCULATE HEW 
 VALUES ror p., P , 
 
 e,, v , r.i.,« 
 
 V 
 
 bej 
 
 BEV BE?' 
 
 CALCULATE NSW 
 VALUES TOR I 
 
 J ca M,D ^3 
 
 Cl' 
 
 CALCULATE THE 
 CHANCE IN I_. 
 
 A 
 
 CALCULATE THE 
 CHARGE TOON THE 
 HOVTOUS aOLUTIOM/ 
 TO THI3 glLUTIOy 
 
 * Obtaining a nominal solution using standard values for the transistor 
 parameters is a good way of getting reasonable starting values. It 
 could have been used for all three methods unless reasonable starting 
 values vere already known. However, since methods #1 and #3 a re 
 independent of their starting values this step is academic. 
 
 Figure 18. Flowchart of method #3 
 
46 
 
 \ ( ma ) 
 
 I (ma) 
 
 3.91 
 
 36. 14 
 
 
 .95 
 
 ZM 
 
 38.85 
 
 
 I.05 
 
 3.86 
 
 36.39 
 
 
 .95 
 
 3.4l 
 
 39.01 
 
 
 1.06 
 
 3.89 
 
 36.23 
 
 
 .94 
 
 3.38 
 
 39.18 
 
 
 1.07 
 
 3.92 
 
 36.05 
 
 
 .94 
 
 3.35 
 
 39.37 
 
 
 1.07 
 
 3.96 
 
 35. 84 
 
 
 .93 
 
 3.31 
 
 39.58 
 
 
 1.08 
 
 4.00 
 
 35.61 
 
 
 .92 
 
 3.27 
 
 39.82 
 
 
 I.09 
 
 4.o4 
 
 35.36 
 
 
 .91 
 
 3.22 
 
 40.09 
 
 
 1.10 
 
 4.09 
 
 35.07 
 
 
 .90 
 
 3.17 
 
 40.39 
 
 
 1.12 
 
 4.15 
 
 34.74 
 
 
 .88 
 
 3.H 
 
 40.73 
 
 
 1.13 
 
 4.21 
 
 34.38 
 
 
 .87 
 
 3.05 
 
 4l.ll 
 
 
 1.15 
 
 4.28 
 
 33.97 
 
 
 .85 
 
 2.97 
 
 41.53 
 
 
 1.17 
 
 4.36 
 
 33.51 
 
 
 .84 
 
 2.89 
 
 42.00 
 
 
 1.19 
 
 4.45 
 
 33.00 
 
 
 .82 
 
 2.80 
 
 42.52 
 
 
 1.21 
 
 4.54 
 
 32.44 
 
 
 .80 
 
 2.70 
 
 43.10 
 
 
 1.24 
 
 4.65 
 
 31.81 
 
 
 .77 
 
 Table 4-1 
 
 Results of method 
 
 #2 
 
 
 Method #1 
 
 Final Value 
 
 
 Method #3 
 
 39.575 
 54.673 
 
 61.084 
 .27576 
 .32854 
 .29942 
 3.646 
 37.681 
 1.007 
 109 
 
 b. 
 
 P 2 
 P 3 
 
 Jm 
 
 JJ3E2 
 
 *C2 ma) v 
 I (amps; 
 
 # of Iterations 
 
 39.565 
 54.674 
 61.091 
 
 .27571 
 .32854 
 .29942 
 3.648 
 37.671 
 1.007 
 89 
 
 Table 4-2 Comparison of methods #1 and #3 
 
hi 
 5. THE EFFECT OF ADDING TEMPERATURE 
 
 In Chapters 3 and h methods of solving non-linear equations were 
 
 explored. These non-linear equations were the result of the inclusion of 
 
 non-linear functions for £ and V in the transistor model. Until now, 
 
 BE 
 
 the effects of temperature were ignored lest including temperature in the 
 
 model have any disastrous effects on the circuit solving method. 
 
 Actually, temperature is not the problem it might originally seem 
 
 because as far as the circuit is concerned the temperature is an external 
 
 variable; that is, the temperature is not a function of any other variables 
 
 in the circuit as were (3 and V . This is not entirely true; if any cur- 
 
 oE 
 
 rent at all is flowing through the transistor there will be some power 
 dissipation at the semiconductor junctions which will be dissipated as 
 heat. The relation of junction temperature to power dissipation in the 
 junctions is of course a function of the current and voltage waveforms at 
 the junction as well as of time. The theory will be developed, however, 
 as if it is possible to consider only an ambient temperature and that the 
 circuit designer will have to allow for junction temperatures. 
 
 Before attempting to select a model containing some temperature 
 dependence, let us glance at the graphs of Figure 19 which show V and 
 £ as functions of both collector current and temperature. From the re- 
 lations of these curves to one another it should be clear that the rela- 
 tion between either (3 or V..^ and temperature is at least linear and using 
 
 ait 
 
 a quadratic function as an approximation should help account for any dis- 
 crepancies. These curves are for the Texas Instruments 2N910 family of 
 NFN double diffused planar silicon transistors and were taken from the 
 1966 perpetual data book produced by T.I. (These curves are typical of 
 
he 
 
 1.0 
 
 01 
 0.1 
 
 r 0.7 
 
 I 
 
 I as 
 
 I 0.9 
 
 I 
 u 
 
 i° 4 
 
 T 0.3 
 
 * az 
 
 BASE-EMITTER VOLTAM 
 
 Vt 
 FREE-AIR TIMPERTURE 
 
 
 
 
 
 
 
 vce« 
 
 U)i 
 
 
 "4 1 
 
 ■^^c 
 
 »50»« 
 
 
 see notc « 
 
 
 "v^ 
 
 
 
 •c« 
 
 10m 
 
 
 
 
 'c" 
 
 lmo 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 ^N 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 L 
 
 
 
 
 
 
 
 -75 -50 -25 25 50 79 100 125 150 
 
 T A — Fr«« -Air T«mp«ratur« — # C 
 
 NORMALIZED STATIC FORWARD CURRENT 
 TRANSFER RATIO 
 Vt 
 COLLECTOR CURRENT 
 
 2.0 
 
 1.6 
 1.6 
 1.4 
 1.2 
 
 1.0 
 0.8 
 0.6 
 0.4 
 0.2 
 
 
 
 
 J 
 
 
 
 
 
 
 
 
 
 
 NONMALIZ 
 AT l c « 10i 
 
 ED TO 1.0 
 no, T A «28» C 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 Ta- 
 
 ' 1 
 
 25 
 
 *c 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 v ce' 10 * 
 
 Sec NOTf 
 
 • 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 ta 1 
 
 ei 
 
 l«< 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 t A ' 
 
 1 — 
 
 so 
 
 •c 
 
 
 \ 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 II 
 
 
 
 1 
 
 1 10 100 
 
 l c ~ Coll»ct»r Curr.nl — M« 
 
 1000 
 
 
 Figure 19. Transistor characteristics 
 
 
h9 
 most silicon transistors.) Although not all transistors have these graphs 
 (some merely have a list of approximate parameter values), it should be 
 clear that such graphs can be easily constructed from data measured in the 
 laboratory. 
 
 Returning to the task of building our model, it is clear that the 
 free air temperature in degrees centigrade is a poor choice of units. Any 
 model which contains a linear temperature term must contend with the sign 
 change at -sero degrees centigrade, and any polynomial model would have to 
 have a point of inflection at zero. Therefore to avoid these problems we 
 shall use the absolute temperature scale in degrees Kelvin which is merely 
 a linear transformation from degrees centigrade, accomplished by adding 
 273 to the centigrade temperature. The full model then, for (3 or Vl,^, 
 either one being referred to as QUANTITY below, would be: 
 
 QUANTITY = a. 1 + a 2 Log(l c ) + a 3 Log 2 (l c ) + a^T + a^ 2 
 
 Tnis equation is essentially the same as our previous models. 
 
 The difference can be easily absorbed by specifying a constant temperature 
 
 which allows the a, T and a T terms to be absorbed into a, and reduces the 
 
 45 1 
 
 model to the same model used in Chapters 3 and k. The easiest way to fit 
 this equation is with a multiple linear regression program which is what 
 was done using data points selected from these graphs. 
 
 Returning to the problem of physically solving this network, 
 either method #1 or method #3 of Chapter k can be used within a loop which 
 adjusts the temperature after a stable solution is found. The reason for 
 the simplicity of adding the temperature is that the temperature is an ex- 
 ternal variable and hence does not affect the internal loop. Using this 
 
50 
 
 method on the common emitter amplifier of Figure 20 with the following 
 
 parameters for p and V_ • 
 
 Bill 
 
 for p : a ± = -57. 6765, a ? = -7.273, 83 = -.91 
 
 a, = .301, a = .10711 x 10' 
 
 k 
 
 . a x = 1.39799, a g = -.IU5U, a 3 = -.0182 
 
 i k = -.00121, a = .II8U9 x 10' 
 
 and working through a temperature range of -55" C to 125" C in ten 
 degree increments the results of Table 5 - l were obtained. 
 
 
51 
 
 Temperature (°C) 
 
 I c (na) 
 
 P 
 
 V fiE ( volts) 
 
 V CE ( volts) 
 
 -55 
 
 8.57 
 
 22.45 
 
 1.35 
 
 12.75 
 
 -45 
 
 9.02 
 
 25.57 
 
 1.34 
 
 12.48 
 
 -35 
 
 9.41 
 
 28.69 
 
 1.32 
 
 12.25 
 
 -25 
 
 9.76 
 
 31.79 
 
 1.30 
 
 12.05 
 
 -15 
 
 10.07 
 
 34.89 
 
 1.29 
 
 11.87 
 
 - 5 
 
 10.36 
 
 37.99 
 
 1.27 
 
 11.70 
 
 5 
 
 10.62 
 
 41.08 
 
 1.25 
 
 11.55 
 
 15 
 
 10.86 
 
 44.17 
 
 1.23 
 
 11.41 
 
 25 
 
 11.08 
 
 47.27 
 
 1.21 
 
 11.28 
 
 35 
 
 11.29 
 
 50.36 
 
 1.19 
 
 11.16 
 
 45 
 
 11. 48 
 
 53.45 
 
 1.18 
 
 11.04 
 
 55 
 
 11.67 
 
 56.54 
 
 1.16 
 
 10.93 
 
 65 
 
 11.85 
 
 59.64 
 
 1.14 
 
 10.83 
 
 75 
 
 12.02 
 
 62.73 
 
 1.12 
 
 10.73 
 
 85 
 
 12.18 
 
 65.83 
 
 1.10 
 
 IO.63 
 
 95 
 
 12.3^ 
 
 68.92 
 
 1.0? 
 
 10.54 
 
 105 
 
 12.49 
 
 72.02 
 
 1.05 
 
 10.45 
 
 115 
 
 12.64 
 
 75.12 
 
 1.03 
 
 IO.36 
 
 125 
 
 12.78 
 
 78.23 
 
 1.01 
 
 10.28 
 
 Table 5-1 
 
 Performance of 
 
 common 
 
 emitter amplifier 
 
 
 47K 
 
 I C j< 330 
 
 TRANSISTOR- 2N910 
 INTERNAL £~50 
 INTERNAL V BE ~1.2V 
 
 Figure 20. Common emitter amplifier 
 
.52 
 
 6. A GENERAL LINEAR CIRCUIT ANALYSIS PROGRAM 
 
 Chapters 3, k, and 5 illustrated the solution of non-linear cir- 
 cuits by using iterative linear analysis. In each case it was necessary to 
 write a specific set of programs to solve each particular network. It is 
 clearly impossible to write enough specific programs in advance to handle 
 each circuit which may be designed. Alter natively, one could always write 
 a new routine to solve each new circuit but the amount of programming and 
 debugging time involved makes this practice prohibitive. For this reason 
 we shall now examine the capabilities and use of an existing linear circuit 
 analysis program and attempt to modify it for our own use. 
 
 The I.B.M. Electronic Circuit Analysis Program (ECAP) is an inte- 
 grated system of programs designed to aid the electrical engineer in the 
 design and analysis of electronic circuits. This system of programs can 
 produce dc, ac and/or transient analysis of electrical networks from a de- 
 scription of the connections of the network (the circuit topology), a list 
 of corresponding element values, a selection of the type of analysis wanted, 
 a description of the circuit excitation, and a list of the outputs desired. 
 
 ECAP recognizes a set of standard electrical circuit elements. Any 
 electrical network that can be constructed from any or all of the different 
 elements in the set can be analyzed by ECAP. There is almost no limit to 
 the number of ways that the circuit elements can be arranged in the network, 
 although the topology is limited to 200 nodes and 600 branches for the 
 I.B.M. 709U and System 3o0. 
 
 The set of standard circuit elements does not include active el- 
 ements, but in many cases these components are easily simulated by means of 
 linear equivalent circuits constructed of standard elements. Non-linear 
 
 
53 
 models cannot be represented by these standard elements, and piecewise 
 linear models only over a restricted range. 
 
 ECAP is very simple to use. The user needs no knowledge of the 
 internal construction of the program and no previous computer experience is 
 required. It is only necessary that the user become acquainted with the 
 methods of communication with ECAP. These include: (a) the technique of 
 describing a circuit to the program, (b) the specification of the type of 
 analysis required, and (c) the interpretation of the res\ilts. The problem 
 of communicating with ECAP is particularly simple for the engineer because 
 the input for ECAP, as well as its output, is expressed in the language of 
 the electrical engineer. 
 
 Once the input for ECAP is prepared, the statements are punched 
 3 cards for entry as input to the ECAP program. ECAP interprets the in- 
 put statements, determines the network topology, generates the network 
 (nodal) equations, performs the desired analysis and produces the specified 
 output in tabular form. 
 
 ECAP actually consists of four related programs: 
 
 1. input language processor 
 
 2. dc analysis program 
 
 3. ac analysis program 
 
 h. transient analysis program. 
 Only the input language and the information relevant to the dc analysis 
 program will be discussed. 
 
 The input language processor is the primary communications link 
 between the user and the analysis programs. It provides the user with a 
 means of describing in familiar terms the complex arrangements of components 
 directly from the circuit. It provides, as well, a means of controlling 
 
5V 
 the type and the extent of the analysis to be performed, and the form and 
 the amount of the output that is desired. 
 
 The outstanding features of the input language are the English 
 language style and the simplicity of the input format. Only six types of 
 statements are needed to describe a given circuit completely. The input 
 statements define the topology of the circuit, the element values, the type 
 of analysis desired, the circuit excitation and a list of the desired 
 output . 
 
 The dc analysis program provides the steady-state solution (volt- 
 ages, currents and power losses) of linear networks, the partial derivatives 
 and sensitivity coefficients of the node voltages with respect to the in- 
 put parameters such as resistance, voltage sources and BETA'S, and both a 
 worst case and a standard deviation analysis of the node voltages. The 
 latter analyses require the entry of parameter tolerances as input data. 
 An automatic parameter modification capability is also available to the 
 program. 
 
 To use this program for dc analysis in ECAP (l620 version) we 
 always need the following two statements which begin in columns one and 
 seven respectively: 
 
 *CONTROL , PRINT ( , TRACE ) ( , PDUMP ) 
 DC ANALYSIS 
 
 The information in the parentheses is useful mainly in the modification of 
 ECAP itself and is optional. These two statements must always appear in 
 the order shown and always before any other types of statements except the 
 
 comment statements which are explained below. It should be noted that 
 
 this only holds for the 1620 version of ECAP. 
 
55 
 The comment statement may be placed anywhere in the input and is 
 identified by the letter "C" in column one of the card followed by anything 
 at all . For example : 
 
 C COMMON EMITTER TEST PROBLEM 
 
 Numeric data may be represented in a number of ways in ECAP as is 
 shown below where "X" is any digit, "E" indicates "10 raised to the power 
 
 and "Y" indicates the exponent that 10 is raised to. Two examples of 
 each type are also given. 
 
 +XX 
 
 12000 
 
 1 
 
 +XX. 
 
 470. 
 
 -3. 
 
 +XX.X 
 
 - 12.5 
 
 +1.1 
 
 + .XX 
 
 + .001 
 
 - .3 
 
 + X.XXE+YY 
 
 +263.1E+3 
 
 + .1+7E-06 
 
 +XXE+YY 
 
 +12E3 
 
 +1E-12 
 
 Note also that blanks are ignored, exponents are limited to +99 °r -99 and 
 that the maximum mantissa length is eight digits. These limits still pro- 
 vide for a great # deal of flexibility in the range and form of data which 
 can be entered into the program. 
 
 For dc purposes, ECAP considers a standard circuit branch which 
 appears as shown in Figure 21. This branch exists between an initial node 
 
 m with node voltage e and a final node n with node voltage e . It must 
 
 m n 
 
 always contain some value for R and may contain a value for the fixed volt- 
 age source E, the fixed current source I and/or the controlled or dependent 
 current source i'. The current J' is defined as the element current; i is 
 
56 
 defined as the branch current. Using these symbols the following defini- 
 tions and relations can be obtained: 
 
 Node voltages 
 Element current 
 Element voltage 
 Branch current 
 Branch voltage 
 Element power loss 
 
 e 5 e 
 
 m n 
 
 e +E-e 
 m n 
 
 e -e 
 m n 
 
 (e +E-e )*J' 
 m n 
 
 The values for R,E, I and i' are inputs and the six quantities 
 above are outputs of the program. 
 
 o e, 
 
 Figure 21. Standard dc circuit branch 
 
 In order to define completely the topology of a dc circuit only 
 two types of input statements are required: the statements specifying the 
 branch data and the statements specifying the dependent current source data 
 These statements are easily written from an existing circuit schematic as 
 will be demonstrated later, but first we consider the format of these 
 statements. 
 
57 
 The general form, of the branch data statement is : 
 
 Bnn 
 
 (N. , N_), R=spec(,E=spec)( ,I=spec) 
 
 where the "Bnn" must lie between columns 1-5 and the rest of the informa- 
 tion must lie between columns 7-72. The information in parentheses is op- 
 tional for any particular branch. The "B" is the identification for the 
 
 branch data statement, "nn" is the number of the branch, "N. " and "N " are 
 
 ' i f 
 
 the numbers of the initial and final nodes of the branch and "spec" may be 
 a single value such as 12000 or for purposes of worst case analysis may be 
 of Vne form: 
 
 value (minimum value, maximum value) or value (percentage). 
 
 For example, a 10K resistor with a 5% tolerance could be represented as: 
 
 R=10000(9500, 10500) or R= 10000 (.05) 
 
 The branch data statements for the simple voltage divider of 
 Figure 22 are : 
 
 Bl N(0,l), R=2000, E=12 
 B2 N(1,0), R=i+000 
 
 Note that the ground or datum node is considered as node "0" and note the 
 signs and directions of the branch currents. 
 
B, 
 
 58 
 
 I2v 
 
 "WAr 
 2K 
 
 4K 
 
 |B 2 
 
 
 
 -ir 
 
 Figure 22. Simple voltage divider 
 
 The general form of the dependent current source statement is : 
 
 Tnn B(b ,b ), BETA=spec (or GM=spec) 
 
 where the "Tnn" must lie between columns 1-5 and the rest of the informa- 
 tion must lie between columns 7-72. The information in parentheses may be 
 used if the current source is to be dependent on a voltage instead of a 
 current. The "T" is the identification for the dependent current source 
 statement, "nn" is the number of the current source and is used for iden- 
 tification only, "b " is the controlling branch, "b " is the controlled 
 branch, "BETA" or "GM" is the current gain and "spec" is as before. For 
 example, if part of a transistor model looked like Figure 23 the appropri- 
 ate B and T statements would be: 
 
 B3 NO, 1 *), R=1000, E=-0.6 
 Bh NO, 1 *), R=10000 
 
 Tl BO, 1 *), BETA=50 
 
 Note the sign of the voltage source; it is negative because it is opposing 
 the current flow from the initial to the final node of branch three. Also 
 note that in the T statement, branch 3 controls branch k. 
 
59 
 
 0*50 
 
 Figure 23. Transistor model 
 
 In addition to the dc steady state solutions, the dc analysis can 
 also give a worst case analysis, a listing of sensitivities and partial 
 derivatives of node voltages with respect to branch elements and the stan- 
 dard deviations of the node voltages. These statements begin in column 
 seven and are written: 
 
 WORST CASE 
 SENSITIVITY 
 STANDARD DEVIATION 
 
 The types of output specifically desired must be indicated in the 
 PRINT statement which also begins in column seven: 
 
 PRINT , OUTPUT ,(,0UTFUT 2 ) ( , OUTPUT ) . . . 
 
 where OUTPUT ,0UTPUT 2 , OUTPUT . . . are defined as follows 
 
60 
 
 OUTPUT DESCRIPTION OF OUTPUT 
 
 Node voltages 
 Element currents 
 Element voltages 
 Branch currents 
 Branch voltages 
 Element power losses 
 Sensitivities and partial 
 
 derivatives 
 Worst case 
 
 Standard deviation 
 Nodal admittance matrix, 
 equivalent current vector, 
 nodal impedance matrix 
 
 In order to execute a given program the following statement begin- 
 ning in column seven is used: 
 
 EXECUTE 
 
 It is also possible to modify the parameters of a circuit after 
 its first solution by using the following statement which begins in column 
 seven : 
 
 "NV" or "VOLTAGES" 
 
 "CA" or "CURRENTS" 
 
 "CV" 
 
 "BA" 
 
 "BV" 
 
 "BP" 
 
 "SE" or "SENSITIVITIES" 
 
 "WO" or "WORST CASE" 
 "ST" or "STANDARD 
 
 DEVIATION 
 "MI" or "MISCELLANEOUS 
 
 MODIFY 
 
 followed by B and T statements containing only enough information to modify 
 the existing circuit. For example, to change the value of the voltage 
 
 
61 
 source in the transistor model of Figure 23 to 0.8 volts we would need: 
 
 B3 E=-0.8 
 EXECUTE 
 
 During the modification process it is also possible to use a "spec" of the 
 form: 
 
 a x (a 2 )a 3 
 
 which causes the element to take on the range of values from a to a with 
 a_+l being the total number of values in the range. For example, to force 
 a resistor to take on the values 1K,2K,3K, . . ,10K we would use the follow- 
 ing: 
 
 R=1000( 9)10000 
 
 which would cause the circuit to be solved 10 times while the resistor was 
 stepped from IK to 10K. 
 
 Finally, to indicate the end of a problem the following statement, 
 beginning in column seven is used: 
 
 END 
 
 This has not been an exhaustive discussion of ECAP's uses or cap- 
 abilities, it was given only to point out the generality, the ease of input 
 and the simplicity of a general linear circuit analysis program. There are 
 other programs as well which not only duplicate ECAP's capabilities but 
 offer even more capabilities. In the next chapter we shall deal with a 
 modification to ECAP which will allow it to be used with non-linear 
 
62 
 
 networks . For the remainder of this chapter a sample ECAP program will be 
 developed and the results will be reproduced. 
 
 Consider the common emitter amplifier of Figure 2ke. and the de- 
 sired transistor model given in Figure 2Ub. The first step in preparing 
 the input for ECAP for this circuit is to redraw the circuit, including 
 the model, by splitting common voltage sources and showing the voltage 
 sources connected to ground. The next step is to number all the nodes 
 except the ground or datum node which is automatically designated zero, 
 beginning with 1 and making sure that all the nodes form an unbroken se- 
 quential set since ECAP uses that test to determine if all the data are 
 present before it executes. Next all the branches are numbered beginning 
 with 1 and again forming an unbroken sequential set. Given this type of 
 circuit it is a simple matter to write the ECAP circuit description. The 
 circuit, modified as described above, is shown in Figure 26. In order to 
 specify a worst case analysis it is necessary to place tolerances on all 
 of the components so the actual ECAP source program in Figure 25 is shown 
 with tolerances ranging up to 10$ in the B and T statements. Finally, the 
 listing from the computer is shown in the remaining pages of the chapter. 
 
 
63 
 
 500A 
 
 Figure 2k. (a) Common emitter amplifier, (b) transistor model 
 
6U 
 
 *CONTROL, PRINT 
 
 C 
 
 C SINGLE STAGE COMMON EMITTER AMPLIFIER 
 
 C 
 
 C 
 C 
 
 c 
 
 Bl 
 
 B2 
 
 B3 
 
 Bl* 
 
 B5 
 
 B6 
 
 C 
 
 C 
 
 C 
 
 Tl 
 
 C 
 
 C 
 
 C 
 
 DC ANALYSIS 
 
 BRANCH DATA 
 
 N(0,2), R=2000 (i860, 211*0), E=20(l9,2l) 
 N(0,1), R=6000( 5580, 6*120), Efc=20(l9,2l) 
 N(0,l), R=1000( 930,1070) 
 N(l,3), R= 350(.10), E=-0.5 
 N(3,0), R= 500( 1*65, 535) 
 N(2,3), R=11.1E3(.10) 
 
 DEPENDENT CURRENT SOURCE DATA 
 
 B(lf,6), BETA-50(l+5,55) 
 
 SOLUTION CONTROL CARDS 
 
 WORST CASE 
 STANDARD DEVIATION 
 SENSITIVITIES 
 
 OUTPUT SPECIFICATIONS 
 
 PRINT,NV,CA,CV,BA,BP,SE,WO,ST,MI 
 
 EXECUTE 
 END 
 
 Figure 25. ECAP program for common emitter amplifier 
 
 20v 
 
 20v 
 
 6K ||b 
 
 100 > I B 
 
 50OHb 5 
 
 Figure 26. Common emitter amplifier to be analyzed by ECAP 
 
65 
 
 «CCNTRCL,PRIM 
 
 t 
 
 C SINGLE STAGE CUNfL'N EMITTER AMPLIFIER 
 
 C 
 
 CC ANALYSIS 
 
 BRANCH CATA 
 
 N(C,2) .K = 2:::i l96Ct 21^.C), E = 2C( 19, 211 
 N(C,l),R=6:::(5b8C,6A2C),E*2C(19,21) 
 
 nic, 1 ) ,'< = 1 ::••:( 93 CtU7C) 
 
 N(i,3) t R=35:(.LO) f E«-C.5 
 
 N(3,:) ,K*5" : (46^>,535) 
 N(2, ?) ,!i=ll.lt3l ,1C) 
 
 DEPENCENT CLIENT SCIRCE TATA 
 
 B(^,fc),HETA=5:(45,55) 
 
 SCLtTICN CCNTRGL CARCS 
 
 WCRST CASE 
 STANCARC TEVIAIILN 
 SENSITIVI7 IuS 
 
 CU7PUT RFCLESTS 
 
 PRIM,NV,CA,CV,BA,RV t eP,SE»WC,ST,Nl 
 EXECLTE 
 
 c 
 
 C 
 
 C 
 
 01 
 
 22 
 
 E3 
 
 t<. 
 
 e5 
 
 E6 
 C 
 
 C 
 C 
 
 11 
 
 C 
 
 c 
 
 c 
 
 c 
 c 
 c 
 
66 
 
 NCDAL CCNCUCTANCE MATRIX 
 PCW CCLS 
 
 1 
 
 1 - 
 
 3 
 
 .4C2381CE-C2 
 
 2 
 
 1 - 
 
 3 
 
 .1428571E CC 
 
 3 
 
 1 - 
 
 3 
 
 -.1457143E CC 
 
 .COCCC CCE C C 
 .59CC901E-C3 
 .90C9CCSE-C4 
 
 _sl2 8 5.71^2E-C2_ 
 .142S472E CC 
 
 .1478044E CC 
 
 NCCAL IMPEDANCE MATRIX 
 RCfc CCLS 
 
 1 - 3 
 1 - 3 
 1 - 3 
 
 .8236EE5E C3 
 
 -.316365 IE C4 
 
 .81C3CS6E 22 
 
 .285269SE CI 
 . 1977274 E C4 
 
 .401755SE CI 
 
 .186E52CE 
 .185114 IE 
 .263149 9E 
 
 4_4 
 
 C4 
 
 C2 
 
 NCDE VCLTAGES 
 
 NCCES 
 1- 3 
 
 eRANCH 
 
 1 
 2 
 3 
 A 
 5 
 6 
 
 VOLTAGES 
 
 27S422CE CI 
 
 .11C7270E C2 
 
 .226S526E CI 
 
 EPANCP 
 
 VCLTAGES 
 
 .11C7270E C2 
 
 .2754220E CI 
 
 •2794223E CI 
 
 .5256933E CC 
 
 .2268526E CI 
 
 .E8C4170E CI 
 
 CURRENTS 
 
 .44636 52E-C2 
 
 .286763CE-C2 
 -.2 794 2 2CE-C2 
 .7340943E-CA 
 .4537C53E-C2 
 .4463640E-C2 
 
 VCLTAGES 
 
 .852 73C3E CT 
 .172C576E C2 
 -. 27542 2CE CI 
 .256S23:E-C1 
 .22685261 CI 
 .88CA17CE CI 
 
 PARTIAL CERIVATIVFS 
 
 NCDE VCLTAGE U I T h RESPECT TC RES. IN BRANCH 
 
 NCCE NC. PARTIALS SENSITIVITIES 
 
 1 -.63667276E-I5 
 
 2 -.A4l292 c .Sr-C2 
 
 3 -.ES66^516C-:5 
 
 -. 12733455E-C3 
 
 -.E82*8558E-C1 
 -.17';229e3E-C3 
 
 PARTIAL CERlVATlVtS 
 
 NCDE VCLTAGE V. I T P RESPECT TC RES. IN BRANCH 
 
NODE NC. 
 
 PART IALS 
 
 1 -.293767896-03 
 
 2 .1512C3CCE-02 
 
 3 -.387278C1E-03 
 
 SENSITIVITIES 
 
 -.23626C73E-G1 
 
 .9C7218G2E-C1 
 -.22236681E-01 
 
 
 PARTIAL DERIVATIVES 
 
 NCCE VOLTAGE ^ I T h RESPECT TC RES. IN BRANCH 
 NCDE NO. PARTIALS SENSITIVITIES 
 
 1 .23C21253t-C2 
 
 2 -.68399?54t-02 
 
 3 .226A1825E-C2 
 
 .23:212536-01 
 
 -.68399254E-01 
 
 .22641829E-01 
 
 PARTIAL CERIVATIVtS 
 
 NCOE VOLTAGE WITH RESPECT TC RES. IN BRANCH 
 
 NCDE NO. PARTIALS SENSITIVITIES 
 
 1 ,2eA796^^E-C5 
 
 2 .27C948766-C3 
 
 3 -.6939S5C4E-C4 
 
 .99678755E-05 
 
 .948320666-03 
 
 -.242894766-03 
 
 PARTIAL CERIVATIV6S 
 
 NCDE VOLTAGE ^ I T H RESPECT TC RES. IN BRANCH 
 
 NCCE NC. PARTIALS SENSITIVITIES 
 
 1 .1695:>143li-:3 
 
 2 .1679745C6-C1 
 
 3 .23678AS6E-03 
 
 .847757186-03 
 .639872526-01 
 . 119392486-02 
 
 FARTIAL DERIVATIVES 
 
 NCCE VOLTAGE hllh RESPECT TC RcS. IN BRANCH 
 
 NCDE NC. PARTIALS SENSITIVITIES 
 
 1 -.113133666-05 
 
 2 .9C129894E-C5 
 
 3 -.159329686-:5 
 
 -. 125578376-03 
 
 . 1CCC44186-C2 
 
 -. 176656176-03 
 
 PARTIAL DERIVATIVES 
 
 NODE VOLTAGE WITH RESPECT TC GV f BRANCH 4 TC BRANCH _fc_ 
 
NODE NO. 
 
 PARTIALS 
 
 SENS ITIVITIES 
 
 .4C67891CE 00 
 
 .58112728E-03 
 
 2 -.32407557E 01 
 
 3 .57289453E 00 
 
 -.4629651CE-02 
 . 81842C74E-03 
 
 68 
 
 PARTIAL DERIVATIVES 
 
 NODE VOLTAGE WITH RESPECT TC VOLTAGE SOURCE IN BRANCH 1 
 NODE NO. PARTIALS SE NSITIVITIES 
 
 1 .14263496E-C2 
 
 2 .98863675E CO 
 
 3 .2CC87795E-02 
 
 .26526992E-C3 
 
 .19772734E 00 
 .4C175589E-03 
 
 PARTIAL DERIVATIVES 
 
 NODE VOLTAGE WITH RESPECT TC VCLTAGE SOLRCE IN BRANCH 
 NCDE NO. PARTIALS SENSITIVITIES 
 
 1 .13731474E CO 
 
 2 -.52727515E OC 
 
 3 .135C5159E CC 
 
 .27462949E-C1 
 
 -.1C545503E CO 
 
 .27C1C319E-C1 
 
 PARTIAL CERIVATIVES 
 
 NCDE VCLTAGE V«ITH RESPECT TC VCLTAGE SOLRCE IN BR ANC H 
 NCDE NO. PARTIALS SENSITIVITIES 
 
 1 -.3879562CE-C1 
 
 2 -.3 690925 8 E C 1 
 
 3 .94536224E 00 
 
 -.19397EC9E-C3 
 
 -.1645462eE-Cl 
 
 .^72681 11E-C2 
 
 WCRST CASE NCCE VCLTAGES 
 
 NCCE NO. NCMINAL CASE WCRST CASE MAX fcCRST CASE PIN 
 
 1 .279A2197E 01 
 
 2 .11072696E 02 
 
 3 .22685264E CI 
 
 .228C5e7CE CI 
 .151 51E4CE 02 
 
 .27 5872 3 6E CI 
 
 .2 31C2CC1E CI 
 .6 974 846 7E CI 
 .17816257E CI 
 
 STANDARD CEVIAT1CN OF NCDE VCLTAGES 
 NCCE NC. STL.CCV. 
 
 .8966177CE-C1 
 
69 
 
 2 .5 5 5 5665:- CC 
 
 3 .e83ci22ef-;i 
 
70 
 7. A GENERAL N0N- LINEAR CIRCUIT ANALYSIS PROGRAM 
 
 In previous chapters it was shown that methods could be devised 
 to solve non-linear circuits using linear analysis methods, and it was 
 also shown that a generalized program could be written to solve linear 
 circuits. It is the purpose of this chapter to devise a general non-linear 
 circuit analysis program. 
 
 As noted in Chapter k t two methods exist for solving non-linear 
 circuits. Since only one method can be used the choice of method will 
 probably be determined by the capabilities of the general program. Clear- 
 ly a general circuit analysis program cannot rely on writing equations for 
 each circuit and then proceed to solve them iteratively as was done in 
 Chapters 3 and k. Therefore, an examination of how the general circuit 
 analysis program selves equations must be completed first, then the appli- 
 cability of the methods of Chapter k can be determined. 
 
 An examination of the ECAP source program indicates that after the 
 topology of the circuit is read as input, the nodal equations for the net- 
 work are constructed in matrix form, after which the matrix elements due to 
 dependent generators are added. The node voltages are calculated by solv- 
 ing the matrix equations. Once the node voltages are calculated it is a 
 simple matter to determine the branch voltages and currents, and then the 
 element voltages, currents and power losses. Other quantities such as 
 sensitivities are calculated through methods irrelevant to this discussion. 
 The main point is that the program essentially solves the node equations of 
 the network after constructing the appropriate data matrices. This means 
 it once a set of parameters are entered into the system they must remain 
 i.ant all through the solution. 
 
71 
 
 At this point an examination of the two successful methods of 
 Chapter h is appropriate. The first method requires iterating around a 
 single transistor stage until the stage is stable, then continuing the pro- 
 cess for any remaining stages and then checking the overall convergence. 
 In the second method, a nominal solution allows the generation of new de- 
 pendent parameters which are then held constant until convergence of the 
 circuit is obtained. Obviously, either of the two methods can make use of 
 ECAP to provide a nominal starting point. 
 
 To use ECAP with the first method, ECAP would have to be called 
 upon each time a modification was made to the parameters in any one stage 
 and the entire circuit would be solved even though only one set of para- 
 meters was recalculated. Although the entire circuit is reevaluated, only 
 one stage is readjusted. Therefore, if each stage requires three itera- 
 tions for convergence, each total circuit iteration of three stages requires 
 nine iterations and if the circuit is required to iterate three times then 
 ECAP routine will be required to produce 27 solutions plus the initial 
 nominal solution. 
 
 The second method, which seems to require nearly as many iterations 
 as the first (at the end of Chapter k it was noted that for the same prob- 
 lem the first method took 109 iterations and the second method 89 itera- 
 -.s), does possess a property which cuts the number of iterations down 
 considerably. In the second method, the parameters for all stages are 
 evaluated simultaneously and then the circuit is iterated until it conver- 
 ges. In essence, this is the same thing as solving the circuit's nodal or 
 loop equations by successive approximation. Whereas iterating a given set 
 of parameters to a convergent solution may have taken five or six iterations, 
 the use of ECAP will solve the circuit in one step. Therefore, if the 
 
72 
 reevaluation of parameters was done three times, ECAP will be called on 
 only three times. Therefore, this method is far more efficient than the 
 first method. 
 
 To use the second method of Chapter h with ECAP a solution would 
 be developed as follows : 
 
 1) ECAP would be used to analyze the topology of the circuit and 
 produce an initial solution of the circuit using nominal linear values for 
 the non-linear paremeters; 
 
 2) after obtaining the results of the new solution, all of the 
 dependent parameters would be re-evaluated and placed into the appropriate 
 locations in ECAP's data structures and one or more of the currents would 
 be chosen to be checked as criteria for determining convergence; 
 
 3) ECAP would be called to obtain a new solution to the present 
 circuit and therefore a new set of values for the currents which were cho- 
 sen for convergence criteria in step two; 
 
 h) the relative changes in the currents would be noted and if any 
 of the changes were significant the process would be repeated from step two; 
 otherwise the process would be complete and the solutions considered as the 
 final solution. 
 
 Now the process contains only one iterative loop although the calculations 
 within the loop are considerably more complex. The revised method also 
 eliminates the problem of finding or creating an independent stage when 
 feedback loops are present. Finally, this modification in no way affects 
 the inclusion of temperature effects since the temperature is still exter- 
 nal to any of the internal processes. The only problem left then is the 
 implementation of the method. 
 
73 
 
 In order to modify ECAP as little as possible the most desirable 
 approach would be to add a completely new routine to ECAP which only re- 
 quires enough modification to ECAP to allow entry into the routine. This 
 also has the advantage of allowing ECAP to be used as it was originally 
 intended. 
 
 Matters are also simplified if the approach to the problem is to 
 allow ECAP to analyze a nominal value circuit and get the nominal solution 
 and then pass control to the iterative procedure which will use as many of 
 ECAP' 3 circuit solving facilities as is feasible to produce the iterated 
 results. It should be noted that the program structure of ECAP (l620 
 Version) consists of one main routine and about seventy subroutines which 
 can be called either from a main routine or another subroutine. 
 
 The input data to such a modified ECAP would consist of the nor- 
 mal ECAP input followed by the normal execution of the program. After 
 execution the language processor would read a control statement and pass 
 control to the new routine. This routine would then read in and analyze 
 the functional parameter dependence, the tolerance required to end the 
 iterative procedure and the quantity to apply this tolerance to as well 
 as a possible control of temperature factors. The routine would then build 
 the required evaluation routines for the dependent parameters, set up the 
 proper tests for ending the iterative procedure and, if necessary, create 
 an iterative loop for varying the temperature. 
 
 Ideally, the routine should be able to accept and evaluate a func- 
 tional relation in any form. However, to program this feature would require a 
 considerable effort to duplicate the algebraic compilation capabilities of 
 a higher level algebraic compiler such as FORTRAN. Therefore, to avoid 
 this complication the following model is assumed: 
 
7U 
 F(I C ,T) = a x + a 2 lnl c + a 3 ^ 2 I C + a^T + a T 2 (7.1) 
 
 and only the coefficients a. ,a ,a ,a, and a are read in. If no temperature 
 dependence is required, a. and a are set to zero or ignored. There is no 
 reason for this restriction other than the desire to simplify program de- 
 sign. It is also possible to program in any other type of model on a "co- 
 efficient only" basis such as this. 
 
 The first required statement for this routine is the only statement 
 of the set which can be recognized by ECAP's language processor and it 
 causes control to be passed to the iterative routine. The format of this 
 statement which appears somewhere in columns 7-72 is : 
 
 ITERATE 
 
 Since this statement gives control to the iteration routine and must be 
 used only after a nominal solution is obtained, it must follow an "EXECUTE" 
 statement (see Chapter 6) and precede any of the following statements which 
 provide information to the iteration routine. These statements however, 
 may appear in any order after the "ITERATE" statement. 
 
 The general form of the statement which indicates the functional 
 dependence of one quantity upon some current and possible temperature is: 
 
 Ann Q(j)=a 1 ,a 2 ,a , (,a^,a ) 
 
 where the "Ann" appears in columns 1-5 and the remainder of the statement 
 appears in columns 7-72. The "a ,a ,a (,a, ,a,_)" are the coefficients of 
 the model shown in Equation 7.1. Note that "a. " and "a " may be omitted 
 if no temperature dependence is required in the function. The allowable 
 format for these coefficients is the same as that of any other numerical 
 
75 
 
 value in ECAP (see Chapter 6). The "Q," may be "E" if the quantity is to be 
 
 » 
 
 a voltage source, "R" for a resistor, and either "BETA" or "GM" for a de- 
 pendent current source. The "J" is the number of the branch in which the 
 current that the "Q" is dependent on flows. The "Ann" represents either 
 the proper branch data reference or the proper dependent current source ref- 
 erence of the original quantity as used in the nominal circuit analysis. 
 Therefore, if in the nominal circuit analysis the following two statements 
 appeared to provide values for V and p respectively: 
 
 B3 N(l,2), R=50,E=-0.3 
 Tl B(3, 1 +),BETA=50 
 
 and it is desired to express V and 3 as functions of the current in 
 
 BE 
 
 branch k, the following statements would be used: 
 
 B3 E(U)=-.3895,-1.62^1E-2,+7.1715E-U 
 Tl BETA(U)=8i+. 41282, 10. 61*133, .V73C-8 
 
 In order to specify the current or currents which are to be used 
 as the criteria for halting the iteration procedure, either of the follow- 
 ing statements, in columns 7-72, may be used: 
 
 CURRENTS=I- ,I.,I,... 
 1 2' 3 
 
 CURRENT=I 
 
 where "I. ,1 ,I_. . ." are the branch numbers of the currents to be examined. 
 
 To specify the tolerance of each current to be examined, either of 
 the following statements in columns 7-72 may be used: 
 
 TOLERANCES^ , T , T- . . . 
 T0LERANCE=T 1 
 
76 
 where "T_,Tp,T . .." are the decimal equivalents of the maximum percentage 
 
 change allowable to stop -che iterations. * The tolerances specified apply 
 to the respective currents given in the "CTJRRENTS. . ." statement. There- 
 fore, if it is desired that a certain procedure continue until the changes 
 in the currents in branches 3 and 12 do not exceed 1% and 3% respectively, 
 the following two statements are necessary: 
 
 CURRENTS=3,12 
 T0LERMCES=.01,.03 
 
 It should be noted that iteration will continue until all the criteria 
 which are specified are met. 
 
 To specify the temperature parameter if the solution is to be 
 calculated for a single temperature the following statement in columns 
 7-72 is used: 
 
 TEMPERATURES T 
 
 where "T" is the desired temperature in degrees centigrade. To carry out 
 the procedure over a range of temperatures the following statement in 
 columns 7-72 is used: 
 
 TEMPERATURE=T. (T )T- 
 i n f 
 
 where "T." is the initial value of temperature in degrees centigrade, "T " 
 is the final value of temperature in degrees centigrade, and "T " is the 
 total number of values in the range other than the initial value to be used 
 in the calculations. For example, to execute the iteration technique every 
 10° from -55° C to 125° C, a total of 19 points, the following statement 
 would be used: 
 
77 
 TEMPERATURE= -55 ( 18 ) 125 
 
 Note : In developing the model of Equation 7.1 the temperature was assumed 
 to be in degrees Kelvin. Although the temperatures in the statements above 
 are given in degrees centigrade, the routine will automatically make the 
 adjustment to degrees Kelvin before evaluating any parameters. 
 
 Finally, to execute the routine after all data statements are en- 
 tered, the "EXECUTE" statement of Chapter 6 is used. The comment statement, 
 although not mentioned above, may be used freely. Also, after the routine 
 completes the iterative process it returns control to ECAP's language 
 processor. 
 
 To complete the chapter, two examples of the use of the routine 
 are given. The first example is the three-transistor feedback amplifier 
 originally discussed in Chapter h, but with slightly different beta func- 
 tions. To provide a valid comparison of the results, the method used in 
 Chapter h was repeated using the new beta function. The second example is 
 the circuit of Chapter 5 evaluated over the same temperature range. 
 
 Results for both circuits are shown for both types of solution. 
 Some justification of the slight differences can be provided from the non- 
 representation of a resistor less branch in ECAP. In previous chapters, the 
 base of the transistor model contained no resistor at all. Since ECAP re- 
 quires some resistance in a branch, very small values were tried, but this 
 was unsatisfactory for the following reason: ECAP calculates node voltages 
 first; with a small base resistor the node voltage difference minus the V 
 drop was very small and the usual errors which arise from subtracting two 
 nearly equal numbers occurred, resulting in relatively inaccurate base cur- 
 rents. Therefore, a larger base resistance was required. To offset this 
 
78 
 resistance, the program was altered to examine the voltage drop across the 
 resistor and then adjust the value of the voltage source to force the 
 branch voltage to be correct. 
 
 For each circuit, a schematic properly drawn for ECAP is given 
 followed by the ECAP source program and then the comparative results. 
 There is also a great deal of data provided by ECAP which is not shown. 
 
 The routine itself is written in FORTRAN-II and is shown in 
 Appendix A. Although this version of ECAP was written for the IBM 1620, 
 the version was modified and recompiled on the I3M 709^, and later recom- 
 piled for the IBM System 360. 
 
 The only significant changes to 1620 ECAP were in the rewriting 
 of the DIMENSION, COMMON and EQUIVALENCE statements to reconcile word 
 length differences and the way in which the University of Illinois' FASTRAN 
 compiler assigns COMMON storage, and the changes in alphameric variable 
 initialization techniques. Otherwise, all other modifications consisted of 
 renaming library subroutines and leaving all 70 subroutines in main storage 
 at one time. One problem in conversion did occur, which was the inability 
 of FASTRAN to handle alphameric input-output (A- type format) with fixed 
 point variables and hence all alphameric variables were renamed to change 
 them to floating point variables. Although the same conversion on the 1620 
 would require more storage, the 709^ assigns one word of storage to both 
 fixed point variables and single precision floating point variables. 
 
79 
 
 13.3 13.3 
 
 r 1 
 
 l *'\ Bui 
 
 47 
 
 IH 
 
 Bsi <L2K 
 
 B 2 i < 
 It 
 
 -L B u i | .68 
 
 Bl *| 33K B 5 ^47 
 
 Q 
 
 Bg| 1 179 
 
 B 14 | 1 1.5 
 
 Figure 27. Three -trans is tor feedback amplifier 
 
80 
 
 TV 
 
 TV. 
 
 V 
 
 Figure 28. Models used for nominal solution of circuit of Figure 27 
 
81 
 
 ♦CONTROL, PRINT 
 
 C 
 
 c 
 c 
 
 Bl 
 
 DC ANALYSIS 
 
 THREE TRANSISTOR FEE 
 
 N(1,0),R=33000 
 
 B2 
 
 N(7,1),R=10000 
 
 B3 
 
 N(l,2),R=50,E=-0.3 
 
 Bit 
 
 N(3,2),R=10.0E6 
 
 B5 
 
 N(2,0),R=U7 
 
 B6 
 
 N(0,3),R=1200,E=12.U 
 
 B7 
 
 N(3, 1 +),R=50,E=-0.3 
 
 B8 
 
 N(5, 1 +),R=10.0E6 
 
 B9 
 
 N(1+,0),R=179 
 
 BIO 
 
 N(0,5),R=U6,E=13.3 
 
 Bll 
 
 N(0,6),R=.68,E=13.3 
 
 B12 
 
 N(6,5),R=5,E=-0.3 
 
 B13 
 
 N(6,7),R=10.0E6 
 
 BlU 
 
 C 
 Tl 
 
 N(7,0),R=1.5 
 
 B(3, i +),BETA=50 
 
 T2 
 
 B(12,13),BETA=100 
 
 C 
 
 
 PRINT , VOLTAGES , CURRENTS 
 
 EXECUTE 
 C 
 
 ITERATE 
 B3 E(U)=-.3895,-1.62i+lE-2,+7.1715E-U 
 Tl BETA (l+)=8U.i+1282, 10.6413 3, .^7308 
 B7 E(8)=-.3895,-1.62UlE-2,+7.1715E-U 
 T2 BETA (8 )=84. 41282,10.64133, +.47308 
 B12 E(l3)=-.29937,-7.8399E-3,+9.3957E-U 
 
 T3 BETA(13 )=98. 98896, 3. 6l4o4, -1.02469 
 CURRENT=l4 
 T0LERANCE=.01 
 EXECUTE 
 END 
 
 Figure 29. ECAP source program for circuit of Figures 27 and 28 
 
 Functional device models are: 
 V BE1 = .3895 + 1.6241 x 10" 2 lnl ci - 7.1715 x 10" ln 2 I cl 
 P x = 84. 1+1282 + 10.64133 LnI cl + .47308 ln 2 I cl 
 
 V BE2 = * 3895 + 1 ' 62kl x 10 " 2 :LnI c2 " 7 * 1715 x 10 " ^ 1 Q2 
 P 2 = 84.41282 + 10.64133 lnl c2 + .47308 Ln 2 I C2 
 
 V B£3 = .29937 + 7.8399 x 10" 3 lnl c3 - 9.3957 x 10 _i+ Ln 2 I c3 
 = 98.98896 + 3.6l4o4 lnl - 1.02469 ln 2 I c3 
 
 I _ in branch 4 
 
 I in branch 8 
 
 I in branch 13 
 C3 
 
82 
 
 Method of Chapter Four Quantity Modified ECAP 
 
 1*0.15 0, 40.1+0 
 
 5^.12 P 2 53.86 
 
 99.53 P 3 99.38 
 
 0.278 V BE1 (volts) 0.279 
 
 0.327 V BE2 (volts) 0.326 
 
 0.300 V (volts) 0.300 
 
 hM I cl (ma) U.25 
 
 32.79 I C2 (ma) 3^.07 
 
 1.07 I.-(ma) 1.12 
 
 89 # of iterations 2 
 
 Table 7-1. Comparison of results for three-transistor amplifier 
 
83 
 
 B 2 |<12K 
 
 1 <► 
 
 f 
 
 B 3 f<4.7K B 5 J£270 
 
 Figure 30. Common emitter amplifier to be evaluated over -55° C 
 to +125° C temperature range 
 
 = 50 
 
 Figure 31. Model used for nominal solution of circuit of Figure 30 
 
84 
 
 *CONTROL, PRINT 
 
 C 
 
 C TEMPERATURE RANGE TEST FOR COMMON EMITTER AMPLIFIER 
 
 C 
 
 DC ANALYSIS 
 C 
 
 Bl N(0,2),R=330,E=l8 
 B2 N (0,l),R= 12000, E=l8 
 B3 N(0,l),R=4700 
 B4 N(l,3),R=500,E=-1.25 
 B5 N(3,0),R=270 
 B6 N(2,3),R=10.0E6 
 C 
 
 Tl B(4,6),BETA=50 
 C 
 
 PRINT , VOLTAGES , CURRENTS 
 
 EXECUTE 
 
 ITERATE 
 C 
 Tl BETA(l)=-57. 6765,-7. 273, -.91,. 301,. 10711E-0U 
 
 Bk e(i)=-i. 39799,+. 14546,+. 01820,+. 00121, +.11849E-05 
 
 TOLERANCES. 01 
 
 CURRENT=1 
 
 TEMPERATURE^ -5 5 ( 18 ) 125 
 C 
 
 EXECUTE 
 END 
 
 Figure 32. ECAP source program for circuit of Figures 30 and 31 
 
 - Functional device model is : 
 P=-57.6765 - 7.273 lnl - .91 lh 2 I c + .301T + .10711 X 10" T 2 
 V=l. 39799 - .14546 mi_ - .01820 ln 2 l„ - .00121T - .11849 x 10" y T 2 
 T in degrees Kelvin 
 I in branch 1 
 
85 
 
 
 UN 
 
 Jt 
 
 CM 
 
 o 
 
 ON 
 
 t^- 
 
 un 
 
 oo 
 
 CO 
 
 CO 
 
 oo 
 
 oo 
 
 OJ 
 
 CM 
 
 CO 
 
 CM 
 
 CM 
 
 ON 00 VO 4 CM 
 
 s un m 
 boo 
 
 H 
 
 H r-l 
 
 H 
 O 
 
 0) 
 
 W 
 
 I 
 
 1 
 
 CO. 
 
 UN CO ON O 
 
 -4" 
 
 Q ON CO CO 
 
 UN NO CO ON ON O 
 
 c— vo in -4- -4- oo oo o-i cm 
 
 rH CM OO -4" UN NO t— CO ONO 
 
 CM 
 CM 
 
 UN CO 
 CM CM 
 
 oo oo 
 
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 m _4 -a- -4- 
 
 O M vd On CM if\ CO 
 
 UN UN UN UN NO NO NO 
 
 ^ 
 
 9 
 
 CO 
 CM 
 
 CM UN CO 
 t- t- t- 
 
 t"- CM CM NO CO 
 
 U\ O 4- l> O 
 
 NO CM NO 
 ro NO CO 
 
 CO On On On O 
 
 O 
 
 8 
 
 ON 
 CM 
 
 s 
 
 t^ 1A W CO 4 ON J- CO 
 NOCOO H oo _4- NO D- 
 
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 CM 
 
 CM CM 
 H H 
 
 CM CM CM 
 
 P 
 
 a 
 u 
 
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 +3 
 <D 
 •H 
 
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 0) 
 
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 p 
 
 PC 
 
 UN .4- CM O 
 
 oo ro co oo 
 
 ON 
 
 r- 
 
 LfN 
 
 no 
 
 rH 
 
 ON 
 
 co 
 
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 CJ 
 
 OJ 
 
 CM 
 
 CM 
 
 CM 
 
 H 
 
 H 
 
 H 
 
 -4" CM 
 
 O 0- UN oo H 
 H O O O O 
 
 > 
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 -P 
 
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 ca 
 
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 -4" 
 
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 C~- ON ON ON ON CO 
 UN NO t- CO ON O 
 
 r- 
 
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 h VO ITi 4 4 
 CM CO -4" UN NO 
 
 0O CO 
 t- CO 
 
 CM CM 
 ON O 
 
 CM 
 CM 
 
 UN CO 
 CM CM 
 
 H _4 t>- <H -4" C-- O 0O NO ON OJ UNCO 
 PO 0O m 4 4 4 UNUNUNUNNONDNO 
 
 •1 
 
 CM 
 H 
 
 PO 
 CM 
 
 CM UN CO 
 
 o- t~- t— 
 
 C~- CM 
 UN O 
 
 H 
 
 -4" 
 
 NO 
 
 o 
 
 NO CM oo 
 0O NO CO 
 
 ON CO t- UN CM CO -4" CN-4- 
 CM-4-VO00 O H oo _4" NO 
 
 CO ON ON ON O 
 
 O 
 H 
 
 H CM 
 H H 
 
 CO 
 
 CM CM CM CM CM 
 H H H H H 
 
 d) 
 
 Sh 
 
 0) 
 
 •H 
 <H 
 •H 
 
 H 
 
 I 
 
 rH 
 <L> 
 P 
 
 P 
 
 •H 
 
 e 
 o 
 
 o 
 o 
 
 Sh 
 O 
 
 <H 
 
 w 
 P 
 
 ■3 
 
 w 
 (D 
 
 •in 
 O 
 
 O 
 
 P 
 
 aJ 
 
 rH 
 
 3 
 
 fH 
 
 UN 
 
 UN 
 
 UN 
 
 UN 
 
 UN 
 
 -4- 
 
 OO 
 
 CM 
 
 1 
 
 1 
 
 1 
 
 1 
 
 UN UN UN UN 
 
 UN 
 CM 
 
 UN 
 OO 
 
 UN 
 
 -4- 
 
 UN UN 
 UN NO 
 
 UN UN 
 C- CO 
 
 UN UN UN UN 
 
 ON O rH CM 
 
 H r-i H 
 
 s 
 
 CM 
 
 l 
 
 ■3 
 
86 
 8. CONCLUSION 
 
 A method has been developed for solving the simultaneous non-linear 
 equations which arise from introducing non-linear elements into electronic 
 circuits. The method has been implemented by modifying an existing 
 program, ECAP, which is capable of solving linear circuits. The purpose 
 of this chapter is to comment on the extensions and limitations of the 
 method. 
 
 The first limitation is in the assumption made at the beginning 
 of the development, that only models of transistors in their active range 
 were to be introduced. The other two regions, saturation and cutoff, were 
 ignored. Saturation can be modeled by the addition of a programmed switch 
 which is used to test the collector-to-emitter voltage of the transistor. 
 Should this voltage go negative (for a PNP transistor), the program can 
 replace the current generator and resistor in the branch with an equivalent 
 of a short circuit, or for greater accuracy, a voltage generator 
 representing the voltage drop across the junctions. In either case, 
 after the change is made another iteration is made and the results examined, 
 In this case, the current in the collector-to-emitter branch must be checkec 
 to see if the saturation conditions are still satisfied if the previous 
 configuration is assumed. 
 
 Modeling the cutoff region of a transistor is slightly more 
 difficult. It is impossible to rely on the model equations to force 
 cutoff conditions which can be detected and force the model to be 
 cnanged as in saturation. Basically, the problem is due to the presence 
 of the logarithm terms in the model. These terms force the models to 
 assume values approaching negative infinity for very small current values. 
 
87 
 The easiest way to avoid this is to obtain parameter values for small 
 current values empirically, and then use the regression techniques to 
 estimate coefficients of the current model with the addition of an 
 exponential term. With proper choice of coefficients, the exponential 
 should be extremely large and positive for the small current values 
 forcing the logarithm terms to be negative. If these terms balance 
 properly, the parameter values should tend toward zero for small current 
 values, while for current values in the active range the exponential should 
 be near zero and thus have little effect. With this modification to the 
 model, the transition to cutoff should be easier to make and be less prone 
 to oscillation. It is conceivable that the switch technique and the extra 
 exponential term could also be used to emulate the reverse transistor 
 mode if desired. 
 
 There is some question as to the applicability of the method to 
 the transient analysis of d.c. circuits. The major problem in extending 
 the method is that the nature of transient analysis requires that the circuit 
 be simulated, not solved. The simulation is usually done with a fixed 
 time increment clock, because of the difficulty of calculation of 
 future event times required for variable time increment simulations. 
 The problem is that the method developed in this paper is, in essence, 
 a variable time increment simulation. By attempting to run this 
 simulation within a simulation, the circuit could conceivably reach 
 steady state within the first time increment, or worse yet, simulate 
 the unstable nature of the circuit within the same first time 
 
88 
 increment. The only suggestion this author can make to curcumvent this 
 problem is to use very small time increments, and to re-evaluate all 
 parameter values at each increment. If the increments are small, the 
 parameter changes should also be small and the resulting simulation should 
 be reasonably close to the real world. 
 
 Finally, the method developed in this paper and the questions 
 raised in this conclusion will hopefully become the subject of further 
 investigation. 
 
89 
 
 LIST OF REFERENCES 
 
 [l] Fitchen, F. C, Transistor Circuit Analysis and Design , 
 D. Van Nostrand Co., Inc., Princeton, New Jersey, 1900. 
 
 [2] Seshu, S. and Balabanian, N. , Linear Network Analysis , John Wiley 
 and Sons, Inc., New York, I96U. 
 
 [3] Editorial Staff, G. E. Transistor Manual , Semiconductor Products 
 Department, Advertising and Sales Promotion, General Electric 
 Company, Syracuse, New York, Seventh Edition, I96U. 
 
 [h] Editorial Staff, "1620 Electronic Circuit Analysis Program (ECAP)," 
 User's Manual (l620-EE-02X) , IBM Corp., Poughkeepsie, New York. 
 
 [5] Editorial Staff, "IBM 1620 Electronic Circuit Analysis Program 
 (ECAP)," System Manual (l620-EE-02X) , IBM Corp., Poughkeepsie, 
 New York. 
 
90 
 
 APPENDIX A 
 
 SUBROUTINE GUTHS1 
 
 THIS SUBROUTINE PERFORMS NON-LINEAR ITERATIONS FOR ECAP AFTER 
 READING CONTROL PARAMETERS FROM THE CONTROL CARDS DESCRIBED IN 
 CHAPTER 7. 
 
 THE REQUIRED ECAP SUBROUTINES: ECB09, ECB22, ECR23, ECB24, ECB25 
 AND ECB26 ARE IDENTICAL TO THEIR ECAXX COUNTERPARTS BUT WERE 
 DUPLICATED AND RENEMED FOR OVERLAY PURPOSES. 
 
 THF ECAP MAIN PROGRAM, ECA01 
 TO LINK TO THIS SUBROUTINE. 
 
 AND ECA06 REQUIRE MINOR MODIFICATIONS 
 
 THE COMMON REQUIREMENTS IN ALL ECAP SUBROUTINES MUST BE CHANGED TO 
 ALIGN WITH COMMON IN THIS SUBROUTINE. 
 
 COMMON 
 DOUBLE 
 COMMON 
 1NPR INT( 
 COMMON 
 COMMON 
 COMMON 
 COMMON 
 COMMON 
 COMMON 
 COMMON 
 COMMON 
 COMMON 
 COMMON 
 COMMON 
 COMMON 
 COMMON 
 COMMON 
 COMMON 
 DOUBLE 
 01 MENS I 
 DIMENSI 
 
 CCSAV(6,200) .1 
 PRECISION 2PRL 
 NMAX,NNODE,NTE 
 10) 
 
 F(200) ,EMIN(20 
 Y(200) ,YMIN(20 
 YTERM(200) ,YTE 
 ERR0R1, ISEO,MS 
 MOBRNI 50) ,MOPA 
 AX1 t SMLEP(50) , 
 EB(200) ,AMPX(2 
 JX1 , JX4, JX5,DE 
 NWOROS(72) ,NMC 
 INPUTB(9) ,NBCD 
 INVAL,LL,ICOL, 
 M2,M3,KCARO,KG 
 EOUI VIM(20) ,KOU 
 MATA(200,4,3) , 
 WCMAX( 50) tWCMI 
 PRECISION SMLE 
 ON NITER (6,2) , 
 ON ICORP(25),T 
 
 DW0RD(74) 
 
 (50,50) 
 
 RMS, NUMB L,NUMBR,NUMBC, IRTN,NTRACE , NSWTCH, KTO, 
 
 0) »EMAX(200) , AMP (200) ,AMPMIN(200) ,AMPMAX(200) 
 
 0) ,YMAX(20O),NINIT(20O),MFIN(200)tMODEK2OO) 
 
 RMH(200) ,YTERML(200) ,IR0WT(200) , I COLT (200) 
 
 EQ,M0,NUMM0,VFIRST(50),VSECND(50>, VLAST(50) 
 
 RM(50) ,M0STEP(50) , IWC0UT(4) 
 
 CURR(200),SMLE(200)»EQUCUR(50),EX(2 00) 
 
 00),AMPB(200) ,VN0M(50) ,ST0SQ(50» ,L t M,IITOL 
 
 LTA,DUM1(28) 
 
 0(2,20) ,KLABEL(4) ,KPUNC ( 5 ) , INDC < 2 , 20 ) 
 
 (20),KTYPE(5),NBLANK,NOEXEC, I TOL ♦ NEOU IM, P IC 
 
 LTYPE,KC0L,NQUIT,ITRANS,K0,KS,KELAST,NUM,M1 
 
 ,NP,NTR,MAC,HNODE,TNUM,NUEL,NOE,NOI,NOIC 
 
 T(2,10) 
 
 YX(200) ,YB(200),YTERMX(200),YTERMB(200) 
 
 N(50) 
 
 P,CURR,SMLE,EQUCUR 
 
 COEFS<50,5) , ICRES(50) , IPTYPE(50) , IPL0C(50) 
 
 OL(25) ,AMP0L0(25),BETA(200),GM(200) 
 
 INITIALIZE £ DEFINE DICTIONARY f. INDICATORS 
 
 IF (NTRACE) 1,3,1 
 
 WRITE (6,2) 
 
 FORMAT (' SUBROUTINE 
 
 GUTHS1 ENTERED'/) 
 
 NI TER ( 1 » 1 ) = 
 NITER( 1,2)= 
 NITER(2,1 ) = 
 NITFR(2,2)= 
 NITER (3,1 ) = 
 NITFRI 3,2)= 
 NI TER<4,2)= 
 N[TFR(4,1 ) = 
 NITFR (5,1 ) = 
 NITFRI 5,2)= 
 NITER (6,1 ) = 
 NITFR<6,2)= 
 DO 300 1=1,50 
 
 -4R232B512 
 -985644992 
 -1019199424 
 -^65551296 
 -4R232R512 
 -700432320 
 -415219648 
 -PR564A992 
 -7339B6752 
 -700432320 
 -650100672 
 -9R5644992 
 
91 
 
 ICRESi I)«0 
 IPTYPEI ] )»0 
 IPLOC( I )«0 
 00 300 J«l,5 
 
 300 C0EFS( l,J)-0.0 
 00 301 1-1,25 
 ICURR( I )«0 
 T0L( 1 )»0.0 
 
 301 AMP0LD( I )-0.0 
 00 302 I»l,200 
 BETA( I )«0.0 
 
 302 GM( I )-0.0 
 INDCUR-0 
 1NDT0L"0 
 INDTEM«0 
 TFMP-0.0 
 TEMPI*0.0 
 TFMPFxO.O 
 TEMPC=0.0 
 I INUM»0 
 ITEMP2M 
 
 C 
 
 C READ L LIST DATA CARO 
 
 C 
 
 1000 READ ( 5,4) NWURDS 
 
 4 FORMAT (72AI) 
 WRITE (6,5) NWOROS 
 
 5 FORMAT ( 1X,72A1 ) 
 KCAR0=KCARD+1 
 NOEXEC=N0EXEC+NQUIT 
 
 C 
 
 C CHECK FOR ' ID' CARD 
 
 C 
 
 IF <NWORDS< 1 >-INDC( 1,15) ) 1004, 1001 , 100* 
 
 1001 IF (NW0RDS(2)-NMC0(1,1) ) 1004,1002,1004 
 
 1002 00 1003 ICOL=l,72 
 
 1003 I0W0RD( ICOL)=NWOROS( ICOL » 
 GO TO 1000 
 
 C 
 
 C CHECK FOR 'COMMENT' CARD 
 
 C 
 
 C SHIFT LEF1 COLUMS 7-72, ELIMINATING BLANKS 
 
 C 
 
 1004 IF (NWORL)S< l)-INPUTB(B) ) 2000,1000,2000 
 2000 KC0L=6 
 
 c 
 
 DO 7 IC0L=7,72 
 
 IF (NW0R!)S( ICUL )-NBLANK) 6,7,6 
 
 6 KC0L=KC0L+1 
 NWORDS(KCUL )»NwORDS( ICOL ) 
 
 7 CONTINUE 
 C 
 
 C CHECK CONTENTS OF COLUMNS 1-6 
 C 
 
 00 11 IC0L=1,5 
 
 IF (KWOROSI ICOD-NBLANK) 8,11,8 
 A DO 9 LTYPE=1,2 
 
92 
 
 IF (NW0R0S< ICOL)-KLABEL(LTYPE)) 9,200,9 
 9 CONTINUE 
 M3 = 5 
 15 ITRANS=6 
 
 10 WRITE (6,3006) M3 ,KCARD, ICOL 
 N0UIT=1 
 
 GO TO 1000 
 3006 FORMAT CO ***** ERROR *«,I3 f « CARD #«,I3,« APPROX. COL.', 
 
 11 CONTINUE 
 
 IF (KCOL-6) 500,12,13 
 
 12 M3 = 4 
 
 GO TO 15 
 
 500 ITRANS=5 
 
 GO TO 10 
 
 CHECK FOR TEMPERATURE, CURRENT, TOLERANCE, EXECUTE, MOOIFY OR 
 RETURN STATEMENT, INDEX NUMBERS 1,2,. ..,6 RESPECTIVELY 
 
 13 IC0L=7 
 DO 20 IDENT^1,6 
 IF <NWORDSUCOL)-NITER( IDENT,1) ) 20,14,20 
 
 14 IF (NWORDS( IC0L+1)-NITFR< IDENT,2) ) 20,25,20 
 
 20 CONTINUE 
 M3=12 
 GO TO 15 
 
 21 M3=34 
 GO TO 15 
 
 25 GO TO (26,26,26,8000,4000,9999) , IDENT 
 
 GFT PAST •=• SIGN ON TOLERANCE, TEMPERATURE OR CURRENTS 
 
 2<S ICOLMCOL + 1 
 
 IF (ICOL-KCUL) 27,21,21 
 27 IF (NWORi)S( IC0L)-KPUNC(1 ) ) 26,28,26 
 2R IC0L=IC0L+1 
 
 GO TO (50,29,39) ,IDENT 
 
 PRHCFSS TOLERANCES AND/OR CURRENTS 
 
 29 IE < JNDCUR ) 21,30,21 
 
 30 INOCURsl 
 4 1 1=0 
 
 31 CALL. ECB09 
 1 = 1 + 1 
 NUM=TNUM 
 IF (1-25) 42,42,21 
 
 32 ICURR(I)=NUM 
 IT=I 
 
 33 IC0L=IC0L+1 
 IE (ICOL-KCOL) 34,34,1000 
 
 34 IF (NWORDS( ICOL )-KPUNC( 3) ) 36,35,36 
 
 35 ICOL=ICOL+1 
 GO TO 31 
 
 36 M3=34 
 GO TO 15 
 
 39 IP ( INDTOL ) 21 ,40,21 
 
 40 INUT0L=1 
 
 13/) 
 
93 
 
 
 
 GO TO 41 
 
 
 42 
 
 GO TO (500,32,43) ,IDENT 
 
 
 ~3 
 
 TOL ( I ) = TNUM 
 
 JT* 1 
 
 GO TO 33 
 
 c 
 
 
 
 c 
 
 
 
 c 
 c 
 
 
 PROCESS TEMPERATURE 
 
 50 
 
 IF (ICOL-KCOL) 51,51,36 
 
 
 51 
 
 IF ( INDTEM) 36,52,36 
 
 
 52 
 
 INDTEM=1 
 
 CALL ECB09 
 
 TFMPI=TNt)M 
 
 IC0L«IC0L+1 
 
 IF (ICOL-KCOL) 54,54,53 
 
 
 53 
 
 TFMP=TFMPI+273.0 
 
 ITEMP2=1 
 
 GO TO 1000 
 
 
 54 
 
 IF (NWORDSl 1C0L)-KPUNC(2) ) 
 
 
 55 
 
 ICOL=ICOL+l 
 
 CALL ECBOQ 
 
 TEMPO TNUM 
 
 ITFMP2=2 
 
 ICOL=ICOL+1 
 
 IF (ICOL-KCOL) 56,56,36 
 
 
 56 
 
 IF <NWORI)S( IC0L)-KPUNC(4) ) 
 
 
 57 
 
 IC0L=IC0L+1 
 CALL ECBOS) 
 TFMPF=TNUh 
 GO TO 1000 
 
 36,55,36 
 
 36,57,36 
 
 C 
 
 C GET COEFFICIENTS L DATA TYPE 
 
 C 
 
 200 IC01MC0L + 1 
 
 IF (ICOL-KCOL) 201,201,21 
 
 201 I INOM- I INl'M^L 
 
 IF (IINUM--50) 203,203,202 
 
 202 M3=36 
 
 GO TO 1 5 
 
 203 CALL ECB09 
 NI)M = TNUM 
 
 IPLOCf 1 INUM)=NUM 
 
 IF (NwDR()S(7)-INPUTB(5) ) 204,207,204 
 
 204 IF (NWDR0S(7)-INPUTB(2) ) 205,208,205 
 
 205 IF (NW0R0S(7)-INPUTB(4) ) 206,209,206 
 
 206 IF <NW0R0S(7)-JNPUTB(3> ) 225,224,225 
 
 207 MTYPE=1 
 MJ TO 210 
 
 208 MTYPE=2 
 GO TO 210 
 
 209 MTYPE=3 
 
 211 IC0L=IC0L+1 
 
 210 IPTYPE( I INUM)=MTYPE 
 
 IF (ICOL-KCOL) 212,212,21 
 
 212 IF (NWORDSI I COL ) -KPUNC < 2 ) ) 211,213,211 
 
 213 IOiL = IC0L+l 
 
94 
 
 IF (ICOL-KCOL) 214,214, 2i 
 
 214 CALL ECB09 
 
 NUM=TNUM 
 
 ICRESI IINUM)=NUM 
 
 ICCLMCOL + 1 
 
 IF ( ICOL-KCOL) 215,215,21 
 
 215 IF (NWORDSt ICOL ) -KPUNC ( 4 ) ) 206,216,206 
 
 216 IC0L=IC0L+1 
 
 IF (ICOL-KCOL) 217,217,21 
 
 217 IF <NWORDS( I COL )-KPUNC ( 1 ) ) 206,218,206 
 2 18 I1C0L=0 
 
 222 IC0L=IC0L+1 
 
 IF (ICOL-KCOL) 220,220,219 
 
 219 IF (IICOL) 500,206,1000 
 
 220 IIC0L=IIC0L+1 
 
 IF (IIC0L-5) 223,223,206 
 
 223 CALL ECB09 
 
 C0EFS( I INUM, I ICOL )=TNUM 
 
 IC0L=IC0L+1 
 
 IF (ICOL-KCOL) 221,221,1000 
 
 221 IF (MWORDS( ICOL >-KPUNC ( 3 ) ) 206,222,206 
 
 224 MTYPE=4 
 GO TO 210 
 
 22 5 M3--36 
 
 GO TO 15 
 C 
 
 C BEGIN EXECUTION OF ITERATION TECHNIQUE 
 C 
 8000 IF (NTRACE) 8901,8900,8901 
 H401 WRITE (6,8908) 
 
 WRITE (6,8902) ( TOL ( I ) , I = 1 , I T ) 
 
 WRITE (6,«903) ( ICURR ( I ) , I = 1 , I T ) 
 
 WRITE (6,8906) 
 
 WRITE (6,8904) < ( COEFS ( I , J ) , J= 1 , 5 ) , I = 1 , I I NUM ) 
 
 WRITF (6,890 7) 
 
 WRITE (6,8905) ( I , ICRES ( I ) , I PTYPE ( I ) , I PLOC ( I ) , I =1 , 20 ) 
 
 WR I IE (6,8911 ) 
 
 WRITE (6,8910) ( CURR ( J ) , J= 1 ,NMAX ) 
 
 8902 FORMAT ( • • , 10F 10 .4 ) 
 
 8903 FORMAT ( '0' ,10110) 
 H904 FORMAT ( • • ,5E1 7.7) 
 
 8905 FORMAT ( • • , 13,3110) 
 
 8906 FORMAT ( • OCOEFF IC I ENTS : • / ) 
 
 8907 FORMAT (»0 I«,7X, 'ICRES IPTYPE IPLOC'/) 
 
 8908 FORMAT ( • OTUL ER ANCES AND CURRENTS:*/) 
 H910 FORMAT ( « • ,8E16.7) 
 
 8911 FORMAT ( « OC URRENTS ' / ) 
 
 HVOO IF ( INDCUR+INOTOL-2) 8001,8002,8001 
 
 H001 M3=35 
 
 GO TO 15 
 *»<? IF ilf-JI) 8003,8004,8003 
 8003 M3=36 
 
 GO 10 15 
 r'iiO^ CONTINUE 
 
 NUM»0 
 
 GO TO (8098,8050) , ITEMP2 
 
95 
 
 C SINGLE TEMPERATURE 
 C 
 8008 CONTINUE 
 
 60 TO 1000 
 
 c 
 
 C RANGE OF TEMPERATURES 
 
 C 
 8050 TEMPOITEMPH-TEMPI I/TEMPC 
 
 TEMPF=TEMPF+273.0 
 
 TFMPI=fEMPlT273.0 
 
 TEMP=TEMPI 
 
 GO TO 8098 
 
 8053 TEMP=TEMP+TEMPC 
 NUM = 
 
 IF (TtMP-TEMPF) 8098» 8098 ,8054 
 
 8054 CONTINUE 
 GO TO 1000 
 
 C 
 
 C STORE PRESENT CURRENT VALUES 
 
 C 
 
 8098 00 8099 1 = 1. IT 
 J=ICURR< I ) 
 
 8099 A*POL0( ! )=CURR( J ) 
 NUM = NUM+ 1 
 
 C 
 
 C CALCULATE NEW DEPENDENT VALUES 
 
 C 
 
 8100 DO 8105 1=1 ,1 INUM 
 ■ )-ICRES( I ) 
 ALCUR=DLOG(CURR < J ) ) 
 
 VALUE =C0EFS( I ,1 ) +ALCUR* < COEFS < I , 2 > +CUEFS ( I , 3 ) *ALCUR ) 
 1 +TEMP*( COEFS ( I,4)+C0EFS< I,5)*TEMP) 
 
 MTYt>E=IPTYPE< I ) 
 
 GO TO (8101, 8102,8103, 8104) ,MTYPE 
 HiOl E< I I ) = VALUE*CCSAV< I 1,3) 
 
 GO TO 8105 
 8102 BETA! I I ) = VALUE 
 
 NBRM=ICOLT( ! I ) 
 
 YTERM( II !=VALUF.*Y(NBRN) 
 
 GO TO 8105 
 8 103 GM( I I )= VALUE 
 
 YTERM( I I )=VALUE 
 
 GO TO 8105 
 8104 Y(NBRN)=1 .0/VALUE 
 - 105 CONTINUE 
 C 
 
 C SOLVE DC PROBLEM 
 C 
 
 DO 8106 I=1,NMAX 
 
 YX( I )=Y( I ) 
 
 EX( I ) = E( I ) 
 HlOfc AMPX( I )=AMP ( I ) 
 
 IF (NTERMS) 8107,8109,8107 
 B107 00 8108 1 = 1 , NTERMS 
 
 8108 YTERMX( I ) = YTERM( I ) 
 
 8109 CALL ECB22( ZPRL) 
 CALL ECB23 
 
96 
 
 CALL ECB25 
 CALL tCB26(ZPRL) 
 IF (NUM-20) 8200,8300,8200 
 C 
 
 C CHECK TOLERANCES 
 C 
 8200 00 8201 1 = 1, IT 
 J=ICURR( I ) 
 SAVE=CURR(J) 
 
 IF < ABSUMPOLDU »-SAVE)-ABS(AKPOLD(n*TOL<n ) ) 8201,8201,8098 
 «?01 CONTINUE 
 C 
 
 C OUTPUT RESULTS 
 C 
 B302 WRITE (6,8303) NU»* 
 
 >3 FORMAT (•- NUMBER OF ITERATIONS: ',13/) 
 IF (INOTEM) 8202„8203„8202 
 
 8202 !'eMPA=TEMP~273„0 
 WRITE (6,9000) TEMPA 
 
 9000 FORMAT ( » f EMPERATURE : 8 ,F10.3/) 
 
 8203 DO 8204 I=1,NMAX 
 YX( I ) = Y( I ) 
 
 EX I I )=E( ! ) 
 
 8204 AMPX{ I )=AMP( I ) 
 
 IF (NTERMS) 8205,8207,8205 
 *205 DO 0206 I = 1,'\JTERMS 
 B206 YTERMX( I )^=YTERM{ I ) 
 M>07 CALL ECB22(ZPRL) 
 CALL ECB23 
 
 IF (NPRINT(IO)) 107,107,108 
 10S JX1=1 
 
 CALL ECB2MZPRL) 
 07 CALL fcCB26(7.PRL) 
 NTR=1 
 
 IF iNPRINTUO)) 103*103,104 
 JX1---2 
 
 CALL cCB2MZPRL> 
 I.C3 CALL ECB25 
 NTR-4 
 
 WRITE (6,9002) < I , ICOLT U ) , I ROWT ( I ) , BETA { I ) ,GM( I) , YTERM( I) , 
 I I=1,IMTERMS) 
 
 WRITE (6,9001) 
 )1 FORMAT (//• T-NUMBER» ,8X,« IC0LT«,12X,» IR0WT»,6X, •BETA' ,11X, «GM« f 
 LUX, 'YTtRM'/ ) 
 FORMAT ( 3X, I4,llX,I4,13X,i4,2F15.7,E15.7) 
 GO TO (POOR, 8053) , ITFMP2 
 100 WRITE (6,8301 ) 
 . 01 F.irfMAT MONO CONVERGENCE AFTER 20 ITERATIONS'/) 
 TO 8 302 
 
 FUTURE MODIFY ROUTINE 
 
 00 CONTINUE 
 
 TO 1000 
 
 (-/IT TO MAIN ROUTINE 
 
97 
 
 9999 RETURN 
 END 
 
98 
 APPENDIX B 
 
 COMMON A,ACHG, ICDCT,KCHG 
 
 DOUBLE PRECISION A ( 40 ) , ACHG ( 40, 4) ,0LD, ICDCT 
 OOUBLE PRECISION A I D ( 20 ) , CS < 20 » ,C ( 20, 20 ) , V ( 20 ) , BB ( 20 ) 
 DOUBLE PRECISION TST , SSS , STDV ,SPST 
 
 DOUBLE PRECISION AMEAN,CD, AKNT , SOUT, S IGN, PCT , STER, AST 
 DOUBLE PRECISION BETA , BVAR, BSTD, TRAT , S I ZE , AM, DF,RR ,R , ADJR, ADJRR 
 DIMENSION TITLE( 18),FMT IN ( 18 ) , FMTOUT { 18 ) , A I ( 40 ) , ANAM ( 25, 40 ) 
 DATA ANAM/»C» , , 0«,«N',«S , , , T», , A», , N , » , T»,« •» , T» f , E , t , R , » , M , f 
 19H?*' •/ 
 
 C 
 
 C STEPWISE MULTIPLE LINEAR REGRESSIUN PROGRAM 
 
 C 
 
 (. CONTROL CARD FORMAT: 
 
 C 
 
 C 1. HEADING CARD - FORMAT (18A4) 
 
 C THE CONTENTS OF THIS CARD ARE PRINTED AS A HEADING ON EVERY 
 
 C PAGE OF OUTPUT. 
 
 C 
 
 C 2. PARAMETER CARD - FORMAT (12,13,12) 
 
 f A. COLS 1-2: NIND = # OF INPUT VARIABLES TO BE READ AS DATA. 
 
 C B. COLS 4-5: NVAR = NIND + VARIABLES CREATED BY TRANSFORMATIONS. 
 C. COL 7: ICHG = 1 IF ANY DATA TRANSFORMATIONS 
 
 C = IF NO DATA TRANSFORMATIONS 
 
 C 
 
 C 3. OATA VARIABLE NAME CARDS - FORMAT (24A1) 
 
 C ONE CARU FOR tACH VARIABLE (IN ORDER) CONTAINING THE VARIABLE 
 
 C NAME IN COLUMNS 1-24. THIS INCLUDES ALL VARIABLES BOTH READ IN 
 
 C AND CREATEIJ BY TRANSFORMATIONS 
 
 C 
 
 C 4. INPUT DATA FORMAT CARD - FORMAT (18A4) 
 
 C STANDARD FORTRAN FORMAT, INCLUDING PARENTHESES, USED TO READ 
 
 C THE INPUT DATA. FOR EXAMPLE: (6F10.3) 
 
 C 
 
 C 5. OUTPUT DATA FORMAT CARD - FORMAT (18A4) 
 
 SAME AS 4. ABOVE, EXCEPT USED FOR PRINTING INPUT DATA, 
 
 r. 
 
 TOL=0. 00005 
 
 c 
 
 f 6. INPUT OATA TRANSFORMATION CARDS - FORMAT ( 5X , 3 1 3,4X , F9.0 ) 
 C NOTE: THESE CARDS MOST BE OMITTED IF ICHG=0 IN 2. ABOVE. 
 C A. TRANSFORMATION CARD FIELOS: 
 
 (. COLS 7- 8: I (FIXED POINT FORMAT) 
 
 C COLS 10-11 : J (FIXED POINT FORMAT) 
 
 C COLS 13-14: K (FIXED POINT FORMAT) 
 
 C COLS 19-27: L OR DL (FLOATING POINT FORMAT) 
 
 C B. I: TRANSFORMATION CODE, INTREPETED AS FOLLOWS: 
 
 C I TRANSFORMATION 
 
 C 01 A(K) = A( J) ** DL 
 
 C 02 A(K) = 1.0 / (A(J) ** DL ) 
 
 C 03 A(K)=A(J)*A(L) 
 
 04 A(K) = A( J) / A(L ) 
 C OD A(K ) = A( J) - A(L) 
 
 C 06 A(K ) = SORT (A (J) ) 
 
 C 07 A(K) a ELOG(A(J>) 
 
 C OR A(K ) = FXPF(A< J) ) 
 
 09 A(K)=A(J)+A(L) 
 
 10 A(K) = SEQUENCE NUMBER OF DATA CARO 
 
 
99 
 
 C 11 »UI » AIJ) ♦ DL 
 
 C 12 AlK) = A(J) * DL 
 
 C 
 
 C C. THE SET Oh TRANSFORMATION CARDS MUST BE FOLLOWED BY A 360 
 
 C DATA SET DELIMITER CARD (/*>. 
 
 C 
 
 1*0 
 C 
 
 C 7. DATA CARDS - FORMAT GIVEN IN 4. ABOVE. 
 
 C THE INPUT DATA CARDS MUST BE FOLLOWED BY A 360 DATA SET 
 
 C DELIMI VER CARD ( /*) . 
 
 c 
 
 C 8. MODEL SELECTION CARDS - FORMAT (40F2.0) 
 
 C BEGINING WITH COLUMN 2, EVERY OTHER COLUMN (I.E.. 2,4,6,8,...) 
 
 C CORRESPONDS TO THE RESPECTIVE DATA VARIABLE (I.E., 1,2,3,4,...) 
 
 C. THE CONTENTS OF THESE COLUMNS DETERMINES THE DISPOSITION OF THE 
 
 C VARIABLE FOR THE REGRESSION CARRIED OUT AS FOLLOWS: 
 
 C 0: VARIABLE NOT USED 
 
 C l: INDEPENDENT VARIABLE 
 
 C 2: DEPENDENT VARIABLE 
 
 C 3: RESTART PROGRAM, I.E., RETURN TO 1. ABOVE 
 
 C 4: END OF PROGRAM - RETURN CONTROL TO SYSTEM 
 
 C NOTE: AS MANY MODEL CARDS AS DESIRED MAY BE USED ; EACH CARD 
 
 C WILL CAUSE THE PROPER REGRESSION TO Bb CARRIED OUT. 
 
 C 9. THE LAST DATA CARD OF ANY KIND MUST BE A 360 DATA SET DELIMITER 
 
 C CARD (/*). 
 
 f. 
 
 •510 FORMAT ( 24A1 ) 
 
 b 1 1 FORMAT |i VARIABLE *',I3,«: ',24A1/) 
 
 615 FORMAT (//• INPUT DATA:'//) 
 
 iuOO FORMAT ( 12,13,12) 
 
 1U01 FORMAT (18A4) 
 
 1002 FORMAT ( • 1 ' ,2X,18A4) 
 
 1006 FORMAT (40(F1.0,1X) ) 
 
 lo56 FORMAT (1RA4) 
 
 I0b7 FORMAT (//• DATA INPUT FORMAT: »18A4) 
 
 1058 FORMAT (//• DATA OUTPUT FORMAT: »18A4) 
 
 hUOl FORMAT (6X.F2.0, 1X,F2.0, 1 X , F2 . , IX, F6.0 ) 
 
 H002 FORMAT ( ' • ,2X , ' ACHG ( • , I 2 , • ) = • , F3.0 , IX , F3.0, IX , F3.0 , 1 X, F6.0) 
 
 •*J00 FORMAT (1H0,10H C(I,J)= ,6F6.2//) 
 
 «*OG2 FORMAT (1H,7H SIZE= ,F10.2) 
 
 1066 FORMAT (•-•,2X,'VAR NO. • , 6X , • NAME • , 2 1 X , • MEAN • , 3X , • POP STD DEV», 
 12X, 'SAMP STU UEV / ) 
 
 1067 FORMAT (' ' , I 5 , 5X , 24A 1 , 3F12 . 5 ) 
 
 '♦Bft FORMAT (4^H0TOO FEW DEGREES OF FREEDOM, TRY ANOTHER E0N/14H SAMPLE 
 
 I SIZE =/18HINDEP VAR IN EON =,F5.0) 
 
 2000 FORMAT («QVAR NO . • , I 3 , • LEADS TO SINGOLARITY VALUE IS',F12.8) 
 
 ^♦46 FORMAT (///2X, • I NT ERCORREL AT I ON MATRIX') 
 
 <*bb FORMAT ( 7X , 24A1 , 5X , I 4 , 2X , 16F6.2 ) 
 
 ^^>9 FORMAT (40X,8I6//24X,9I5) 
 
 3J09 FORMAT ( •-• ,18X, 'DEPENDENT VARIABLE IS NUMBER -• , I 3, • - • , 3X , 24A1 ) 
 
 ^90 FORMAT (' ', 1 5X ,' SAMPLE SIZE =•, F6. 1 , 7X , 'DEGREES OF FREEDOM =',F6. 
 
 II ) 
 
 3010 FORMAT ( •0',6X, , R**2 = «,Fb.3,7X,'R = • , F5. 3, 8X , • STD ERR OF EST =• 
 1 ,Fft.3) 
 <*72 FORMAT (•0 , ,2x,'AOJ R**2 = ' , F5. 3, 3X, ' ADJ R = • , F5. 3, 4X, • ADJ STD E 
 1RR OF EST = • ,FP.3) 
 
100 
 
 475 FORMAT < •- • , 2X , • L I NEAR REGRESSION EQUATION COEFFICIENTS') 
 3012 FORMAT (»0 VAR MO. NAME'23X'REG WT BTA WT WT SIG -RAT 
 
 110' ) 
 3053 FORMAT (• • ,2X , 14 ,3X ,24A1 ,F12.5, 3F1 1 .5 ) 
 
 469 FORMAT CO'///) 
 3091 FORMAT (»-• ,2X , 'RESULTS ARE IN RAW SCORES') 
 3086 FORMAT ('0',2X,'END OF PROBLEM' //« 2 • ) 
 
 430 FORMAT (*-',2X,'END OF REGRESSION PROGRAM' /• 1 • ) 
 9003 FORMAT (5016. R) 
 
 5000 FORMAT (//• DURBIN - WATSON STATISTIC: ' F7 .3, 20X • VON NEUMANN RATIO 
 1: «F7.3//) 
 
 5001 FORMAT ( • • 31)20.9) 
 
 5002 FORMAT (// T14, • ACTUAL ', T28 ,' EST IMATE '♦ T52 , 'RES I DUAL •// ) 
 C 
 
 C INITIALIZE PROGRAM PARAMETERS 
 C 
 
 10 DO 14 1=1,20 
 
 AID( I )=0.0 
 
 DO 14 J=l,20 
 14 C( I ,J)=0.0 
 
 REWIND 3 
 C 
 C READ TITLE 
 
 READ (5,1056) ( T I TL t ( I ) , 1 = 1 , 18 ) 
 
 WRITE (6,1002) (TI ILE ( K) ,K=1 , 18 ) 
 C READ NUMBER OF VARIABLES, NVAR = 10 MAX 
 16 READ (5,1000) N I NO, NVAR, ICHG 
 
 NIN0=NIND+1 
 
 ICI)CT = 
 
 NVARM=NVAR+l 
 
 M=NVARM 
 
 IF (NVARM .LT. 1) GO TO 850 
 20 DO 24 1=2, NVARM 
 C READ IN NAMES OF VARIABLES IN CARO COLS 1-24 
 
 K= I- 1 
 
 READ (5,510) (ANAM( J, I ) ,J = 1,24) 
 24 WRITE (6,511) K , ( ANAM ( J , I ) , J= 1 , 24) 
 C READ IN DATA FORMAT 
 
 READ (5,1001) (FMTIN( I), 1=1,18) 
 
 READ (5,1001) (FMT0OT( I ),I=1,1R) 
 C WRITE TITLE OF OUTPUT DATA 
 C WRITE FORMAT USED TO READ IN INPUT DATA 
 
 WRITE (6,1057) ( FMT I N ( I ) , I = 1 , 1 8 ) 
 
 WRITE (6,105H) ( FMTOUT ( I ) , I = 1 , 1 8 ) 
 
 IF ( ICHG .LE. 0) GO TO 38 
 
 KCHG=0 
 
 NTRANS=40 
 
 DO 35 L=1,NTRANS 
 C RFAO IN VARIABLE TRANSFORMATIONS, MAX # ■ 10 
 
 30 READ (5,8001,tND=35) ( ACHG ( L , J ) , J= 1 ,4 ) 
 C WRITE OOT TRANSFORMATIONS 
 
 WRITE (6,H002) L , ( ACHG ( L , J ) , J= I ,4 ) 
 
 KCHG=KCHG+1 
 
 GO TO 30 
 35 REWIND 5 
 C WRITE NAMES OF INPUT DATA VARIABLES 
 38 WRITE (6,1002) ( T I TL E < I ) , I =1 , 18 ) 
 
101 
 
 40 
 
 55 
 
 60 
 
 12 
 
 74 
 
 7ft 
 
 79 
 
 80 
 M 
 
 82 
 
 HA 
 
 WRITE 4 6.615) 
 
 READ IN NINO COLS OF DATA PER DATA CARD FORMAT R6F STMT 1001 
 
 REWIND 5 
 
 READ (5,FMTIN,EN0=60) ( A ( I ) , I -2 ,N INO ) 
 
 WRITE LIST OF INDEPENDENT VARIABLE INPUT DATA 
 
 WRITE (6,FMT0UT) ( A ( I ) , I «2 ,N IND ) 
 
 WRITE (3,9003) ( A ( I ) , I -2 ,NVARM ) 
 
 A( n-i.o 
 
 ICDCT=ICDCT+1 
 
 IF ( ICHG .GT. 0) CALL CHANGG 
 
 DO 55 I=1,NVARM 
 
 DO 55 J=I,NVARM 
 
 C( I , J)=C( I ,J)+A( I )*A( J) 
 
 GO TO 40 
 
 S I ZF = C (1.1 ) 
 
 END FILE 3 
 
 REWIND 1 
 
 V( 1 )=DSORT(C( 1,1 ) ) 
 
 DO 74 I=2,NVARM 
 
 IF (C( I, I ) .LE. 0) GO TO 72 
 
 v(i) = <sizE*cn,i)-c(i,i)*C(i r in/(SizE*sizE) 
 
 IF ( V( I ) .LE. 0) GO TO 72 
 
 V( I )=USQR1 ( V( I ) )*VI 1 ) 
 
 GO TO 74 
 
 V( I ) = 1.0*V( 1 ) 
 
 CONTINUE 
 
 SSS=OSORT(SIZE) 
 
 SSS=1.0/SSS 
 
 WRITE DATA STATISTICS HEADING 
 
 WRITE (6,1066) 
 
 DO 76 I=2,NVARM 
 
 STDV=V( I )*SSS 
 
 SPST=V( I )*SSS 
 
 SPST=SPST*SPST 
 
 CU=(SIZE*SIZE)/( (SIZE-1.0)*(SIZE-1.0)) 
 
 SPST=SPST*CD 
 
 SPST=DSORT(SPST) 
 
 AHEAN=C( 1, I )/SlZE 
 
 K= I -1 
 
 WRITE DATA STATISTICS 
 
 HKITE (6,1067) K, (ANAM( J, I ) ,J=1,24) , AMEAN, STDV , SPST 
 
 CUNT INUE 
 
 DO 79 I=2,NVARM 
 
 AI ( I )=0.0 
 
 IC0R=1 
 
 GO TO 81 
 
 READ MODEL SELECTION CARDS 
 
 READ (5,1006) ( A I ( I ) , I = 2 ,NVARM ) 
 
 A I ( 1 > = 1 .0 
 
 IF (AI(2)-3.0) 82,800,850 
 
 AKNT=0.0 
 
 00 84 I=1,NVARM 
 
 IF (A( I ) .NE. 
 
 AKNT=AKNT+1.0 
 
 CONTINUE 
 
 IF (SIZE .GT. 
 
 WRITE (6,4RR) 
 
 1 .0) GO TO 84 
 
 AKNT) GO TO 
 SI?E,AKNT 
 
 86 
 
102 
 
 GO TO 80 
 fl6 DO 92 1=1,NVARM 
 
 IF (AIO( I ) .GT. 0) GO TO 90 
 
 CS( I)=1.0/V< I ) 
 
 GO TO 92 
 90 CS( I)«V( I ) 
 92 CONTINUE 
 
 DO 94 I«1,NVARM 
 
 DO 94 J=1,NVARM 
 94 C( I ,J)=C( I,J)*CS< I)*CS< J) 
 
 DO 180 N=1,M 
 
 IF IAI (N) .EO. 1 ) GO TO 96 
 
 SDUT=0.0 
 
 GO TO 98 
 96 S0UT=1.0 
 98 IF (SOUT .EO. AID(N)) GO TO 180 
 
 IF <C(N,N) ,LE. 0) GO TO 170 
 
 IF (C(N,N) ,LE. TOL) GO TO 170 
 
 101 C(N,N)=1.0/C(N,N) 
 
 IF (SOUT .GT. 0) GO TO 106 
 
 102 DO 105 1=1, M 
 
 IF (I-N) 103,105,104 
 
 103 C( I,N)=(1.0-2.0*AID( I ) )*C« I,N) 
 GO TO 105 
 
 104 C(N, I )=(1.0-2.0*AID( I ) )*C(N,I ) 
 
 105 CONTINUE 
 
 106 DO in 1 = 1, M 
 DC) 111 J=I ,M 
 
 SIGN=1.0-2.0*I)ABS(S0UT-AI0( I )*AID( J) ) 
 IF (I-N; 107,111,110 
 
 107 IF (J-N) 108,111,109 
 
 108 C( I ,J)=C( 1,J)+SIGN*C( I ,N)*C( J,N)*C(N,N) 
 GO TO 111 
 
 109 C( I ,J)=C( I ,J)+SIGN*C( I ,N)*C(N,J)*C(N,N) 
 GO TO 111 
 
 110 C( I ,J)=C( I ,J)+SIGN*C(N,I )*C<N,J)*C(N,N) 
 
 111 CONTINUE 
 
 IF (SOUT .Lfc. 0) GO TO 116 
 
 112 DO 115 I=1,M 
 SIGN=1.0-2.0»AID( I ) 
 IF ( I-N) 113, 115,114 
 
 113 C( I ,N)=SIGN*C( I ,N)*C(N,N) 
 GO TO 115 
 
 114 C(N.I )=SIGN*C(N,I )*C(N,N) 
 
 115 CONTINUE 
 GO TO 169 
 
 116 DO 168 I=1,M 
 
 IF (I-N) 161,168,162 
 
 161 C( I ,N)=C( I ,N)*C(N,N) 
 GO TO 16H 
 
 162 C(N, I )=C(N, I )*C(N,N) 
 
 168 CONTINUE 
 
 169 AID(N)=SOUT 
 GO TO 180 
 
 170 K=N-1 
 
 WRITE (6,2000) K,C,C(N,N) 
 
103 
 
 AI (Nl-2.0 
 
 GO TO 190 
 180 CONTINUE 
 190 00 250 I-l.NVARM 
 
 IF (AIO(I)) 250,241,242 
 2*1 CS< I )»V( I ) 
 
 GO TO 250 
 2*2 CS( I )-1.0/V( I) 
 250 CONTINUE 
 
 IF ( ICOR .LE. 0) GO TO 444 
 C WRITE • INTERCORRELATION MATRIX' 
 
 WRITE (6,446) 
 
 MKB«M-1 
 C 
 
 WRITE (6,459) < IJ,I J»1,MKB) 
 
 00 447 I I = 1 , M 
 
 DO 447 JJ=I I ,M 
 447 C( JJ,I I )=C( II, JJ) 
 
 00 450 I 1=2, M 
 
 MK=I 1-1 
 C WRITE MATRIX ELEMENTS 
 
 WRITE (6,455) (ANAM(JN,II) t JN»l,24>,MK,(C<II,JJ), JJ»2 t II ) 
 450 CONTINUE 
 
 DO 458 I 1 = 1, M 
 
 DO 458 JJ = 1 ,M 
 4b 8 C( I I,JJ)=C( I I ,JJ)*CS( II )*CS( JJ) 
 
 ICOR=0 
 
 GO TO 80 
 444 DO 254 I=1,NVARM 
 
 DO 254 J=*I ,NVARM 
 ^54 C( I ,J)=C( I ,J)*CS( I )*CS( J) 
 
 AM=0.0 
 
 DO 299 I=1,NVARM 
 
 IF (AIO(I)-l.O) 299,280,299 
 280 AM=AM+1.0 
 299 CONTINUE 
 
 DO 300 I=2,NVARM 
 
 IF (AMI) .Lb. 1.0) GO TO 300 
 301 PCT=C( I , I )/(V( I >*V( I ) ) 
 STER=C( I, I )/SIZE 
 
 AST=SIZt/(SI2E-AM) 
 
 A()SSR = STER*AST 
 
 STER=DSORT(STER) 
 
 ADSSR=SORT(ADSSR) 
 
 DF=SIZE-AM 
 
 RR=1.0-PCT 
 
 R=DSORT(RR) 
 
 ADJRR=1.0-(1.0-RR)*( ( S I ZE-1 .0 ) / ( S IZE-AM ) ) 
 
 IF (ADJRR .GT. 0.0) GO TO 340 
 
 ADJRR=0.0 
 
 ADJR=0,0 
 
 GO TO 344 
 340 ADJR=OSORT( ADJRR ) 
 344 K= I - 1 
 C WRITE REGRESSION EOUATION STATISTICS 
 
 WRITE (6,1002) (TITLE(MK),MK»1,18) 
 
 WRITE (6,3009) K , ( ANAM ( MK , I ) ,MK»1 , 24 ) 
 
10 k 
 
 WRITE (6,490) SIZE, OF 
 WRITE (6,3010) RR,R,STER 
 WRITE (6,472} ADJRR , ADJR , ADSSR 
 WRITE (6,475) 
 ; WRITE TITLES FOR REGRESSION EQUATION COEFFICIENT TABLE 
 WRITE (6,3012) 
 DO 320 J*1,NVARM 
 IF (AID(J) .NE. 1.0) GO TO 320 
 IF (I~J> 324,320,325 
 
 324 BETA»C( I ,J> 
 GO TO 326 
 
 325 BETA=C( J, I ) 
 
 326 BVAR=C( I, I) *C U , J ) / ( S I ZE-AM ) 
 BSTD=DSORT(BVAR) 
 TRAT=BETA/BSTD 
 
 K = J-1 
 
 BB( J )=BETA 
 BVAR=BETA*V( J)/V< I ) 
 ; WRITE REGRESSION EQUATION COEFFICIENTS 
 
 WRITE (6,3053) K , ( ANAM ( NJ , J ) ,NJ«1 , 24 ) ,BETA , BVAR, BSTD, TR AT 
 320 CONTINUE 
 SE=0.0 
 DIFS=0.0 
 KZ = 2 
 PR6=0.0 
 IN I = 1 
 
 WRITE (6,b002) 
 4002 READ ( 3 ,9003 , END=4004 ) ( A ♦ I A ) , I A = 2 ,NVARM ) 
 EST=0.0 
 
 DO 4060 J=2,NVARM 
 IF (AIO(J)-l.O) 4060,4059,4060 
 
 4059 EST = EST + BB( J)*A(.J) 
 
 4060 CONTINUE 
 EST=EST+Bft( 1 ) 
 A ( 1 ) =: fc S T 
 RESI0=A( I )-EST 
 SE=SE+RESID*RESID 
 
 IF- (IN1-1) 4071,4071,4070 
 
 4070 DIFD=RESIO-PRE 
 DIFS=DIFS+DIFD*DIFD 
 
 4071 PRE=RESIO 
 
 WRITE (6,50011 A( I ) ,EST,RESIO 
 I N I = I N I + 1 
 GO TO 400 2 
 4004 REWIND 3 
 
 D'.IRR = DIFS/SE 
 V0N=SIZE*UURB/(SIZE-1.01 
 WRITE (6,5000) OURB,VON 
 
 300 
 
 CONT INUE 
 
 
 WRITE (6,3091) 
 
 
 GO TO 80 
 
 BOO 
 
 WRITE (6,3096) 
 
 
 IF (NVARM .LE. 
 
 820 
 
 GO TO 10 
 
 H50 
 
 WRITE (6,430) 
 
 0) GO TO 850 
 
105 
 
 STOP 
 
 END 
 
 SUBROUTINE CHANGG 
 
 COMMON A, ACHG, ICOCT t KCHG 
 
 DOUBLE PRECISION A ( 40 ) , ACHG140,M ,DLD, ICOCT 
 
 OC 100 I-WKCHG 
 
 KBAB-ACHG( 1,1) 
 
 ND-IDINT(ACHG( I ,2 ) ) 
 
 MD«IOINT(ACHG( 1,3} ) 
 
 LO»IDINT( ACHG1 I ,4) ) 
 
 MD-MD+1 
 
 ND*N0+1 
 
 LD-LD+1 
 
 DLO-ACHGI 1 ,4) 
 
 GO TO < I, 2, 3, 4, 5, 6, 7, 8, 9, 10,11, 12), KBAB 
 
 1 A(MD) =A(ND) **DLD 
 GO TO 100 
 
 2 AIMD)*1 ,0/( A(ND)**DLD) 
 GO TO 100 
 
 3 A(MD>=A(NO)*A(LD) 
 GO TO 100 
 
 <♦ A(MD)*A(ND)/A(LD) 
 GO TO 100 
 
 5 A(MO)*A(NO)-A(LO) 
 GO TO 100 
 
 6 A(MD)=DSORT( A(ND} ) 
 GO TO 100 
 
 7 A(MD)=DLOG< A(ND) > 
 GO TO 100 
 
 R A(MO)=DbXP( A(NO) ) 
 
 GO TO 100 
 9 A(MQ)=A(ND)+A(LD) 
 
 GO TO 100 
 
 10 A(MD)=ICOCT 
 GO TO 100 
 
 11 MMD)=A(ND)+DID 
 GO TO 100 
 
 12 A(MD)=A(ND)*DLD 
 100 CONTINUE 
 
 RETURN 
 ENO 
 
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 i 
 
 « 
 
 rfl 
 
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