LIBRARY OF THE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAICN 510.84 no.Z79-J2S w •H T3 u rn CD -3" -P J" £ .-1 -H U ft 21+01 magnetic tapes lUl+2 card read/ punch 1055 japer tape punch 105m- paper tape reader — 18 consc typewr — . - — — — — , — -p O 0) ct3 w -p c a •H c o o aJ U a> 3) •H ft o -p o ] cj ■H vD on ■H P rH o P W 00 — CO qj CM CM H c a j O bl Ph 1 ^t cd cd o ■ ov CM CM 2 EH O LT\ I o o P VD en CO £ cd Xl o cd P CD cd O 6S. o cd P a? cd Ph Ph Ph LT\ O VD fO O f\l a S- CD t- 0J a cd x o cd p a; T3 60 p cri o h w |s TJ\ ■P • P. W CO OOP CJ S 'H a; co jo rH 3 W o vD vD O CM LT\ t~- o o P VD on \^ H CO qj < 1 cu cd O ^i i> — — xi H W H o on -h p CM O O cd P cd R I p P CU O rH O W rH OJ M O I CU p rH CJ P o o a p o rH Ph O p Pi 3 P CO P rH CD w QJ -P rH P 0J £ a; CO rH H ti •H O a bo co H a-; qj a cri G Ph O G o o rH K QJ cd QJ vD -P p T3 rH « gj G 00 Q H rH CM t— CO QJ P CO o r-\ V g w oo CM CO UA .00 m rn -LTN — -LT\ ON" 00 CM LA r-l IP, -3- oo ' CM CM m On H ' on p ■H U CD VO P CM Ph OO Cd rH T3 < cd p cd Q SO LA _ON On CM CM on rn LTN -CM - VD CM VD on vD LTN t— LTN CM VD- CM rn CO. CM on -H- vD CO ' CM on 0) p -p < HO. R MP QJg w « U •H G O P 5h O p cd O P QJ G rH W " P Pi rH U OJ o o P G Cm H QJ -P P rH > 03 bO fk bfl hj o h a « a> p P cS ■H ? P bD ftH •H C! O H > Table 2.1. Component Identification 1801-2C processor-controller Memory: 2usec-, l6K words, l6 bits/word Standard features: 12 External interrupt levels 3 Data channels 3 Index registers 3 Internal timers Operator's console 105^-2 paper tape reader 1055-2 paper tape punch 1232' analog-digital converter, model 2 1233 analog input data channel 123*+ analog input data channel adapter 2 lkk2-6 card reader/punch, 92*+7 priority #7 lM+3-1 printer, 9256 priority #6 l8l6 console typewriter 1826 data adapter unit 1828 enclosure 1851 multiplexor control 2185 comparator 2310-A1 disk, single module, single platter, 9l6l priority #1 2*+01 magnetic tape drives, 9232 priority #2 2803 magnetic tape control unit (shared with 3^0-75 via 29II switch) 28l6 switching unit for magnetic tape drives -5- 2911 switching unit for magnetic tape control 3222 four extra data channels 3262 digital input adapter 3286 digital input, voltage sense (one group of l6 hits) 3287 digital input, high speed (one group of l6 bits) 3290 digital channel output adapter, 9275 priority #5 3291 digital channel input adapter, 928U priority $+ 3295 digital output adapter 3296 digital output control 3593 connector element (+5v) 3612 electronic contact operate (l6 hits) kk30 reader-punch controller kk-31 printer adapter UU32 printer controller 5253 group of l6 points on analog multiplexor 5258 multiplexor control 5569 printer controller 5710 process interrupt adapter 57l6 process interrupt, voltage (one group of 16 bits) 6l21 take-up reel for paper tape punch 6l25 register output, high speed 7720 36O channel adapter, 97 1+3 priority #3 7926 paper tape adapter 9665 internal timer, 0.125 msec. 9681 internal timer, 1+.0 msec. 9683 internal timer, 8.0 msec. RPQ, C08037 System/360-type 1800 data channel -6- Table 2.2. Interrupt and Addressing Summary of Input/Output Devices Device Interrupt Level ILSW Bit Data Channel Area Code Process Interrupt 00 00 11 Interval Timers 00 01 2310 Disk 01 00 1 Ok 36O Ch. to Ch. 02 00 3 13 Magnetic Tape Drives 03 00 2 18 Typewriter 01+ 00 01 Comparator 0^ 01 5 Digital Input 05 00 . 6 11 Digital-Analog Output 05 01 7 12 Analog-Digital Input 05 02 k 10 lM+3 Printer 06 00 8 06 IO5U/IO55 Paper tape read- punch 06 01 03 1I+I4.2 read-punch 07 00 9 02 Console Interrupt 08 00 ■7- The system includes a single analog-to-digital converter which can receive signals from one or more multiplexor input points, under control of the 1800 program. A sample -and -hold amplifier permits conversion rates up to 20,000 conversions per second. The system can also sense binary conditions, such as the open or closed state of a switch, either under the initiative of the 1800 program (using the contact sense feature) or by interrupt of the program (using the process interrupt feature). Analog output is accomplished through a fast digital output register, which can be used to drive various output devices. It is expected that a DCS digital-to-analog converter, presently connected to the ILLIAC II, will be connected to the 1800 through this register. The system also has l6 electronic contact operate output points, which can be used to cause any desired program-controlled operation such as turn -on -tape -drive, etc. The access to the System/360-50 is a channel-to-channel ad- apter which allows information to be exchanged between the 1800 and the 36O-5O in burst mode at selector channel speeds. The access to tape units is through an electro-mechanical switch which allows the l800 to use the 9-track phase-encoded 180 KHz magnetic tape drives that are a part of the System/360-50/75. 2.2. l800 Processor The 1800 is a general purpose digital computer with interrupt and channel capability. The central processing unit is an 1801 model 2C processor -controller, having l6K words of 2 usee core storage. Each core word has l6 data bits, 1 parity bit, and 1 storage protect bit. The processor is generally applicable to problems in the area of process control or high speed analog data acquisition. -8- 2.3* Data Processing Input/Citput 2.3-1- 105^ Paper Tape Reader (model 2 ) This tape reader reads one -inch eight -track tape at a maximum rate of lU.8 characters/second. Data is read into core storage as an image of the holes in the tape, with each punched character being read into one addressed core location. 2.3.2. 1055 Paper Tape Punch (model 2) This tape punch punches one-inch eight-track paper tape at a maximum rate of lU.8 characters/second. Data characters are punched as an image of the data in core storage. 2.3.3. lM+2 Card Read/Punch (model 6) This read/punch operates on a data channel and provides serial reading and punching of cards. The model 6 reads cards at 300 cards/minute and punches cards at 80 columns/second. 2.3- 1 +. 1^3 Printer (model l) This printer operates on a data channel at a speed of 150 lines/minute, on a 120 character line with a 52 character set: 10 numeric, 26 alphabetic, and ^-/iWh, • $ @ ( )*' 2.3-5- I8l6 Keyboard-Printer This console typewriter provides printed output at the rate of lU.8 characters/second and a keyboard for data entry into the processor. 2.3-6. 2310 Disk Drive (model Al) This is a single platter moveable head disk consisting of one drive mechanism. The 2315 cartridge consists of a single platter of 203 cylinders of two tracks each. Each track consist of h sectors of 321 words each. One word is stored on disk as l6 data bits plus 1 parity, 1 storage protect, and 2 spacing bits. The maximum storage capacity in a single access is 2568 words. 2. 3«T« 2401 Magnetic Tape Drives (model 6) These drives are phase-encoded 180,000 bytes/second tape drives handling one-half inch tape of the regular 10-5 inch reel, 2400 foot length variety. The capacity of a 2400 foot reel of tape written on this drive is : 20 byte block size -42, 847 blocks or 856,91+0 bytes, 100 byte block size-39,846 blocks or 3,984,600 bytes, 500 byte block size-29,510 blocks or 14,755,000 bytes, 1000 bytes block size-22,284 blocks or 22,284,000 bytes, 2000 byte block size-l4,959 blocks or 29,918,000 bytes. One 1800 word (l6 data bits + 1 parity bit) is written on tape as two consecutive bytes (8 data bits + 1 parity bit each). There are six tape drives shared by the 36O-5O, the 360-75; and the 1800. Each computer is connected to the tape drives via its data channel and a 2803 control unit. The three 2803 control units are connected through a 28l6 switching unit to the tape drives in such a way that all three computers can access all six tape drives. The switching function of the 2816 is done automatically, although the operator can manually disconnect any given tape drive from any given control unit. The 2803 control unit used by the 1800 is also connected, via a 29H switching unit, to a second channel of the 360-75- The 29H is a manual switch only. This arrangement allows the 360-75 an alternate path to the tape drives during periods when the 1800 is not using them. 2.3-8. 7720 18 00- System/ 360 Channel-to-Channel Adapter This is a direct core-to-core connection via a data channel on each of the two computers. Thus, the 1800 and the 36O-5O each look like an input/output device to the other. This device is similar to the channel-to-channel adapter which is used to connect the 36O-5O to the 36O-75. ■10- 2.4. Process (Analog, Digital, and Control) Input/Output 2.4.1. Process Interrupt, Voltage Process interrupt is factory wired to one of 24 priority levels of processor interrupt. When an interrupt occurrs, the processor program will branch to an interrupt routine associated with that level. If a higher level interrupt routine is in progress, the new condition waits until the higher one is completed. Each pair of customer terminals is factory wired to a partic- ular bit position of a l6-bit Process Interrupt Status Word (PISW). Each PISW is interrogated as a l6-bit word for individual terminal identification by a program. Sense specifications: 1. Contact Grouping: l6 voltage input group. ■ 2. Transmission Path: Line lengths and resistance may be of any magnitude as long as the dc voltage levels appear within tolerance at the customer terminals. 3- Interrupt Condition: An interrupt will occurr by a voltage level changing from "0" to "l". Interrupt is initiated on the leading edge of the voltage rise. Binary "1" = -1.0 vdc min. to +30 vdc max. Binary "0" = -6.0 vdc min. to -30 vdc max. Indeterminate = -6.0 vdc to -1.0 vdc h. Input Impedance: 3 -7k ohms (approx. ) 5- Sensing delay: Filter and line capacitance introduce a delay before the system can reliably detect a change in voltage level. The following maximum delay values are for line lengths up to 250 feet. The capacitance of longer line lengths will increase the delays. Voltage level input to reliable detection =2.5 msec max. Max. "1" voltage to reliable "0" = 5 msec max. -11- 6. Safety protection: The equipment will tolerate accidental connection to voltage as high as 120 v ac without damage other than the possible opening of the fuse in the dc ground line. 7. Electrical noise protection: The voltage source should be referenced only to the iBOO system ground through the common or dc return lead of the signal wiring. If desired, a single power supply may be used for more than one input when located in the same immediate area. 8. Terminal description: A fanning strip with screw -driver con- nections is used for customer wires. 9. Circuit description: See Figure 2-3, process interrupt, voltage sense schematic. 10. Wiring practice: Twisted pair wiring is recommended for each individual voltage source. Two wire termination is provided for each source. Terminal sizes are #6 on standard barrier strips. No tiedown for shielding is provided. It is recommended that the customer provide reasonable physical separation from output and analog system wiring and from any ac power lines enroute. 2.U.2. Contact Sense, Voltage Digital input points may be used either collectively as a l6-bit register input or individually for the sensing of separate process conditions. The input data is read by the processor-controller on command as binary "1" or "0" bits in a l6-bit word. Input data is sensed by a voltage change. The specifications are the same as process interrupt (see section 2.^.1) with the following exception: 2. Transmission path: limited to 100 ft. -12- Customer wires Bit 16 Twisted Pairs Bit 15 TB-B -O- Fault Protection Board 7-5K vW 7.5K uvo z^ I.B.M. Transistorized Circuits Figure 2.3- Process Interrupt, Voltage Sense Schematic 2.k.3. Electronic Contact Operate (ECO) This feature provides program selection of one or more output points (within a group of 16) , permitting the closing of customer circuits for a period of time controlled by the program. The specifi- cations governing the customer's input voltage and load characteristics are: 1. Ground : Common or dc return is connected to the 1800 system ground. To avoid ground loops or injection of noise into the system the customer's voltage source should be floating or isolated from ground at the voltage source. 2. Customer Power Supplies : Each power supply furnishes power to four (or multiples of four) digital output points. 3. Load Current (switched): Must not exceed 0.^5 amp. -13- k. Load Characteristics : A wide variety of R, L, and C load characteristics can be accommodated within the above voltage and current specifications provided the peak instantaneous voltage at the terminals does not exceed: +65 v dc maximum, +1 v dc minimum 5. Output Impedance : Diode - "l" (on) = 5-7 megohms "0" (off) =8.0 ohms Switch - "0" (off) = 1.25 megohms "l" (on) = variable 6. Transfer Time (resistive load) : Less than 10 usee for turn on. Less than 10 usee for turn off. 7- Duration of Closure : Duration selected by program. 8. Synchronization : Generation of program action may be initiate by an external "sync" signal. 9* Terminal Description : ECO is terminated in the customer access area at the rear of the 1801 processor-controller. 10. Circuit Description : See Figure 2.k. 11. Wiring Practice : Use twisted pair wiring to reduce electrical interference. The electronic contact operate wiring should not be run in the same cable with analog or digital inputs. 2.k.k. Register Output (R0) Register Output is a l6-bit binary register which can transmit its contents over l6 pairs of conductors to a customer provided device. Transfer of this data is under program control and can be initiated by the customer device (either an external sync signal, or process interm] )• -Ik- 'I MM! , 3 Lnnno t V r * 3 U ~ 5 -£ * "3 ~ 3 1»T) O 3 n T?< 9 E r £ o >- -c 2." _ *- 4) ♦= 1) ' ut 3 o Q. 3 °- 9- C/-1 □ 3 . * «£ 5 - 41 is c = o ™ ° — o I 1 ( 1 1 I I I ' I * I I I I I I i i- <-Ki- o-KJ- t~^ r T Ho-*- I ^VM\- U- -Jv CM u_ <*, T .1 c 1 -15- The voltage and current specifications are : 1. Rate : 500*000 (l6 bit) words per second (maximum) 2. Output Voltage : Binary "1" = -3 v nominal Binary "0" = v nominal 3- Output Current : 32 ma maximum (including termination and customer load). k. Load Characteristic : Termination to customer +3 v and load must present 100 ohms characteristic to the transmission line. Customer +3 v must be between +2.88 and +3-^ v referenced to 1800 system dc ground. 5. Terminal Description : Register outputs terminate in a customer access area at the rear of the 1801 processor-controller. 6. Circuit Description : See Figure 2-5- 7. Line Length : 100 feet (maximum). 8. Line Capacitance : 18 picofarads/foot (maximum). 9. Wiring Practice : Use twisted pair conductors for wiring to the terminals in order to minimize pickup of electrical noise. This cable should not be run in the same cable with analog or digital inputs. ■16- Customer ^ IBM Customer Devices 1800 System DC Ground 550 : + 3v 1 350 : I -O Input Figure 2.5. Register Output 2-^+. 5 • Analog Input The Analog Input units and features provide modular packaged equipment used to convert voltage or current signals to digital values. The modules used to accomplish the conversions include analog-to-digital converters, multiplexors, amplifiers, and other signal conditioning equipment. A physical phenomenon is first sensed and converted to an analog electrical signal by sensors or transducers, such as thermocouples or strain gages. Electrical signals from sensors or transducers may be in the millivolt, volt, or milliampere range. Low voltage signals (less than 1 volt) must be amplified to a level acceptable for conversion to digital form. All customer lines from transducers are terminated at the control system on screw-down terminals. The signals are also conditioned at the terminals, including the filtering of extraneous signals, known as noise. Conversion of analog signals from a voltage level to digital information is accomplished by an Analog-to-Digital Converter (ADC). Such converters, however, are complex enough so that if multiple sources of analog signals are to be converted, they share the use of one ADC. The switching is accomplished by a multiplexor. The data path from sensor or transducer to processor is shown by Figure 2.6. The units and features that accomplish the analog input function are briefly introduced below, followed by more detailed descriptions. As shown in Figure 2.6, customer input signals are routed through termination, signal conditioning elements, multiplexor switches, an amplifier (low level signals only), and into the analog-to-digital converter (ADC). The output of the ADC is presented to the processor- controller (PC) via the data channel from the ADC output register. -18- High -Level Single -Ended Inputs 1828 | 1851-11 Standard Terminal* Signal Conditioning Flem»nts Solid-State Multiplexer (Max. 256 Points) 1 Solid-State Block Switch External Sync — 1801 ~l ^ | Al Basic ' ADC ' w ' Out 4 wn u Bus Earn ma ■JWfg>M NOTE 1 --© Q> Solid Sto e Multiplexer Switchej (16 per block jwitch) \f~\- State Multiplexer- Block Switch (Cne per 16 inputs, up to 16 per ADC Totol MPX/S Piuj Totol MPX/R Amplifier Switchej Must Not Be More Thon 16.) 1* 30. A-30v > - Anolog - to - Digitol. Converter (ADC) Sample and Hold Amplifier (For Mod 2 ADC ) tWA- -WW Hh To 1 800 System Anolog Ground NOTES: 1 . Multiplexer matching card (Connector Element) Figure 2.7. Solid State Multiplexor Inputs -22- 2.k.5.k. Analog Input Calibration The analog input calibration facility is housed in the 1828 Enclosure. Power is supplied to the calibration facility through the power switch on the front left side of the 1828. The calibration facility provides the following dc reference voltages for calibration of AI features when the calibration facility is connected directly to an appropriate 1851 input terminal pair: +5 volts 100 mv -5 volts 50 mv 500 mv 20 mv 200 mv 10 mv Exact voltages are measured at the factory and are recorded to five significant digits on the reference unit. Note that connections for +5 volt and -5 volt ranges are different. A special high-level input point is selected by multiplexor address 13E8-,r (which is outside the normal range of Mpx/S addresses) for ADC calibration only. The multiplexor calibration point can be addressed at any time by the customer program or diagnostic program for an operational check of the ADC. The reference voltage to be addressed is selected by changing connections on a terminal strip. An IBM Customer Engineer changes the connections on the terminal strip. 2. 1 +.5-5. Sample -and -Hold Amplifier The Sample -and -Hold Amplifier is an integral part of the Model 2 ADC. It is a single -ended amplifier capable of providing a short aperture time in the sampling of high-level analog signals and of providing a high accuracy hold function. The amplifier has an input impedance of 100K ohms. The program must consider the reversed polarities obtained from sample -and -hold input points. -23- 2.U.5-6. External Sync The operation of the ADC can be controlled by an external timing (sync) pulse. When the Solid-State Multiplexor is used, a "ready" condition is transmitted before the solid state switches are actuated. The external device provides a sync start pulse which allows the solid-state switches in the multiplexor to be actuated and then conversion of the selected signal begins. An "8" bit in the modifier of a IOCC, either "Write" or "Initialize Read/' sets up the external sync mode. The absence of an "8" bit in the modifier of either a "Write" or "Initialize Read" command terminates the external sync mode. 2.h-3'l' Comparator The Comparator performs selective checking on the digital values converted by the ADC. A range type check is made to confirm that the converted values are within specified limits. The limits are obtained from the Multiplexor Address Table (one PC cycle delay allows both limits to be acquired) whenever a check is required. The PC is informed of an out-of limits condition by interrupt. The two Analog Input Data channel adapter features are a prerequisite to this feature. In order that a range comparision can be made, both a high limit and a low limit must be set. In converting many analog input source signals, it may be necessary to monitor each signal to assure that the signal remains within specified bounds. Normally, a number of these signals are redundant and other signals need only be checked occasionally. To allow for flexibility of checking input signals, a separate control (in Multiplexor Address word) is added to instruct the Comparator to perform checking when required. It should be noted that limit words need not remain static. For example, when a particular high limit is exceeded, then a single change will permit recognition of the return of the signal within the -2k- former limits. The high limit is substituted for the low limit and the maximum value is set for the high limit. If the interval timer is read after each limit is exceeded, then the time interval that the signal was out -of -limits is known. _p^_ 3. System Software 3.1. Operating System Requirements The control program for the 1800 computer must meet several severe requirements. For example, consider an 1800 job which involves high-speed analog to digital conversion. Such a program will rely heavily on large input/output buffers, immediate response to interrupts, etc. In short, data will be entering and leaving the processor-controller (PC) at such a rate as to allow essentially no time for system overhead. Historically, such programs were written for stand-alone execution: the program was responsible for loading itself into core and performing all of its functions, including input/output, interrupt handling, etc This method is obviously undesirable even on a stand-alone computer; the fact that the 1800 will be controlled by the System/360 makes such a configuration impossible. The solution to these problems is an operating system which is passive in nature. For example, during execution of an 1800 job, the operating system can gain control from the problem program in the following ways only: 1) Detection of an abnormal condition (such as a protect error, etc. ); 2) Operator intervention (via the console typewriter); 3) The job itself; k) The System/360 computer. If we assume that (2) is not an arbitrary action, then {k) becomes the only interrupt which could disrupt a job executing in a proper manner. We eliminate this problem by requiring that the System/360 communicate with the 1800 by request of the 1800 only, unless the System/ 360 has detected an abnormal condition which the 1800 does not have the ability to recognize. This called an "1800 master-360 slave" environment. -26- Other, more specific requirements and plans for attacking them are : 1) Available core storage . In order to take up the smallest possible amount of core, the resident portion of the operating system will include only those programs essential to the execution of all jobs. These programs will include interrupt handlers, System/360 communication routines, console supervisor, storage dump and program loader routines, input/output supervisor, etc. All other programs will be in the form of subroutines dynamically loaded with the user's program as requested. Such subroutines will consist of device -dependent I/O error recovery routines, data conversion programs, etc. 2) Interrupt processing . Some 1800 jobs will need to process their own interrupts. The resident operating system will allow user interrupt exits to a limited extent. 3) Operator communication . Operator /user control of a program will be available through the l8l6 typewriter keyboard. The operating system will contain an extensive set of routines which will allow operator /program conversation in a flexible manner. h) System/360 Model 75 communication . There will be two communication paths between the 1800 and the 360-75* The first of these is the pool of System/360 tape drives which will be attached to both systems. Secondly, two-way communication will be provided through the 36O-5O. The l800-System/360-50 channel-to-channel adapter will appear to be a series of pseudo-tape units to the 1800 program. Data output to one of these pseudo-units will be read in by the 36O-5O and stored on a direct-access device. The same concept applies to the 50-75 connection; therefore, a subsequent job on the 360-75 may "read" the pseudo-tape, in which case the 36O-5O will extract the data from the direct-access device and send it to the 360-75- -27- 5) SYSIN/SYSOUT facilities will be handled in the same manner as (k). When a user's job is read in by the 3^0-50, a series of pseudo-tapes is created on 360-50 disk storage for that job. One of these pseudo-tapes (the SYSIN tape) is then loaded with the card images which make up the job. The 1800 (or the 360-75) will process the job by issuing read requests to the 36O-5O for data from the SYSIN file and write requests for data to the SYSOUT file. When execution of a job is completed, the 36O-5O dumps the contents of the SYSOUT and SYSPUNCH files to a printer and punch, respectively. The other pseudo-tape files (there are sixteen in all) may be used for 1800-360-75 communication, scratch, etc. See Figure 3«1- 3»2. Operating System Components 1) Input /Output Supervisor (IOSUP) . The function of this program is to schedule system or user requests for I/O to devices other than the console typewriter. Logic consists of verifying the availability of the I/O device, initiating the I/O, and, if necessary, recovering from an initial failure such as device out-of -ready status. Once the I/O operation is initiated, IOSUP returns control to the calling program (in most cases a system I/O subroutine which was invoked directly by the user program). Input to the I/O supervisor consists of a device address, I/O control command to be executed, and an event control word (ECW 2) Console I/O Supervisor (CNSUP) . CNSUP controls all input from and output to the l8l6 typewriter console. Messages input by the operator are converted to EBCDIC and passed to CSERV for appropriate action. Output of program-generated messages to the operator is initiated by CNSUP. 3) Console service program (CSERV) . Operator messages input to CNSUP are routed here for action. CSERV may take such action as canceling a job, passing a response on to a user program, etc -28- w o ft a ■p o CD w ft '«».^' - — ■ r — : * — 1 ffi iH fl O F-i o H s O A' r w t^-H s ft O o c/i H o TO g ft -P CD -p >H >H £ >-l >H ?H fn L/J OJ CO CO O O CO w on o •H ft CD O M IT\ CO" O W O VD'H -P W fH CD -P ! o rH a u p a CD O CI CD CD is p CD pq pi o ■H P nJ o •H O O k) Dump program (DUMP) . The DUMP program, upon request, takes panel, partial core, or full core dumps. Although normally invoked by the system upon detection of an abnormal condition, DUMP may also be called by a user program for snapshot (debugging) purposes. 5) System Loader (LOADR) . LOADR reads in user programs and subroutines, relocates them into user core, resolves external references, prints a storage map, etc Although normally called by the Job Scheduler, future plans for LCADR include dynamic reference by the user for overlay or "ping-pong" purposes. 6) Time supervisor (TIME) . Currently, the TIME supervisor provides the caller with the current time of day. Future plans call for interval timing logic. 7 ) Channel-to-Channel Adapter Supervisor (CASUP) . CASUP controls all communication from the Support Processor (System/360-50) via the channel-to-channel adapter. 8) Job scheduler (JBSCH) . This program schedules jobs for execution by interpreting control cards, allocating I/O devices, etc. JBSCH resides in the user portion of core as a transient module, i.e., it is overlaid by user programs. 9) Subroutine library . An extensive set of subroutines will reside on Support Processor direct-access storage. References to these routines by a user program (via CALL macro) -will result in their being loaded with the user program by LOADR. -30- 3.3- Interrupt Logic In keeping with the prerequisite of simplicity with flexibility, the interrupt logic is designed as follows: All processes asynchronous to the CPU (such as interval timing, I/O operations, etc) will signify their termination by interrupt. The interrupt portion of the operating system will then store the status of the completed event into the associated event control word (ECW), thus changing it from zero to non-zero. For example, when the I/O supervisor (IOSUP) initiates an oper- ation to the lU^-2 card reader, the address of a zeroed ECW will be placed into a location which can be referenced by the interrupt supervisor. Control will then return to the calling program, which may proceed with main line computing or wait for completion of the I/O operation. The latter is accomplished by calling the WAIT routine, passing to it (as an argument) the address of the ECW associated with the event being waited for. Upon completion of the I/O operation, an interrupt will occur. The interrupt supervisor will decode it, placing all status information into the ECW (thus setting it non-zero). Control will then be returned to main-line execution, which may be the WAIT routine. WAIT will ascertain that the ECW is now non-zero and will therefore return to the calling program. The program will then process the data in the ECW as post-operation device status by checking for I/O errors, etc. Note that IOSUP and WAIT may be called directly by a user program; however, the typical mode of operation will be to call a system subroutine which will in turn perform the detailed work. See Figure 3*2. ■31- low core high core Figure 3«2. I/O Subroutine Flow of Control -32- 3.^. Languages At the current time, the 1800 programmer has one language at his disposal - 1800 assembler language. Furthermore, the 1800 assembler is a System/360 program. The fact that the two computers may easily communicate with each other makes this situation an advantageous one, however, since the 1800 is not a good computer for compilers and assemblers (no character manipulation or translate instructions, for example ) . The lack of such a language as FORTRAN is not too critical when one considers that the System/360-75 i s much more suitable for numerical computations than the 1800. Besides being an order of magnitude slower, the 1800 has no floating point hardware. The Department is considering implementation of a higher level language in the future. ■33- HOV Ze 19?£ ^ ^