LIBRARY OF THE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAICN 5IO,8t lliUAL /KilhMtrK UMTS CLILI^E Cf \LKlPT ICw CF INIERACTIGN" ^'ITrflAXlXftlNIC PR0CE"S5D"R"S I.U4 AKiTI-^xIlC L^TA f CROATS 1.^.1 ShLRl fl>tD PUIM 1.^.4£ LC^G f-J/fcL FLIM l.-^.i FLL/UhC PLiM 1.^.^ DcCINAL 1.U5 iN^lRoCIiCNS EXECLTIC B> ST^ITHHiTIC "UNITS 1.5.1 ALL 1.5.2 SttTBALl 1-5.3 MLLUPLif _ 1.5.^ CI VIC t 1.5.5 CCI-P/Rt ALGEBRAICALLY _ 1.5.t CLN^ERl TC CE'CIMaL " 1.5.7 CCNVtPT TC FLCAIING PUiNT 1.5.6 CC^^fcRT TC LCNvi FiXEC PCIM 1.5.^ PCLYNLA^IAL c \(ALLA 1 1.ON 1.C6 tXcEPlICNAL CLNCillCNS FOR A^lThSETIC INSTRUCTIONS l.o.l CENfcRAL _ 1.0.2 C\.fcPfLCIp> ILiV) ~" ~ 1.6.3 ONCERfLCi* (LN) 1.5.^ invalil; deciwal data ud) 1.6.5 LLii: Li- SKiMFiCANCt (LSJ INTERNAL SIAIIL CESCRIPTICN 2.Ci oENEfAL z.1.1 CVER/Lt ELCCK LiAGRAM 2.1.2 CC^^£NTS CN THE STRUCTUrtE i. 1.2.1 INPUT 2.1.2.^ IMHAL AND TERMIN AL OP ER ATION S 2.1.2.5 /CCirrCN-iUSTirACTirR i.l.i.^ GthERAIiCN CF iHULUPLtS 2.1.2.5 OcTFCT i.l.2.fc CGCriEM LICIT GENERAUCN i.l.i.7 CLNOITICN DETET:TICN ~ i.l.2.d E)(FCNEM ARITHMETIC 2.1-2.S CCMRCL ~ li/Od/b^ '" SELI lUN U.l - 1/^ 2.C2 REGlSUfiS 2.2.1 M-ftE6I£ 2^2. 1 .J^ 2.2.1.2 2.2.1.3 k,Z»l Li-FfcGI 2 .'2 . 2 .i 2 .2.2.^ 2 .2 • 2 J J 2.1,:i iJf«-RfcGJ 2.2.3.1 2 .2 •3.2 2.2.3.3 2.2.4 LS-REGl 2.2.4.1 2 • 2 .4 .2 2.2.4.3 ^.2.5 Lf-P£G1 2.2.5.1 2.2.3.2 2.2.5.3 2.2.0 Lh-R£GI 2.2.6.1 2.2.6.2 2.2.6.3 2.2.7 Lu-PkGl 2.2.7.] 2 • 2 . 7 .2 2.2.7.3 1.2.6 Lh-RtGJ 2.2.8.1 2.2.8.2 2 .2 .8 .3 2-2".9 Lw- RE Gl 2.2.9.1 2 .2.9.2 2.2.9.3 Of SIGI^AL NAMES OF i>IGfiAL NAMES lEA GENERAL I>PLEM£NT4TICN PL/1 DEiC«lPTlflN Of SIGNAL NAMES SlEfi CLNERAL I^PLEMeNTATICN ~~ PL/l DESCRIPTION OF SIGNAL NAMES STta' GENERAL IfPLtMENTATION --- PL/1 DESCRIPTION STER GENERAL IfPlEMEfsTSTTClS^ PL/1 DESCRIPTION £T £R GENERAL INtLEMENTATION PL/1 DESCRIPTION OF SIGNAL NAMES GENERAL IfPLEMENrATION PL/1 DdSCRIPTlCN CF SIGNAL NAMES i 1 E R GENERAL ^^^LOETv^7^^:N PL/1 DESCRIPTION OF SIGNAL NAMES STER GENERAL IMPLEMENTATION PL/1 DESCRIPTION OF SIGNAL NAMES STER GENERAL UPLEMENTATION PL/1 DESCRIPTICN OF SIGN/L NAMES 2.C3 V-BLS INTERFACE 2.3.1 GENERAL 2.3.2 INPOT 10 IHE ARITHMETIC LNITS VIA THE W-BUS 2.3.3 IfPLEMEhTAI ICN 2.3.4 PL/1 DE6CSIFTILN CF SIGNAL NAMES 2. 04 XI-ELS INTERt^CE^ 2.4.1 GENERAL' 2.4.2 OUIFUT FPCM THE ARITHMfcfIC UNITS VIA THE XT-BUS 2.4.3 WPLEhtNT/TlCN 2.4.^ PL/1 DESCRiPTICN OF SIGNAL NAMES 2.05 SIGNfct-LlGlT SUE1RACTERS_ 2.^.1 GENER/t 2.5.2 IMFLEflENlAIIUN 2.06 CUNASSiGNEC) 1^/06/69 SELiiuN u.i - zr^ 2.07 .PKCPAo/»TUN LIGIQ i.7.1 OdNfcHAL ^.7.^ FIWSI LtVEt LCGIC 6£L AIIdMJS ^.7.3 itCCNL IhVEL 'LLClTXTULJJiTICNS ^.1.^ ThIHU Lfc\*.2 RfcCCCINt tARhriARE ^.9.3 MLLTIPLV EAlENDEITPTJErrSTCN " 2. IC WCCkL LlV IS ICN 2.10.1 GbNERAL 2.1U.2 FCNCTILNAL uESCRIFIION i.lC.i IfPLt^hM/lIiLA i.ll CCNtiTlCN LEIfcCT 2.11.1 Lw ZtftL LtltCT ^•ll.i.l GENERAL 2.11.i.2 i^PL£*'ENTATICN i. 11.1.3 PL/l CESGKIPTiCN GF SIGN/^L NAMES 2.11.2 Lh iE»iC CETECT"' 2 .ll.i.l GENEK/L 2.11.2.2 lfPLE>EMATICN 2.11.^.3 PL/l CESCRIPTICN CF SIGNAL NAMES 2.11.3 H. ALL ONES DETECT 2.11.3.1 GENERAL 2 .11.3.2 I^PLc^fE^TATTX^^ 2. 11. J. 3 PL/1 DESCHiPTiGN OF SIGNAL NAMES 2.11.^ HA^ HtGlSTERS 2-11. ^.i GENERAL 2.11.4.2 IfPL£>^ENTATIGN 2.11.4.3 PL/i CE^CRIPTIQM OF SIGNAL NAMES 2.11.5 FL/G h^TCH 2.11.5.1 GENERAL 2.11.5.2 i^PLE^EMATICN '' " 2.12 cXPLNtNT AfPCNENT LNirACCER ACCER CVERFLG* AND UNUtRFLOW DETECT ELL CLLNTER tLL CLLMtft CCNDIIILN CETECTICN FL/l CESCRIPTICN CF SIGPJAL N^AWE^ li 06/69 SECIIUN U.l - 3/4 2 .12 .A 2 .1^ .5 ^ .12 .6 i. .1^ .7 c .U .E 2.13 CCMUCL i.13.1 GENER/i i.l3.i 1ASK £IAGt LOGIC .CONTROL POINT) "2713.3 SECU£^££ UACL LOGIC 2. 13, A «tPLY >C£NEKATICN i.13.5 HARCwAPt ♦^♦♦** VCLU^t I ENDS ♦♦*4** 2.14 LAYCLT 2.14.1 L^VCIT OF PROCESSING HARChARE 2.14.2 C^^tTT^ATIE FEU bLtJ-dLUCK UJ- PRUCfcSSlNt HAKUWAKE 3.C UPEiiATIONAL OfaSCPIfTICN ' 3.1 CCNTRLL fLCkCI-ARUKG 3.2 INSTRUCT ICh LEXCCING ~ 3.3 LOADING Cf CPtR/NiiS 3.3.1 GENERAL ' 3.3.2 CLNTRCL fLCii TAliLES 3.3.3 TIMING 3.4 EXPONENI AFilhMEUC 3.5 FLOATING PCINT ACCITICNt SUBTRACTION, COMPARISON 3.5.1 GtNERAL 3 . 5. 2 CiTNTRUI-FLC 6^ TABLE S 3.6 MULTIPLIC/TICN 3.7 DIVISICN 3.8 CLNN/ERiiCN CF NUNatK TYPE _ __ _ _ _ _ 3.y i>fcCIM/iL CPERATICNi ' 3.10 POLYNCMIAL E^ALLATiCN _ ^ 3.11 RETURNING RESULTS 3.U MAINTENANCE *AC14:1TI£S /NO tXTERNAL DISPLAYS 4.C MEKCEC SIGNiftL fifiH.i. INDEX 5.C SIMULATICN LZ/Lt/t'i StLI ION O.l - 4/4 LIST OF FIGURES -inL"^F NO. TITl F 1 1 . • ^. '♦. 1 . ,1.2.1 7.2.1 ^. ^.-^ ,■>.?. 1 ,^.~.^ ,^.2.1 '•.2. 1 ^. ^. ^ 7.^.1 ,7.5.2 ,^.2.1 ■^ . 2 . 1 2. 1 ?. 1 "'. ] 1 . 1 2. 1 _ • i. 1 -. 1 5.2 ?. 1 2.2 ?. I 2.2 .9. S. 1 |.9.?.? .<:.^.^ j.lC.2.1 .10.2.2 Uo.^.i ! -^ . ? . ^ n. ^.^ M n . ^ . ^, - 11. 1.?. I ill. 2.2.1 "n .3.?.' SHTRT F LTNG FI FLfJATIN U X TICN C E PCS! ERFLPVJ LQCAH LCCKA y -F P CN LOG TICN C THE M- IT, SH TICN C R-^AY n M CF ^' L^GIC LCGIC CI SIGN F yccE w CF y OICCE RVAL S EC TION FCTIGN eCTir^N EC TION Q REG I H RPGI G REGI C I I I FORMAT CRMAT MAT AT MAT CN FCR TIC UN F M-RF THE THE THE TFE THE THE TFF THE THE THE THE TwEEN -^US I T-BUS F A SI TICN n CCRRE EAC GP Ht^£._G RCPAGA IC Die F THE SHIFT IFT GA F MULT RIVER ULTIPL FiJR ML AND L CCMPUTFR AR I TH IT BLO GISTER US_. REG METIC INDICATORS CK DIAGRAM (VER 2) US UM I'M LS LM UH UQ uc LH LC CUT REG OUT REG RFG REG REG REG REG PEG VALID NTERFA INTERF GNEC-D F "^IGN CTICN CUP RCUP.. TICN L DE i^AT Yl SUP ARRAY TF COR IPLY.P CCNTRO Y EXTE LTIPLY ATCH P LSI PUT 1ST PUT TST 1ST 1ST 1ST 1ST 1ST 1ST OAT CE ACE IGI ED- LCG ER G ER G ER FR ER ER FR EK FR A AND^ SELECTORS ATING AND SFLFCTCRS ATING AND SELECTCOS AND SFLFCTCkS AND SELECTORS CN INBUS AND TI I T SUBTRACTER DIGIT SUBTRACTER IC CGIC RIX BOARD SECTION OF THE M SHIFT ARRAY RESPONDENCE EICCLE TiNC CCNNECTICN L NDEO PRECISICN LOGIC EXTENDED PRECISION OSITION FOR MULTIPLY L niVISlON TC F'JLL. P.PECISJONL SIRUCTURE CCEL DIVISION MATRIX ELECT LCGIC FOR POSITIVE PARTIM REMAINDERS FOR NEGATIVE PARTIAL REMAINDERS LCGIC FOR. 7ERCN ANC XWOP, . LOGIC FOR ZEROP STER ZERO DETECT STPR ZERO DFTECT STER (BYTES C-5) AND TWON ALL ONES DETECT 1 /O^/f c SECTION 0.2 - 1/2 2. 11, A. 2, .1 2 . 1 1 . A . ? , ,2 2.1L.4.2. a 2.11.5.2. ,1 2.12.1.1 2.12.3.1 2.12.3.1 . 1 2.12.3.2, I 2,12.3.3. 1 2.12.4.1 2.12.^.1 2. l?.f .^ 2.13.2.1 ?.l-^..2.? 2 . n . ? . '^ ^.n. 2. A 2.13.3.1 2 . n . ^ . 2 2.13.3.3 ( 2.13.^.4 ?.n.^,5 1 2.n.M,i ! 2.n.A.? 2.13.'^.^ 1 2.1^.-^.4 1 2.n.4.^ 2.13.^.^ 2. U.-^ .1 1 2.13.5.2 1 MLCCK DIAGR/iM CF FA-REGISTEB 31.CCK DIAGRAM OF FB-REGISTER .. TYPiC 11-60 tRAteING NUMaeR 6L/^K CR •«' IF ORIGINAL QF URAMING IS IN MORKI.-^G FILE lAi FATFEH IhAN IN DRAFTING. IFE IMTI/LS AU fcL/^K DfcbCKlFTlLN OF DRAWING Tl-,E CAT£ CF THE HCTST RECENT VERSION DF THE TTRAWTNG- IhC. CF i'CMH, NC. OF DAY. LAST DiGiT UF YEAR) BLANK I IF PRELIA^INAKY CRAi4 ING IS I IF PACKAGING OF THE LCGIC SPECIFIED, bLANK OTHERWISE, 1 If ..IRING TABLE FirS"^1 EN" GET^ffATED" FDR DRA>n7TG7 BLANK CTHERtalSE. NOT LEMNEC CuMPLEIc, BLANK OTHERWISE I:T^ THE DRAWTNGKAS BEETJ NOTE •DATE' IS IHE LAIE OF THE MOST RECENT VERSION OF THE DRAWING. ATKINS DMNG. NO. OtSCBIPllON 210- 21C- 2iG- 210- 21C- 21C- 211- 211- 211- 211- 211- 211- 212- 2 12- 21^;- 212- 21^- 2 13- 21i- 01 •U2 Oi •0^ Cb 06 01 02 03 AU AU AU AU AU AU AU AU AU •0^*AU Oi)*AU 06*AU Ol*AU 02*Au Oi*AU 04«AU Ob*AU u 1 Ao U2*AU INPOI MODEL U OUCT ItN WJUEL C HiiuEL L WGChL L UO ANu FLAG RE Uw RtOi PAKllY iV ANL li^SlhUC ILLiAC bJM /^C cXPLNtN tUL REG tAU CLN LnA lLMRLL AND ASSIHILATION^ Alti TC NLOEL LIVISUN iVISlLN OlViSuR INTEkVAL SELECT I SELkCT CIUDt MATRIX IVISICN QUOTIENT ELTFFER Ob I PUT omTING UUCTIEKT BUFFER TNPUT TO DQ AND OH DETECT (fa akd fb) and tt.ag match lnes detect LOGIC i\iibICN IVISICN LH 2EKU GiSTfcRS 5ThH ALL ERf^OT; FLIP-FLOP NT RELIiTtKi wlIH NT DECODER Hon variant decoder iii fcxpunent akiihmeiic unit - block diagram EUU REGISTERS WITH JN/CUT GATTTHr ^ 7 LM I AUOlK ISTER-CCUNTER LIIILN ctlECT SSIoNtU PLiM VIN-Ol. DATE 03 07' 03 07" 0307' -Q3or U307' 0307 0307 0307 0307 1015 0213 0212 1127 Tr2T ll27'i OVZ'V l 1127 I VIN-U2 1003 1 Oi/Ol/69 SELI lUN U.^ -l/** .1 LUNIRuL CCMKuL PblM PCiM VIN-OJ Au Au AO AU AU AU Au AU Au AU AU AU AU AU AU Ao AU Ac Au Ao Au AU MU AU AU Au AU Au AU Au AU AU AU Au AU Au Au AU AU AU Au Au AL Au AU Ao Au AU ArtllhXbTlC UMT CAKL^ AKllHMtTIC LNII CAKl) V1N-U5 ~ L iYCur - TOP UAY LAVUuT - daircM Hxr M i^ M M M M t^ ub u:> uS Uj U5 us uS KtLdSTkK, KtGiblER. PLbiT iuNi> f C b i 1 1 L i\ S pcbiriLi\s J9-16 17-32 33-4a 49-64 UKI VhKS Htuiilkft StLcCIGR ANU GATfc KbGISrEP CcTPlT T.WlKItRb btLtClUK <-LIP/^LuPS KEGISIER kllH SELEulJRSf hITh :>hL£CTQRS, ^I]h itLtCTCK3, kUh StLtuTURS, lELtcTOA xin^EJrs CUIPUT UAIINo, PJSITIui^i CUl*^L>r u/JTING, PCSITICN5 ULIPLT v^AriNU, PJilTlGNS LUTPJT GATING, PQSITICNS KEGibTkR KtUi SILK REGlbTth LuAC AND KEGIbl th HtUliTER HtuISTER Rt£iSIfcR PUSITTONS PGSITiGNS PCSITIGNS FUSiTIGNS 01-16 17-32 33-48 4^-64 -773=Tr5T Ul-lb 19-36 37-54 55-64 DRIVERS (SAME ptrsi liUNs Ui 4.S, LM REGISIER CuTPLI GATING oA REulsrER kTiH SELECTORS, U.^ KtGlSTER kllh 5tLECfCK6, PQ:>ITIUNS UM REulSTEf hllH :)EL£lTORS, PC5IT1CNS UM REGISTER WiTh StLECTURS, POSITIONS of LCAo fihL SfcLtCTQK CRiV£R.S (SAHE AS UM REGISTER CUIPlT ^ATING, PJSITIUN^ UM RtGUTER CUTPuT GArTNC "PUSTTIUNS L:>, LM ♦ifcGIilER CUTPLI GATING LS REGISTER, PLSlTlLiNS 01-Od LS REuISIER, PCSITICNS 09-24 LS REGISltP. POSITIONS 25-4C Li» REGISTER, PCilTIGNS 41-56 R'EbrSTER, TuSTTIGNS 57-^4 AS 223-Od) U1-T5- 17-32 33-4d 49-64 222-05) 01-32 33-^^4 UKIVERS (SAME AS (DETAIL OF CARO) 222-10) LS LM, LS RELI^TEK GATE DRIVERS LM REGISTER, PCSITICNS 01-08 POSITIONS jQS-24 PCilTICNS 25-40 PLSITICNS 41-36 PCSITICNS ^-6¥ , L:> register gate CRiVER:> (SAME AS REGISTER tallH SELECTORS, POSITIONS mllh itLECTCRS, POSITIONS hITH SELECTORS. POSITIONS WITH SELECTORS, POSITIONS ^UCXCii rSTYERTS LMuLh7 OF Lh SELElTOR LnLlUh CF UF SELECTOR { SAME AS 225-06) (DETAIL OF CARD) LM LM LM LM LM Uh UH UH Jh UH REGISTER, RtoISTER, REGISTER, RtGISTER, REGlSTtR REGISTEfi REGISTER LCAC' A No u« u^ Uw RtGISTER EEGISIER REGISTER REulSTbK LLAl ANC kITH SELECTORS, kllH SELECTORS, ^llh SELECTORS, WTTh SELECTORS, PUSlTICNi> POSITIONS POSITIONS POSl I ICTTa 10098 10096 071bd U/i8B U307^ 03079 03079 03079 UJ0 79 121/cj 03 079 03079 03079 0307V 03079 03079 03 079 03079 03079 03079 307 9- 03U79 03079 03079 03079 03079 -trJ0T9 03079 030 79 01048 03079 03079 nir- 030 7^ 03079 03079 03079 03079 03079 0307 9 03079 03079 03079 03079 03079 n -ri 03079 03079 03079 03079 03079 03079 i7*A» SELECTOR DRIVERS LuLlUC, LCRIUC, ^NO StTUGCNt OF Ug SELECTOR uG SELtCTCR FLIP/FLOPi 03079 03079 03079 12178 ShCTioN 0.4 ^-znr 228-01 228-02 228-03 228-04 228-05 22 8-06 22 9-01 229-02 229-03 229-04 229-C5 229-06 230-01 23C-02 23C-03 230-04 230-05 240-01 240-02 240-03 240-04 250-01 250-02 25C-C3 25C-C4 25C-05 25C-C6 240-07 250-08 250-09 250-09 250-10 250-10 2 50- 1 1 NOTE 270-01 270-02 270-03 27C-C4 27C-05 270-06 27C-07 28C-C1 280-02 280-03 280-04 280-05 280-06 2aO-0 7 280-Ca 2U0-09 ^8L-iO 280-11 29C-01 290-0^; AU AU AU AU AU AU AU AU AU AU AU AU AU AU AU AU AU AU AU AU AU AU AU AU AU AU AU AU AU AU AU AU AU AU THcRfc Lh LH Lri LH LH LO LO LC LO AE^ISTER, REGISTER, PC^ITIGMS PLSlJlChS .01-0 a. 09-24 25-40 LQfeJALL ILF_CARJ3) REGISItR, POSITIONS 41-56 MfcGlSIER, PCSiriCNS 57-64 LOAC CRiVtRS (SAME AS 229-061 REGISTER, PQSITICNS 01-Ofi ^DETAIL Of CARO) REGISTER, PLSITICNS 09-24 R£GI£TEI<, POEIT IONS 25-40 REGISTER, PC-STflClvrS 4l-"5^ REGISTER, PG^SITIQNS 57-64 Lw _ LO LCAC CFIVtRS (SAME AS 228-7i6J BLK UiAGRAM Cf V-8U^ AND X-fiUS V/-BLS T6RMINATU8S, X-BLS ORI VERT, B¥TFS r,T..3,4 V-bUS P/RIiy Ct-£CK^Ni6j BYTE;> 1,2 y-btS PAKIJy ChECKlNG, BVTES"~T,4' y-bUS TERMIMATQRS, X-B05 DRIVERS, BYTE XT BL5 SELECT CK FARIIV GENEKATCR, BYTES 1,2 PARITY GtKERATCH, BYlES^ 3,4 GXT SiltLTCR ANC GATE CRIVERS XT tiLb XT £0;> SIGNED SIGNED SIGNED SIGNED SIGNED SluNED S I G^ ED :>IGNED URIWERS DIGIT DIGIT LIGII DIGIT DIG 11 Dli^I 1 DIGIT DIGIT EOR Sob TR AClOR Sb£THACTCR SLETRAGTCR SCtilRACTOR SuetR ACTOR SLd TRACT CR SUBIRACTCR SUJaTRACTCR SOS CuNTRCL UP uF UF OF OF "5i; "TTr~2» Sl» 2ND 4 S2,. 1ST 4 S2» ZHD 4 S3, isr 4 S3, 2N0 4 S4 • rrr" 4 S4* 2N0 4 AND H SHIFT Si,S^,S3 NEG ^ND G DRIVERS UBSJLETE DRIVERS FCR iDS CCNTRGL AND H SiilTT ARRAY (S3 AND S3,S4 NEG /ihU G DRIVERS UdSU LETE dV CCRI«ECTICN LCGIC, Ti i S2 ,""3"3 , AND posniuNs POSITIONS pusniuNs POSITIONS PirsrrTioN3 POSITIONS PD3TTTDN3 D"F POSITIONS OF BYTES ARRAY (SI AND S2T~ BY I bS BYTES bYTES' BYTES BYIES BYTES BTTFS"' S4T 54 AU AU AU Au AU AU Au AU AU AU AU AU AU AU AU Au Al. Ao AU Au IS NC 26C- SERIES. PKCFAG/^llUN LOGIC, FIRST LE VEL LEVEL LEVcL LEVEL LEVEL POSITIONS POSITIONS POSTTICKS POSITIONS 01-12 13-24 2 5-36 37-48 PRGP^U/IICN LOGIC, FIRST PKLPAGiillCN iCbIC, FIRST PROPAG^UCN LOG-IC, FIPSI PKCP/G/IICN ICG iC, FIRST LEVEL POSIT IONS 49-611 PROP. LOGIC, 1ST LEVEL POS 61-64, 2N0 LEVEL POS 01-32 PROP. LCGIC, 2NU LEVEL FOS 33-64, 3RD LEVEL POS 01-64" H ihlfl AKH4Y POSITiCN:> Yd, I) - Y(l,8) Yd, 9) - Yd,40J Yd, 41)- Yd, 64) Y(2^Tr~- __Q3ai9 03079 03079 03079 . "03079 03079 . CB 079 : 03079 . ~uiij/g r 0307y . "030 79 I 03079 ~U3079 03079 L "OJUT^L 122971 03079 , 03079 03079i; 03079L; DTDT9n 03079 LJ 03079 11 0307911 030791) 30 79LJ ~~Tn079Ii 030791; "0307911 02l5di: "0307911 021581 — D3TJ7gr "03 0791: 030791! ""030791 030791 POSITICNS POSITIONS P'CSITICNS FOSdlQNS pcsiriCNS POSITIONS pcsiriCNS FUSITIONS cruek:> ftrPtATEC ChDVl GAIES HUCI IPL UK REClDE MLLUe^ EJHENUi-D PKECISICN SHIFT SHIFT bhlf I SFIFT bHIFT SHIFT SHIFT SHIFT ShlF 1 Shin ARRAY ARHAY ARR/y AKHAY ARW/ Y ARRAY ARK^ Y ARPAY -D3UT9I 030 79 1 03079 I 030791 l}3079l 030791 Y(2,33)- Y(3,U - Y(3,33)- Y(4„l» - Y(4, 33)- BY Y{2,32) - Y(2,64) Y(3,32r" Y(3,64) 7(4,3Tr" Y(4,64) 250-09, 030/9 1 030 791 "030791 O307SI TBUml 030 7Sl ^bU-lU LOGIC U3^ft8 T 0307^^1 njT079l 03079 1 05/01/69 SEC I lUN U.4 - 3/4" ► ♦♦♦ NUfc A L,RAkH^im NoNthK PRErlXEC WITH * FC* OENJftb A CUNJKJL FLUti CHAKI ♦ •01 ♦AU V-bLS iNFLT cCMRUL SEUUEUCt VI N- C I ,-C2 ,-03 I002d 1 -0^ ♦AO V-fct:> INPUT CCMi^CL SfcGJfcNC k ViN-Q^,-05 lOOb o 1 -Gj ♦Ao AJU.SctlrtALl. uK CCMPARt fATTTF ~ " ITZD5 1 -J** ♦AU ALLCN oHf ALIGN Ltf bh TO Ut OiZU'y 1 ■J5 ♦AU cALLUL/IlLN CCMRLL fCR AiC (CAD 03209 1 •06 ♦AU i-^uHH Ut Ui2U^ I ■J7 ♦AU it! fL/GS 03209 1 ■Oo ♦Au MULTIPLY (hPt) 031^ 9 I •09 ♦AU MULTIPLY tNC (NFYENU) OTZtT? 1 :^««4>^« bND ♦♦♦♦♦♦ /./6s ' " ~~" SE CTi orr-a. V ^ «►/'♦ 1.0 Introduction 1.1 Purpose, Scope and Orgemization of the ManuaJ. This manual is a working document for the design, construction, checkout, and maintenance of the arithmetic units for Illiac III. It is an evolving dociment and will be frequently updated. Readers are encoioraged to notify the author of errors or suggest clarifications. Although the manual is intended to be essentially complete in itself there are supporting documents available to readers with special interests. These are described below: Detailed Logic Drawings - Typical cross sections of logic are shown in the manual^ however, due to their bulk, the detailed logic drawings are not included. The originals of these drawings (see Drawing Index in Section O.O) are maintained by the Illiac III drafting section and will generally be available only to those directly involved in construction, checkout, or mainteneince. Engineering Manual - The Engineering Manual contains construction details for all of the printed circuit boards with which Illiac III is con- structed. Copies of the logic diagrams for relevant boards are included in the AU Manual. The Engineering Manual is also maintained by the Drafting Section and is available on a need-to-know basis. DCS Report No. 333: "Design of the Arithmetic Units of Illiac III : Use of Redundancy and Higher-Radix Methods", by D. E. Atkins - In keeping with the experimental nature of Illiac III, the arithmetic units are intended to be a practical testing ground for recent theoretical work in computer arithmetic. This report is to represent the more theoretical aspects of the design, especially the use of a redxmdant number representation. The use of redundancy is a prime factor in obtaining high-speed operation. This report is readily available from the Department of Computer Science , Mailing Center, Room 222 DCL, University of Illinois, Urbana, Illinois 618OI. The 8/18/69 Section 1.1 - 1/2 AU Manual itself is primarily intended to be a design description as opposed to a design Justification. Publication: "Higher Radix Division Using Estimates of the Divisor and Partial Remainders", by D. E. Atkins - This paper presents the theoretical basis for the division scheme implemented in Illiac III. It is published in the IEEE Transactions on Computers , Vol. C-IT, No. 10, (October I968), pp. 925-93^. Reprints are available from the author, or the Illiac III office, 297 Digital Computer Laboratory. The arithmetic unit manual is divided into four Jaajor sections: an introduction, an internal static description, an operation description and a presentation of AU simulation programs. The internal static description, Section 2, begins by presenting the blocks diagram of an arithmetic unit and then describes each sub-system of the \init. This description is presented at three levels of detail: first, as a verbal function description; secondly, as a block diagram of the sub- systems; and thirdly, as a detailed view of the actual logic. For most sub-systems only a typical section of the logic is shown. Likewise the operational description, Section 3, is presented in steps of increasing detail. Each order executed in au AU is described as a sequence of sub-operations. These sub-operations are defined yerbally and then with detailed flow charts and flow tables. Section 4 is a alphabetized list of signal names together with the PL/1 definition. 8/18/69 Section 1.1 - 2/2 1.2 Conventions The logic symbols used in this manxial conform to MIL-STD-806B , Graphic Symbols for Logic Diagrams . Niimbers appearing within the symbol (if any) specify the Illiac III card type as defined in the Engineering Manual . Positive logic is used throughout. The symbol, 1, denotes a logically true state and corresponds to a nominal +6 volts. The symbol, 0, denotes a logically false state and corresponds to a nominal volts. Logic notation is defined below: Truth Table for Function AUD OR Variables a, b a b ab 1 1 1 1 1 a.., b avb 1 1 1 1 1 1 1 Logic Symbol ab avb NEGATION or COMPLEMENTATION 5/16/69 Section 1.2 - 1/ k Function NAND (Not AND) NOR (Not OR) EXCLUSIVE OR EQUIVALENCE (Complement of EXCLUSIVE OR) Truth Table for Variables a,b a b ab 1 1 1 1 1 1 1 a b avb 1 1 1 1 1 a b a®b 1 1 1 1 1 1 a b aEb 1 1 1 1 1 1 Logic Symbol ab avb (no specific symbol) (no specific symbol) 5/16/69 Section 1.2 - 2/ k The arithmetic unit has "been simulated using PL/l. It was found that this language is useful in describing both struct\ire of registers, buses, etc. and the function of the various control signals. The descrip- tion of each subsystem therefore includes a PL/1 description of signal names relevant to the structiore. The following conventions have been adopted: 1. Registers and buses are defined as bit strings. Example: DECLARE US BIT (61^);/* TRUE OUTPUTS OF US-REGISTER*/ DECLARE USSEL BIT (6i+);/*TRUE OUTPUTS OF US-SELECTOR*/. 2. Subsections of a register or bus (any bit string) are defined using the PL/l function, SUBSTR. The general form of calling is SUBSTR (S, i, j) where S is the name of a bit string, i is the first position of the substring, and j is the length of the substring. Example: SUBSTR (US, 1, 32) is the left half of the US Register. 5/16/69 3. Signals which are common across many positions of a register, selector, etc. are divided into sub-signals. This is usually done only because of loading considerations but in some cases the sub-signals will be operated independent of each other. Sub-signals are designated in the form nm, where nm denotes that the signal is common across byte n through byte m. If nm are not given, then the signal name is operative across all bytes, through 7- Example: LDUSGl /*LOAD US-REGISTER BYTES AND 1 */ h. The function of signal names are defined as procedures. The name of the procedure is the name of the signal. Example: LDUSOl: /*USSEL BYTES 0-1 TO US BYTES 0-1 */ PROCEDURE; SUBSTR (US, 1, 16) = SUBSTR (USSEL, 1, l6); END; LDUS: PROCEDURE; CALL LDUSOl; CALL LDUS23; CALL LDUSl+5; CALL LDUS6T; END; Section 1.2 - 3/i+ 5. Shifting is accomplished by use of SUBSTR and concatenation (i!). LSL8US: PROCEDURE ;/*LS LEFT 8 TO US */ US = SUBSTR (LS, 9, 56) || '00000000'; END; 6. The PL/1 logical operators are as follows: I IS OR & IS AND -^ IS NEGATION 5/16/69 Section 1.2 - U/U 1. 3 Brief Description of Interaction vith Taxicrlnic Processors The two identical Arithmetic Units (AU) perform most of the arithmetic operations in the ILLIAC III system. Integer addition and subtraction, as well as several iinary operations form exceptions and are actually executed in the Taxicrinic Processors. (These exceptions are noted in Tahle 1.5-2 The prime responsibility of the Arithmetic Units is the high-speed execution of floating point arithmetic operations. The units also provide facilities for integer multiplication and division and conversions from one number-type to another, e.g., floating to long fixed. As in the case with all other units of the system, com- munication with the processors is via the Exchange Net. The Arithmetic Units interact primarily with the Taxicrinic Processors (TP), although paths are also available between the AU's and the I/O Processor. The Exchange Net assigns an AU to a requesting Processor and also returns the results of an arithmetic operation to the processor which initiated the operation. Figure 1.3.1 illustrates the location of the AU's in the overall system. The following is a general overview of the operation Of the Arithmetic Units within the ILLIAC III System. The execution of an arithmetic instruction begins in a Taxicrinic Processor. The operands are assumed to be in the top of the Operand stack of the TP. When a TP encounters an arithmetic instruction (an instruction with the mnemonic byte of the form 10XXXXXXl*it determines whether an AU is required to execute the operation. If this is the case, the TP places a request with the Exchange Net, which in turn locates and assigns an AU which is not in use. The TP then sends the AU a control byte containing the instruction variant (IV): add, subtract, etc. and the number type (NT): fixed, floating, etc, together with the operands. *The last bit is a flag bit. 9/18/69 Section 1.3 - 1/3 TAXICRPJIC J PROCESSORS ^c ^^^ ^^^ ^^^ 7^^ J^ ^ ^ ^ FC >C ^.^ ^S^ ^^^ 7^^ J^ sc DC ^ ^ ^ FC SC DC ^c — ^t »5 ^t >' 7^ "^ ^ ^ FC SC DC ^C ^^^ >. ^5 7^^ 7"- \ \ ^^ ^C ^^^ ^C 7*^ ?^ i, i,^ >5^ ^5^ ^C ^C A FC SC DC ^ ^ ^ ARITHMETIC UNITS AU AU J T lU EXCHANGE NET- :i 1 PAU :i I/O PROCESSORS I ((((({( ■CENTRAL UNITS i^IXXXX^ CHANNEL INTERFACE UNITS 4|5|6|7|el9|l0|ll 12 13 14 15 SECONDARY STORAGE SCAN/DISPLAY INTER- MACHINE LINKS LOW SPEED TERM. Figure 1.3.1 - Schematic of Illiac III Computer 8/18/69 Section 1.3 - 2/3 Since the data paths through the Exchange Net are one Word wide (U bytes) and since in general, the operands consist of more than one full word, a series of transmissions is required. Upon rapid, initial decoding of the instruction variant and nxomber type, the AU loads the operands as received, a word at a time, into the appropriate registers. When all operands have been received, the TP-AU path is broken and the AU proceeds with execution of the operation. When the result has been formed, the AU notifies the Exchange Net, which in turn accesses the TP which initiated the AU operation. The result is then returned, a word at a time, to the TP. If an error condition such as OVERFLOW has occurred, a "l" appears on a designated line in the AU to TP control byte. The flags of the erroneous result being returned are set so as to indicate the nature of the error. Upon receiving the result, the TP places it in the top of the operand stack and continues to the next instruction. The AU is released and is available for the next assignment. The expected execution time for floating point (56 bit mantissa) addition, subtraction, and multiplication is 3-6 ysec. and 8-9)Jsec. for division. 8/18/69 Section 1.3 - 3/3 l.U Arithmetic Data Formats There are four types of arithmetic data used in Illiac III. The attributes of these data are as follows: Base = binary or decimal Scale = fixed point or floating point Mode = real Precision = l6 bit integer, or 32 bit signed integer, or 56 bit signed fraction and 7 bit chracteristic, or 14 decimal digit signed integer. These attributes have been combined to form four different number types as described in the remainder of this section. Although not illustrated in the previous figures, a flag bit 'is associated with each byte of the four number types described. Operands used in arithmetic operations may have flags set, and thus the question arises as to the flag setting of an arithmetic result. The flag bits of numbers pro- duced by arithmetic operations will have the following significance. a) For unary operations (other than number type conversions) the flags of the operand are unchanged. b) For operations with two or more operands and no error conditions, the flag setting of the result is the flag setting of one of the operands. c) For comparison instructions, the flags transmit the result of the comparison from the Arithmetic Unit (AU) to the Taxicrinic Processor (T?) via the Exchange Net (XN) . d) For operations resulting in error conditions, the flags transmit the type error condition from the AU to the TP via the XN. The significance of arithmetic flags is described further in Section 1.5.10. 8/18/69 Section l.i+ - 1/1 l.U.l Short Fixed Point Base = binary Scale = fixed Mode = real Precision = l6 bit, unsigned integer if an address. 15 bit, signed integer otherwise. A short fixed point niomber is a half-word binary integer which is treated as signed or unsigned depending upon its use. When used as an address, a short fixed point number will always be considered positive and since all l6 bits may be required to represent the magnitude, no sign bit is explicitly specified. Addition of addresses, as performed in the pointer modification 1 6 operation ADDITION, is computed Mod (2 ) , in effect allow implicit address subtraction. Subtraction of addresses, as performed in the pointer modifica- tion operation CONDITIONAL SUBTRACTION, is performed as a two's comple- ment subtraction, Mod 2 . The results will always be treated as a positive integer. Numbers of the short fixed point type may also be used for other than addresses in any of the 13 arithmetic operations. In this case, the most significant (MS) bit will be treated as a sign bit and a negative number will be represented in two's complement form with a sign bit of 1. The range 15 IS of these integers is -2 ^ to +(2 ^ -l) i.e., -32,768 to +32,76? and overflow will be checked. ^ 2 bytes )| I Number Type Code = GO I Sign or MS digit J Figure 1.^4.1.1 - Short Fixed Point Format 8/18/69 Section l.U.l - l/l 1.U.2 Long Fixed Point Base = binary Scale = fixed Mode = real Precision = 31 bit, signed integer A long fixed point number is a full-word signed integer. Positive numbers are represented in true binary notation with a sign bit of zero. Negative numbers are represented in two's complement notation. The range of these integers is -2^^ to +(2^^ -l), i.e., -2,1^7,1+83,6^8 to ■^flkj ,U83,6h'J and overflow will be checked. k k bytas r.jgn bit Number Type Code = 01 Figure 1.4.2.1 - Long Fixed Point Format ! 8/18/69 Section 1.U.2 - l/l 1-^.3 Floating Point Base ^- binary- Scale = floating Mode = real Precision - 56 bit, signed fraction 7 bit characteristic Floating point numbers are a double word in length, subdivided as indicated below: K 8 bytes -Fraction Radix point Characteristic vSign of- fraction Number Type Code - 10 Figure l.U.3.1 - Floating Point Format The first bit ds the sign of the fraction. The fraction is always in true representation, i.e., the fraction of negative numbers is carried in positive form. The fraction is expressed in base I6, hexadecimal form and therefore consists of lU hexadecimal digits. In hexadecimal represen- tation, the c haracteristi c represents the power to which 16 must be raised to express the true magnitude of the number. The 7 bits of the characteristic are treated as an excess 6U number with range -6k to 463 corresponding to the binary values through 127, respectively. The characteristic zero, for example, is represented as 1000000. 8/18/69 Section 1.U.3 - 1/2 A floating point number in main store or produced as the result of a floating point arithmetic operation will always be normalized. For the hexadecimal representation, this means that the fraction will have a non-zero, high-order hexadecinfial digit . This type normalization permits the three high order bits of a normalized number to be zero. Normalization is not programmable. Under the normalization described above, the range covered by this notation is l6~ to (l - l6 ) x l6 , which is approximately '^.h x 10~ 75 to 7 -2 X 10 . The binary representation of these maximum and minimum values are shown in Table 1.1+. 3.1. A floating point zero will be represented as a number with th» most negative, zero fraction, and positive sign as indicated in the figure below. All zero results will be returned from the AU in this form. DESCRIPTION NUMBER POWER OF 16 CHAR FRACTION Maximum positive number 1.0 0.5 Minimum positive number True zero +7.2 x 10'''^ - (1-16"^ ) X 16^ 1111111 1.0 X 10° St 1/16 X 16"^ 0.5 X 10° =i 1/2 X 16° 5.U X 10"'''^= iS""*" X 16 -6k +0.0 = X l6' .6U 1111111 All I's 1000001 00010... 1000000 10000... 0000000 000100 . . . 0000000 All O's Table l.U.3.1 Examples of Floating Point Representation 8/18/69 Section l.i|.3 - 2/2 l.k.k Decimal Base ■" decimal Scale = fixed Mode = real Precision = ik digit, signed integer The alphanumeric representation of decimal digits uses the USASCII code extended to eight bits. The high order k bits are designated the zone and are 0101 for decimal digits. The low order k bits are the binary encoding 0000 - 1001 of the digits 0-9 respectively. 1 byt£ r °.^.°.^: I . . Zone BCD Figure l.i|.l|.l - USASCII Digit Tormat A plus sign (-;-) is represented as 1011 and a minus sign (-) as 1101 in the right, half of the left-most byte of the number, i.e. in the half byte designated "S" in Figure I.U.I4.2.* •Definition of USASCII-8 taken from IBM System/360 Principles of Operations , File S36O-OI, Form A22-6821-T, P- 150.1. 8/18/69 Section l.U.U - 1/2 Decimal operands, i.e., decimal numbers to be sent to an arithmetic unit, must be in a packed or unzoned format with two digits rather than one digit per byte. A decimal number consists of a double word subdivided into BCD digits and a h bit sign as shown below: 8 bytes X S Ta'o BCD digits per byte X = Not used , ^^ ^ + = 1011 S = Sign - = 1101 Figure l.ii.U.2 Decimal Number Format 1 1 1 1 1 1 1 1 1 1 1 1 — r"-- 1 1 1 Number Type Code = 11 Alphanumeric, or zoned format, may be converted to the above format by use of the PACK instruction of the TP. The decimal number zero may be either plus or minus, but in either case an Equal Zero (EQ) indicator will be turned on when it is tested with a Test Algebraic (TA) instruction. 8/18/69 Section l.U.U - 2/2 1.5 Instructions Executed by Arithmetic Units This section describes the arithmetic instructions. The arith- metic instructions which are executed in a Taxicrinic Processor are in- cluded in Section 2.2.9- of the Programming Manual. An asterisk(*) by a name denotes an order which will not be available in the initial version of the Illiac III Arithmetic Units. Provisions are being made however for their eventual -incorp- oration, either by additional hardware or as programmed macro-instructions. The following conventions are used in this section. a. "Fixed" includes both short and long fixed point format unless otherwise noted. b. A indicates the location of the Operand Stack Pointer (0SP). c. The abbreviations used for Indicators are as follows: 0V ^ Overflow L3 = Loss of Significance G'x " Greater Than EO ■-'■ Equal LT - Less Than FM ^ Flag Match UN = Underflow ID -- Invalid Decimal Data The flags of results of unary operations other than number type conversions are unchanged. The "flag" convention for binary and multi-cycle arithmetic- is of the form: where F -^ 'the flags of" X = the operand next to the top operand W - the result produced *- - "replaced by" 8/25/69 Section 1.5 - 1/5 f . "Flag" convention for the conversion instructions is of the form: F' . . - F , i-j ra-n where the flags within a number type are numbered consecu- tively 0, 1, ..., 7 from left to right. F = the mth through nth flag of the original, unconverted m-n number . F' . . = the ith through jth flag of the resultant converted ■*■ ~ J number . *- "replaced by" g. Note that when an arithmetic computational error occurs, the flag setting of the result is not a copy of the flags of the operand, but is rather an indication of the type error which has occurred. (See Section 1.5.10). Arithmetic Indicators include two types of indicators; comparison in - icators and computational condition indicators . Since all except fixed point comparisons (CPRA) are executed in an rithmetic unit, provisions have been included to return the results of the com- Eurison (GT, LT, EQ, m) to the Taxicrinic Processor. This transfer is accom- Lished by returning a floating point zero with the flags set to indicate the ssult of the comparison. 8/5/69 Section 1.5 - 2/5 i When this pseudo-result;, zero, is received by the Taxicrinic Processor, the flags indicating the results of the comparison set indicator flipflops which may be tested by a subsequent instruction. For fixed point comparisons and test algebraic (TA), both of which are executed solely in a taxicrinic processor, the indicator flipflops are set directly. The comparison indicators are designated as follows: EQ = Equal Zero GT - Greater Than LT = Less Than FM = Flags Match The flags of a result which set these indicators are called comparison indicator flags, and are described in Table 1.5.1. The comparison indicator flags are assigned as follows; Flag of Byte Number GT 5 EQ 6 LT T FM 8 Byte numbering is to 7> left to right. Table 1.5.2 is a summary of the arithmetic iinit order code. 8/25/69 Section 1.5 - 3/5 TABLE 1.5.1 COMPARISON INDICATORS INDICATOR AND DESCIIPTION ORDERS IN WHICH *PSEUDO RESULT INDICATOR MAY OCCUR RETURNED FRCM AU TA None GT = 1 CPRA ZER^ TA None EQ = 1 CPRA ZERfb TA None LT = 1 CPRA ZER25 GT - Greater Than A > A > P Eq ■ - Equal A - A - E LT - - Less rhan A < A < B FM ■ - Flags Match Flags of A =^ 0, FM = 1 Flags of A / 0, 5M -- Flags of A =- Flags of 3, M Flags of A ^ Flags of B, m TA OPEA None FM = 1 ZER0 arithmetic unit is used only for Decimal and Floating CPRA. TA is ^.;cuted in the taxicrinic processor for all number types. In all cases the operands in the 03 are not changed. /25/69 Section 1.5 - ^/5 TABLE 1.5.2 ILLIAC III ARITHMETIC UNIT ORDER CODE ORDER NUMBER TYPE Instruction Short Long Mnemonic Variant Fixed Fixed Floating Decimal (None) 0000 « « » tt CVL 0001 TP « 10 11 CVF 0010 00 01 « 11 CVD 0011 00 01 10 » NEG 0100 TP TP TP TP ABS 0101 TP TP TP TP MNS 0110 TP TP TP TP TA 0111 TP TP TP TP ADD 1000 TP TP 10 # (None) 1001 ^ « « « SUB 1010 TP TP 10 # CPRA 1011 TP TP 10 « MPY 1100 00 01 10 « POLY 1101 * « 10 # DIV 1110 00 01 10. « (None)# 1111 if « « « *Not defined. No operation will take place. TP - This operation performed in Taxicrinic Processor, # - IV = 1111 is used to indicate the final coefficient in a POLY order. 8/25/69 Section 1.5 - 5/5 .5.1 Add ADD 10|10 Q|NT Add the top two numbers in the 0S, decrement the f)S? by CS (cell size) and load the sum into the new top of stack position. Before ADD B After ADD A + B Flags: F(A + B) ^ F(A) Fixed: Indicators: 0V (Executed in TP) Floating: Indicators: 0V, UN, LS ♦Decimal: Indicators: 0V, ID .5.2 Subtract SUB ^ 1 1 N T Subtract the top number in 0S from the next-to-top number, decrement the 0SP by 'CS and place the difference in the new top of stack position. Before SUB B After SUB A - B Flags: F(A - B) - F(A) Fixed: Indicators: 0V (Executed in TP) Floating: Indicators: 0V, UN, LS ♦Decimal: Indicators: j6v, ID i /15/69 Section 1.5-1/2 - l/l 1.5.3 Multiply MPY 1 0[l 1 OiN Tl Fixed: Floating: * Decimal; Multiply the next-to-top number (multiplicand) by the top number (multiplier) in the 0S. Before MPY A B The most significant part of the product (A least significant part (A the multiplier. Cell size of result is twice CS of operands. After MPY B) replaces the multiplicand; the B) replaces L TFbOTa^ ^)m^ F[A], F[(A . B)_]= Flags: F[ (A Indicators: V^ The normalized result replaces the multiplicand, and the 0SP is decre- mented by CS. After MPY A Flags: F[A • B] - F[A] Indicators: 0V, UN The unnormalized result replaces the multiplicand, and the 0SP is decremented by CS. As both operands and the result, are double words, the sum of the number of significant digits in the operands must be < lU to prevent overflow. After MPY A • B A Flags: F[A • B] *- F[A] Indicators: 0V, ID *A double length result is returned for fixed multiply so as to permit fixed point numbers to be interpreted as either a fraction or integer. Overflow of the single length boundaj^y is checked and a flag is set if it occurs, however, a Bogus Result interrupt is not generated. 12/9/69 Section 1.5.3 - 1/1 1.5.^ Divide DIV 1 1 1 N Fixed: Floating: ♦Decimal: Divide the next-to-top number (dividend) by the top number (divisor) in the 0S. Before DIV B The quotient replaces the dividend and the remainder replaces the divisor. "a/B I Remain After DIV Flags: F(A/B) -^ F(A), F(Remainder) = Indicators: 0V The quotient replaces the dividend, and the 0SP is decremented by CS. After DIV | A/B Flags: F(A/B) *- F(A), F(Remainder) = Indicators: 0Y, UN The quotient replaces the dividend and the remainder replaces the divisor. A/B After DIV Remain A Flags: F(A/B) *- F(A), F(Remainder) = Indicators: ^V, ID Remainder has same sign as dividend (A-Op) except zero is always positive. /25/69 Section 1.5-^ - l/l 1.5.5 Compare Algebraically CPRA 10 10 11 N T Fixed: Floating: "^'Decimal: Compare algebraically the next-to-top number in 0S with the top number in the ^S. Set GT, LT, EQ Indicators. Compare flags for match or no match and set appropriate indicator. Decrement 0SP by CS. If A - B > 0, set GT If A - B = 0, set EQ If A - B < 0, set LT If flags of A match flags of B, set FM Before CPRA B After CPRA Flags: Unchanged Indicators: GT, LT, EQ, FM in TP) Indicators: GT, LT, EQ, FM, Indicators: GT, LT, EQ, FM, ID, : (Executed 8/25/69 Section 1.5-5 - l/l 1.5.6 Co nvert t o Deciti .a^ CVD 1 I 1 N T Convert the specified number on top of 0S into a packed (2 BCD/byte) double word decimal number. 1.5.T Short Fixed: Flags: F'q_^-Fq_^ ^■2-T = ' Indicators: None Long Fixed: Flags: F'q_3-Fo_3 Indicators: None Floating: Flags: F'q_^-Fq_^ Indicators: OV Decimal: N0P Convert to Floating Point CVF 10 1 N T Convert the specified number at top of 0S into a normalized floating point number . Short Fixed: Flags: F' 0-1 0-1 F'2-7 = ° Indicators: None Long Fixed: Flags: F' 0-3 0-3 i Floating: Decimal: ^\.i - ° Indicators: None N0P Flags: F'q_^-Fq_^ Indicators: ID 8.?5/69 Section 1.5.6/1.5.7 - 1/1 1.5.8 Convert to Long Fixed Point CVL I 1 I Q i| n" Short Fixed: Long Fixed: Floating: Decimal: Convert the specified number at top of 0S into a long fixed point number. Flags: F' 0-1 F (Executed in the TP) F' = ^ 2-3 Indicators N0P Flags: F' None 0-3 0-3 Fi are lost Indicators: 0V Same as above Indicators: 0V, ID 8/25/69 Section 1.5.8 - 1/1 1.5.9 Polynomial Evaluation POLY 1 O il 1 N T The polynomial of the form n n-1 a X + a -.x + n n-l ax + a is evaluated. To specify the polynomial, the coefficients a^ through a are pushed into the 0S in that order. The value of x is then pushed in followed by the degree n, a short fixed point number. Before POLY 3- £■ n-l After POLY Ans *Fixed: Floating: ♦Decimal: Flags: F(Result) *- F(X) Indicators: ^Y, Indicators: 0V, UN, LS Indicators: 0V, LS, ID ?/2$/69 Section 1.5-9 - 1/1 1 . 6 Exceptional Conditions for Arithmetic Instructions 1.6.1 General When a computational condition such as an overflow occurs in an arithmetic \init , this information must be returned to the taxicrinic processor. As with comparison operations (Section 1.5.2), the flags of a result are used to return this condition information, and to set indicator | flipflops which may be tested with subsequent instructions. The bogus result produced is returned to the Taxicrinic Processor, not as a copy of the flags of an operand, but rather as an indication of the condition which has occurred. The fact that an error has occurred is included with the Exchange Net trans- mission in the control byte. The bogus result with the appropriate computational condition flag(s) set is pushed into the 0S as if it were a correct result. An interrupt then takes place ex:cept for an overflow tor fixed point multiply. (See Sec. 1.5.3 - 1 For the reader familiar with PL/I, Table 1.6.1.2 describes the analogy between the computational conditions of PL/I* and those implemented in the hardware of Illiac III. Although there is not a one-to-one correspond- ence between the two versions, both yield approximately the same information if the instruction and nvimber type are known. The following parts in this section describe the Illiac III computa- tional condition indicators and illustrate the disposition of bogus results. The assignment of computational condition flags is illustrated for the various number types in Figure 1.6.1.1. The comparison indicator flags (Section 1.5) are also shown for the sake of completeness. *"IBM Operating System/ 360, PL/I - Language Specifications," File No. S360-29, Form C28-6571-U, p. l62. 9/18/69 Section 1.6.1 - 1/3 LS UN 0V 10 GT EQ LT FM bd Nl M N N M M bd LS M ^y ID GT EQ LT ^ N N M N 1^ M 0V ID T^ M M l>^l 0V ID SIZE ^ = Flag of Byte (Bit #9) * = Not Used in this Number Type Figure 1.6.1.1 Flag Bit Designation for Arithmetic Indicators >/l8/69 Section 1.6.1 - 2/3 Table 1.6.1.2 Correspondence between Computational Conditions of PL/I and Those of Illiac III ILLIAC III PL/ 1 Instruction Variant Number Type Computational Condition Indicator CONVERSION CVF or CVL Decimal Invalid Decimal Data CVD or CVL Floating Overflow CVL Decimal Overflow FIXEDOVERFLOW ADD, MPY, SUB, ABS, DIV, POLY Long or Short Fixed or Decimal Overflow OVERFLOW ADD, SUB, Floating Overflow MPY, DIV, POLY, SIZE No hardware imple- mentation. UNDERFLOW ADD, SUB, MPY DIV, POLY Floating Underflow ZERODIVIDE DIV Any Overflow 9/18/69 Section 1.6.1 - 3/3 1.6.2 - OVERFLOW (OV) Table 1.6.2.1 - OVERFLOW (OV) ORDER IN WHICH CONDITION MAY OCCUR DESCRIPTION OF CONDITION RESULT IN STACK ADD, SUB S. Fixed (also in CPRA) Magnitude of result exceeds (2''"^-l). Low order 16 bits of the result. L. Fixed (also in CPRA) Magnitude of result exceeds (2^-^-1). Low order 32 bits of the result. Floating The exponent of the normalized result exceeds 63 and the result frac- tion is not zero. Fraction is that computed and correctly normalized. Sign of fraction is cor- rect. Exponent = -t63. Decimal Magnitude of result exceeds 99999999999999 (lU, 9's). Low order ik digits of the result. MPY, POLY 1 S. Fixed Magnitude of result exceeds (2''"^-l). Full-word correct result with OV flag set. '/18/69 Section 1.6.2 - 1/3 Table 1.6.2.1 - Overflow (OV) (Continued) Order in Which Condition May Occur Description of Condition Resiilt in Stack L, Fixed Magnitude of result 31 exceeds (2 -l). Double word (integer) correct result with OV flag set. Floating The exponent of the normalized result exceeds 63 and the result fraction is not zero. Fraction is that com- puted and correctly normalized. Sign of fraction is correct. Exponent = -+63. Decimal Magnitude of result exceeds ik, 9's. Low order lU digits of the result. DIV S. Fixed L. Fixed Division by zero. Largest number represen- table . Sign of result is sign of dividend. Re- mainder is 0. Floating Division by zero. ■ Fraction and exponent are all I's. Sign of frac- tion is the sign of the dividend. Decimal Division by zero. Largest number representable. 9/18/69 Section 1.6.2 - 2/3 Table 1.6.2.1 - Overflow (OV) (Continued) Order in Which Condition May Occur Description of Condition Result in Stack ABS, NEG S. Fixed Attempt to negate the most negative number representable. The integer +1. CVD Floating The magnitude of the converted number ex- ceeds the range of the new number type . Result is the converted * number with missing high order digits which have overflowed. CVL Floating Decimal The magnitude of the converted number ex- ceeds the range of the new number type . Result is the converted number with missing high order bits which have overflowed. * This is true only if Exponent of Floating Operand is £ lU. Otherwise "double" overflow occurs and error is compounded. 9/18/69 Section 1.6.2 - 3/3 1.6.3 Underflow (ITO) Table 1.6.3.1 - UNDERFLOW (UN) ORDER IN WHICH DESCRIPTION RESULT IN CONDITION MAY OCCUR OF CONDITION STACK ADD The exponent of the Fraction is that com- SUB MPY normalized result is less than -6U and the puted and correctly- normalized. Sign of DIV result fraction is fraction is correct. POLY not zero. Exponent is -6U. Floating Only 9/18/69 Section 1.6.3 - l/l 1.6.U Invalid Decimal Data (ID) Table I.6.I1.I - INVALID DECIMAL DATA (ID) ORDER IN WHICH DESCRIPTION RESULT IN CONDITION MAY OCCUR OF CONDITION STACK Any Decimal Order A sign or digit code Result is the contents of Except NEG, ABS, of an operand is the AU accumulator when MNS, TA. incorrect . the decoding error was detected. No ID check is made for unary operations except CVF and CVL. 9/18/69 Section 1.6.U - l/l 1.6.5 Loss of Significance (LS) Table 1.6.5.1 - LOSS OF SIGNIFICANCE (LS) ORDER IN WHICH DESCRIPTION RESULT IN CONDITION MAY OCCUR OF CONDITION STACK ADD Fraction of result is True zero with LS SUB 0. Exponent of result flag set. POLY / -6k. For example- Floating Only when two equal numbers are subtracted. 9/18/69 Section 1.6.5 - l/l 2. INTERNAL STATIC DESCRIPTION 2.1 General 2.1.1 Overall Block Diagram Figvire 2.1.1.1 is a block diagram of an Illiac III arithmetic vmit. The conventions used in this figure eire as follows: 1) Functional sub-hlocks are denoted by rectangles. Inside each box is the name of the block followed by a list of the names of signals which control it. 2) The lines between boxes denote data buses. 3) Selector signal names are of the form F X T, where F is the name of the register from which the data is transferred. X = D if the transfer is direct , i.e. without shifting. X = R if the data is shifted n places to the right during the transfer. X = L if the data is shifted n places to the left n ^ during the transfer. T = the name of the register to_ which data is transferred. h) A register name standing alone, for example, UQ, denotes the true output of all positions of the register. A subsection of a register is specified in the following form: np, where n is the number of the first byte (8 bits per byte) of the subsection and p is the number of the last byte of the sub- section. Byte numbering is through 7* Example: VDUHUT means V-BUS Direct to UH-Register, bytes k through "J. 5) If R denotes the name of a register, then RSEL denotes the output of the associated input selector. 8/25/69 Section 2.1.1 - I/5 6) If R denotes the name of a register, then LDR denotes the signal which loads the output of the associated select into the register flip-flops. 7) All selectors, registers, subtracters and shift gates are 6k bits (8 bytes) vide, except for the M-Register which is 56 bits wide. I I 8/25/69 Section 2.1.1 - 2/5 IS in O in c 5S 0(/l 1- 2 OJ 3 tr o LU > -1- -LU ^ CKi^ < X rr UJ|- §5 o < O < Q U. — ^ o o o < _J _l CD _J ^^ 3 < S 3 3 O O c tn -i _- 2 -1 -J Ul V) 2 irti" 3 s = 5 -1 ,_ QJ K) ^^5 2 Ml -1 2 v> 2 2 (M 3 O 3 O -1 _l its 2 I K K o w UJ UJ "2 1- 1- 5 = : /^SELECT UO DIRECT TO UM, BYTES 3-5*/ PROCEDURE; SUBSTR(UMSEL,2b,24)=SUBSTR(U0,2 5,24) ; END; U0nUM67: /^SELECT UO DIRECT TO UM, BYTES 6,7*/ PROCEDURE; SUBSTR(UMSEL,49,16)=SUBSTR(U0,49,16); END; I 9/29/69 Section 2.2.3.3 - 2/2 2.2.U LS-Register 2.2. U.l General The LS-Register (Lower S^ign Register) is part of the secondfiLry rank of the acciimulator for the signed-digit subtracter (SDS) array. It holds the sign bits of the result from the SDS output prior to their being transferred back to the primary sign bit accumulator (US-Register) or the UH-Register for terminal processing. The LS-Register consists of 8 bytes of flip-flop storage. Since this register is loaded from only one source (the T output of subtracter h) no selector gates such as used with the US-Register are necessary. The input is selected and loaded \inder control of the signal Tl+DLS. The output of the LS-Register drives inputs into the US- selector (LSL8US, LSDUS, LSRBUS) and an input into the UH Selector (LSDUH; 8/26/69 Section 2. 2. U.l - l/l 1 2.2.U.2 Implementation The LS-Register is implemented with the 26O-OO flip-flop board. A typical position is shown in Figure 2.2.i+.2.1. Relevant detailed drawings are as follows: 22^-01, -02, -03, -OI+, -05, -06. 8/26/69 Section 2.2.U.2 - 1/2 EXTERNAL CONNECTION T4i V^ LSi T4i \J LSi 260-00 (8 PER CARD) TO: FIG. 2.2.2.2.1 (3 LOADS) FIG. 2.2.6.2.1 ( 1 LOAD) Figure 2. 2. U. 2.1 - Typical Position of the LS Register 8/26/69 Section 2.2.1|.2 - 2/2 2.2.U.3 PL/1 Description of Signal Names /-PL/1 DESCRIPTIUN GF SIGNAL NAM ES RELEVA NT TO LS KeOISTER*/ /-RELEVANT DRAWING NUMBERS: 22^-01 ,-02 , -03 , -04 »'-0b, -06 ."*/ DECLARE LS B I T ( 64 ) ; /*TRUE OUTPUT UF LS REGISTER*/ DECLARE T4 BIT(64); /*TRUE OUTPUT OF SDS-4, SIGN BITS=:V T4DLS: /*T4 DIRECT TO LS (SAME AS LOAD LS), ALL BYTES*/ PROCEDURE; _ CALL T4DLS01; CALL T40LS23; CALL T40LS45; CALL T4DLS67; END; l4nLS01: /*T4 DIRECT TO LS, BYTES 0,1 */ PROCEDURE; SUBSTR(LS,1,16)=SUBSTR(T4, 1, 16) ; END; ■140LS23: /*T4 DIRECT TO LS , 'BYTES 2 , 3" */ PROCEDURE; SUBSTR(LS,17,16)=SUBSTR(T4,17,16) ; END; 14DLS45: /*T4 DIRECT TO LS, BYTES 4,5 */ PROCEDURE; SUBSTR(LS,33,16)=SUBSTR1T4,33, 16)"; END; T40LS67: /*T4 DIRECT TO LS, BYTES 6,7 */ PROCEDURE; SUBS1R(LS,49,16)=SUBSTR|T4,33,16) ; END; 9/29/69 Section 2.2.U.3 - l/l 2.2.5 LM-Register 2.2.5-1 General The LM-Register (Lower Magnitude Register) is peirt of the secondary rank of the acciunulator for the signed digit subtracter (SDS) array. The register holds the magnitude bits of the result from the SDS output prior to their being transferred back to the primary magnitude bit accumulator ( UM-Register ) or to the UQ Register which serves as an output buffer. The LM-Register consists of 8 bytes of flip-flop storage. Since this register is loaded from only one source (the Z output of subtractor h) no selector gates such as used with the UM-Register are necessary. The input is selected and loaded iinder control of the signal ZUdLS. The output of the LM-Register drives inputs into the UM-Selec- tor (LML8UM, LMDUM, LMR8UM) and an input into the UQ-Selector (LMDUQ). 8/26/69 Section 2.2.5.1 - l/l 2.2. 5.2 Implementation The LM-Register is implemented with the 260-00 flip-flop "boaxd. A typical position is shown in Figure 2. 2. 5 .2.1. Relevant detailed drawings are as follows: 225-01, -02, -03, -OU, -05, -06. 8/26/69 Section 2.2.5-2 - 1/2 Z4DLM EXTERNAL CONNECTION Z4i Z4i LM; LM: 260-00 (8 PER CARD) TO: FIG. 2.2.3.2.1 (3 LOADS) FIG. 2.2.7.2.1 (L LOAD) Figure 2.2.5.2.1 - Typical Position of the LM Eegister 8/26/69 Section 2.2.5-2 - 2/2 P 2.5.3 PL/1 Description of Signal Names /-PL/1 DESCRIPTIUN UF SIGNAL NAMES RELEVANT TO LM KEGISTbR «/ /-RELEVANT DRAWING NUMBER S : 22 5-0 1 ,-02 , -03 , -04, -05 » -06 */ DECLARE LM Brr(64); /*TRUE OUTPUT UF LM KEGISTER */ DECLARE lA BIT(64); /*TRUE OUTPUT OF SDS-4, MAGNITUDE BITS*/ Z4DLM: /*Z4 DIRECT TO LM (SAME AS LOAD LM), ALL BYTES*/ PROCEDURE; CALL Z4SLM01D CALL Z4DLM23; CALL Z4DLM4b; CAlI ZADLM67; END; Z^DLMOl: /*Z4 DIRECT TO LM, BYTES 0,1*/ PROCEDURE; SUBSTR{LM,1,16)=SUBSTR(Z4,1,16) ; END; ZADLM23: /*ZA DIRECT TO LM, BYTES' 2,3*/ PROCEDURE; SUBSTR(LM,17,16)=SUBSTR(Z4,17,16) ; END; Z4DLM4b: /*Z4 DIRECT TO LM, BYTES 4,5*/ PROCEDURE; _ SUBSTR(LM,33,16)=SUBSTR(Z4, 33, 16) ; END; Z4DLM67: /*Z4 DIRECT TO LM, BYTES 6,7*/ PROCEDURE; SUBSTR(LM,49,16)=SUBSTR(Z4,49,16) ; END; 9/29/69 Section 2.2.5»3 - l/l 2.2.6 UH-Register 2.2.6.1 General The UH-Register (Upper H Register) is part of a functional set of registers consisting of UH and UQ and the secondary ranks LH and LQ. These 8-byte registers serve as input-output buffers, as shift registers for initial and terminal operations of an arithmetic order^ and as storage for the sign bits of the quotient (in signed-digit format) during division. The UH-Register complex consists of input selectors and flip-flop storage. The inputs to the register supplied by the selector and their primary use are described below: Signal Name LSDUH LHLIUH LHlAUH LHL8UH mL32UH LHR4UH Description Select true outputs of LS-Register direct (i.e. without shifting). Select true outputs of LH-Register shifted left 1 bit. Select true outputs of LH-Register shifted left k bits. Select true outputs of LH- Register shifted left 8 bits (1 byte) Select true outputs of LM- Register shifted left 32 bits {k bytes) . Select true outputs of LH- Register shifted right h bits. Primary Use In conversion from integer to decimal number type. Binary normalization for division. Hexadecimal normalization in all floating point operations Hexadecimal normalization in all floating point operations In fixed point division. To align radix points of fractions for floating point ADD and SUB. 8/26/69 Section 2.2.6.1 - 1/2 Signal Name LHB8UH VDUHO VDUH13 VDUHi+T QBDUH7 Description Select true outputs of LH-Begister shifted right 8 tits. Select V-Bus data byte 1 direct to UH byte 0. Select V-Bus data bytes 2-U direct to UH bytes 1-3. Select V-Bus data bytes 1-U direct to UH bytes Select the quotient buffer from model division to UH, byte 7. Primary Use To align radix points of fractions for floating point ADD and SUB. Initial loading of operands, i Initial loading of operands, Initial loading of operands. All division operations The outputs of the selector, UHSEL. (i = 1 to 64), are loaded into the UH flip-flops under control of LDUH (Load UH) . These signals and their sub-signals are defined more precisely in PL/1 in Section 2.2.6.3. The outputs of the UH flip-flops drive the LH register, the US Selector (UHDUS), the M Selector (UHDM) , and the UH Zero Detect logic. 8/26/69 Section 2.2.6.1 - 2/2 2.2.6.2 Implementation The UH Selector is implemented with the 29^-00 selector card and the 228-03 NMD card. The flip-flops are 260-00. A typical position of the UH Register and Selector is shown in Figure 2.2.6.2.1. Relevant detailed drawings are as follows: 226-01, 02, -03, -OU, -05, -06, -07. 8/26/69 Section 2.2.6.2 - 1/2 LHLIUH LML32UH LSDUH LHL8UH LHL4UH VDUH LHR4UH LHR8UH LDUH LH LH V i-8 i-4 LH LH LS. i+4 i+8 I Ky v^ \y LM LH i + 32 — •■ 228 228 i-i-l 294-00 (8 PER CARD) ^^ 294-00 (8 PER CARD) uhselSt UHSEL: 260-00 (8 PER CARD) V n.c, FOR i= 1,2, ... ,64 Typical Position of the UH Register and Selectors 8/18/69 Section 2.2.6.2 - 2/2 2.2.6.3 PL/1 Description of Signal Names L/1 OPSCRIPIIDN OF SIGNAL NAMES RELFVANT TO UH KEGISTFK*/ ELEVANT DRAWING NDMHFKS: 22 )-0 1 f-02 , -03 , -OA, -Ob , -06 , -07*/ DFCLARE UH B I T ( 6A ) ; /*TRUE OUTPUT OF UH REGISTER*/ DECLARE UHSEL BIT 16^); /*TRUE UUTPUT OF UH SELECTOR*/ h: PROCEDURE; CALL LDUHOl; CALL LDUH23; CALL LDUHA5; C ALL JjpUHbli END; HO 3: PROCEDURE; CALL LDUHOl; CALL LDUH23; END; H47: PROCEDURE; CALL LUUH^b; CALL LDUH67; END; HOI /*LOAU UH BYTES 0,1 FROM UHSEL BYTES 0,1 */ PROCEDURE; SUBSTR(UH, 1, 16 )=SUBSTR( UHSEL, 1,16) ; END; H23: /*H>AD UH BYTES 2,3 FROM UHSEj. BYTES 2,3 */ PROCEDURE; SUBSTR(UH,17,16)=SUBSTR(UHSEL,17,16); END; H45: /*LL)AO UH BYTES 4,5 FROM UHSEL BYTES 4,b */ PROCEDURE; SUBSTR(UH,33, 1 6 ) = SUBS TR ( UHS EL ?_33 , 16) ; END; H67: /*LUAD UH BYlES 6,7 FROM UHSEL BYTES 6,7 */ PROCEDURE; SUBSTR(UH,49, 1 6 ) = SUBSTR ( UHS EL , 49, 16) ; END; /*SELECT LH LEFT 1 BIT TO UH*/ PROCEDURE; CALL LHL1UH14; CALL LHL1UH57; END; /*SELECT LH LEFT 1 BIT TO UH BYTES 1-4*/ PROCEDURE ; SUBSTR(UHSEL,9,32) = SUBSTR(LH, 10,32 ) ; END; /*SELECT LH LEFT 1 BIT TO UH BYTES b-7*/ PROCEDURE; SUBSTR(UHSEL,41,24) = SUBSTR(LH,42,23) | | 'O'B; END; /*SELECT LH LEFT 4 BITS TO U H, ALL BY TES*/ PROCEDURE; CALL LHL4UH03; CALL LHL4UH47; END; •UH03: /^SELECT LH LEFT 4 BITS TO UH, BYTES 0-3*/ PROCEDURE ; SUBSTR(UHSEL, 1 , 32 ) = SURSTK ( LH, 5, 32 ) ; END; IUH47: /--SELECT LH LEFT 4 BITS TO UH, BYTES 4-7*/ PROCEDURE; SUBSTR(UHSEL,3 3,32 )=SUBSTR(LH,37,28) I I 'OOOO'B; END; UH: /*SELECT LH LEF'L R BITS TO UH , ALL BYTE S*/ PROCEDURE; CALL LHL8UH03; CALL LHL8UH47; ,UHt>7 ►UH: 9/29/69 Section 2.2.6.3 - 1/3 END; LHLRUH03: /^SELECT LH LEFT 8 BITS TO UH, BYTES 0-3*/ PROCEDURE; SUBSTR(UHSEL,l,32)=SUBSTR(LHt9,32 ) ; END; LHLaUH47: /^SELECT LH LEFT 8 BITS TO UH, BYTES 4-7*/ PROCEDURE; SUBSTR(UHSEL,33,32) = SUBSTR(LHt41t24) I r8'0'B; END; LHR4UH; /^SELECT LH RIGHT 4 BITS TO UH, ALL BYTES*/ PROCEDURE; CALL LHR4UH03; CALL LHR4UH47; END; LHR4UH03: /*SELECT LH RIGHT 4 BITS TO OH, BYTES 0-3*/ PROCEDURE; SUBSTR(UHSEL,1,32)='0000«B| | SUBSTR ( LH, 1 , 28 ) ; END; LHR4UH47; /*SELECT LH RIGHT 4 BITS TO UH, BYTES 4-7*/; PROCEDURE; _ SUBSTR(UHSEL,33,32)=SUBSTR(LH,29, 32); END; LHRRUH: /*SELECT LH RIGHT 8 BITS TO UH, ALL BYTES*/ PROCEDURE; CALL LHR8UH03; CALL LHR8UH47; END; LHR8UH03: /*SELECT LH RIGHT 8 BITS TO UH, BYTES 0-3*/ PROCEDURE; SUBSTR(UHSEL,1,32)=(8) 'O'BI | SUBSTR ( LH, 1 , 24 ) ; END; LHR8UH47: /*SELECT LH RIGHT 8 BITS TO UH, BYTES 4-7*/ SUBSTR(UHSEL,33,32)=SUBSTR(LH,2 5,32); END; LML32UH: /*SELECT LM LEFT 32 BITS INTO UH (SAME AS LMDUH7)*/ PROCEDURE; SUBSTR(UHSEL,1,32)=SUBSTR(LM,33,32); END; LSDUH; /*SELECT LS direct to UH, ALL BYTES*/ PROCEDURE; CALL LSDUH03; CALL LSDUH47; END; LSDUH03: /*SELECT LS DIRECT TO UH, BYTES 0-3*/ PROCEDURE; SUBSTR ( UHSEL , 1 , 32 ) = SUBSTR ( L S , 1 , 32 ) ; END; LSDUH47: /*SELECT LS DIRECT TO UH, BYTES 4-7*/ PROCEDURE; SUBSTR(UHSEL,33,32)=SUBSTR(LS,33,32); END; VDUHO: /*SELECT V-BUS DATA BYTE 1 DIRECT TO UH B YTE */ PROCEDURE; SUBSTR (UHSEL , 1 ,8 ) =SUBSTR ( V , 1 1 , 8 ) ; END; VDUHI3: /*SELECT V-BUS DATA BYTES 2-4 DIRECT TO UH BYTES 1-3*/ PROCEDURE; SUBSTR(UHSEL,9,8)= SUB S TR( V ,21 ,8) ; SUBSTR I UHSEL, 1 7 , 8 ) = SUBSTR ( V , 31 , 8 ) ; SUBSTR (UHSEL,?'),8) = SUBSTR( V,41 ,8) ; 9/29/69 Section 2.2.6.3 - 2/3 UH47: DATA BYTES l-<* DIRECT TO UH BYTES 4-7*/ /♦SELECT V-BUS PROCEDURE: SUBSTR(UHSEL,33,H)=SUBSTK( V» 11,8) SUBSTR(UHSEL,41 , 8 ) = SUBS TR ( V , 2 1 » 8 ) SUBSTR(UHSEL,49,8)=SUBSTR( V,31 ,8) SUBS TR(UHSE L , 5 7 , 8 ) = SUBSTR ( V, 41, 8 ) END; 9/29/69 Section 2.2.6.3 - 3/3 2.2.7 UQ-Register 2.2.7.1 General The UQ-Register (Upper Q Register) is part of a functional set of registers consisting of UH and UQ and the secondary ranks LH and LQ, respec- tively. This 8-byte register serves as an input-output buffer, as a shift register for initial and terminal operations of an arithmetic order and as storage for the magnitude bits of the quotient (in signed-digit format) during division. The UQ-Register complex consists of input selectors and flip-flop storage. The inputs to the register and their primary use are described below: Signal Name LMDUQ LQLIUQ lqlUuq LQL8UQ LQR1UQ03 LQRi+UQ LQR8UQ Description Select true output of LM- Register directly (without shifting) Select true output of LQ- Register shifted left 1 bit. Select true output of LQ- Register shifted left k bits. Select true output of LQ- Register shifted left 8 bits. Select true output of LQ- Register shifted right 1 bit. Applies only to bytes 0-3. Select true output of LQ- Register shifted right k bits, Select true output of LQ- Register shifted right 8 bits, Primary Use Transfer of results for signe digit subtracter complex to U for terminal shifting and out Binary normalization for divi Hexadecimal normalization in : floating point operations. Hexadecimal normalization in ; floating point operations. Post normalization of remaindt in integer division. Alignment of radix points of fractions for floating point ADD and SUB. Alignment of radix point of fractions for floating point ADD and SUB. 8/26/69 . Section 2.2.7.1 - 1/2 Signal Name SELDECSIGN SETUQ030NE VDUQO VDUQ13 vduqUt Description Select the sign of a decimal result into UQ(5) - UQ(8) Set UQ(1) - UQ(32) to all I's. Select V-Bus data byte 1 direct to UQ byte 0. Select V-Bus data bytes 2-J+ direct to UQ bytes 1-3. Select V-Bus data bytes l-ii direct to UQ bytes U-J . Primary Use Conversion to decimal number type. Generation of maximum floating point number on division by zero. Initial loading of operands. Initial loading of operands. Initial loading of operands. The outputs of the UQ selector, UQSELi (i = 1 to 6U) are loaded into the UQ flip-flops under control of LDUQ (Load UQ) . All signals associated with the UQ-Register are defined more precisely in PL/1 notation in Section 2.2.7' 3. The outputs of the UQ flip-flops drive the LQ register, the UM selector, the UQ Zero Detect Logic and the XT-Bus interface. 8/26/69 Section 2.2.7-1 - 2/2 2.2.7.2 Implementation The UQ Selector is implemented with the 29^-00 selector card and the 228-03 NMD card. The flip-flops are the 260-00. A typical position of the high order half of the UH Register and Selector is shown in Figure 2. 2.7 .2.1. A typical position of the low-order half is shown in Figure 2.2.7-2.2. Relevant detailed drawings are as follows: 227-01, 02, 03, 0^+ , 05, 06, 07. 8/27/69 Section 2.2-7.2 - 1/3 LQ LQ Q(2I30NE LOLIUQ LQRIUQ LMDUQ LQL8UQ LQL4UQ VDUQ .QR4UQ LQR8UQ LDUQ 260-00 (8 PER CARD) FOR i= 1,2, ... ,32 n.c. = no connection Figure 2.2.7.2.1 - Typical Position of UQ Register and Selector (Bytes 0-3) i| a/18/69 Section 2.2.7-2 - 2/3 LQ LQ V i-8 i-4 LQLIUQ LMDUQ LQL8UQ LQL4UQ VDUQ LQR4UQ LQR8UQ \y LQ LQ LM. i+4 i + 8 • LQ \y 294-00 (8 PER CARD) i + l V ■ 228-14 (16 PER CARD 294-00 (8 PER CARD) uqselSt LDUQ KJ UQSEL V n.c. Kj 260-00 (8 PER CARD) FOR i= 33,34 64 n.c. = no connection UQ UQ Figure 2.2.7.2.2 - Typical Position of UQ Register and Selector (Bytes I4-7) 8/I8/69 Section 2.2.7-2 - 3/3 2.2.7.3 PL/1 Description of Signal Names /vPL/1 DFSCRIPllUN Uh S1(;NAL NAMtS RELeVANT llj U(0 KbGISlbK*/ /*RFLEVANT 1)RAWIN(, NUMBERS: 2 27-0 1 , -02 ,-03 ♦ -04 , -Ob , -06, -07* / DECLARE UQ rtIT(64); /*TRUE OUTPUT OF UO REGISTER*/ DECLARE UOSEL B I T ( 64 ) ; /=<=TRUE UUTPUT UF UO SEL EC 1 ()R':=/ DECLARE TEMP_S B1TI4), TEMP1_S BITIH), I N J EC TS I r,N_S BIT(4), INJFCTSIGN1_S BIT{H); INJECTS IGN:/*INJECI SIGN IN HIGH ORDER POSITIONS Oh UO UN RIGHT SHIFTS */ PROCEDORE ; INJECTSIGN_S = (4)«1'B; I NJ ECTS I GN1_S = (H)«I'B; END; LDUO: PROCEDURE; CALL LDUOO; CALL LDUQl; CALL LUU023; CALL L0U045: CALL L0U067; END; LDU0I3: PROCEDURE; CALL LDUOl: CALL LDU023; END; Ll)U047: PROCEDURE; CALL LDU045; CALL LDU067; END; LiniOO: /«LGAD UO BYTE FROM UOSEL BYTE «/ PROCEDURE; SOBSTR(UOt 1,8)=SUBSTR(UQSEL,1,H ) ; END; LUUOI: /=^LL)AD UO BYTE I FROM UOSEL BYTE I */ PROCEDURE ; SUBSTR(U0,9,8) = SUBS TR ( UOSEL , 9, F ) ; END: LDU023: /«LOAD UO BYTES 2t3 FROM UOSEL BYTES 2,3 */ PROCEDURE; SUBSTR(UOt 17, 16) = SUBSTR"(U0SEL,17t 16) ; END; LDU045: /*LOAD UO BYTES 4,b FROM UOSEL BYTES 4,5 */ PROCEDURE: SUBSTR(U0,33, 1 6 ) =SUBSTR ( UQSEL, 33 , 16) ; END; LI)U067: /«LOAD UO BYTES 6,7 FROM UOSEI BYTES 6,7 */ PROCEDURE; SUBSTR(U0,49, 16) = SUBSTR(U0SEL,49, 16) ; END; LMOUO: /^SELECT LM DIRECT TO UO, ALL BYTES-/ PROCEDURE; „ _ _ _ CALL LMDU003; CALL " LMDU047'; ' END; LMnu003: /*SFLECT LM DIRECT TO UO, BYTES 0-3*/ PROCEDURE; SUBSTRIUOSEL, 1 ,32)=SUBSTR(LM, 1,32 ) ; END; LM0U047: /^SELECT LM DIRECT TO UO , BYTES 4-7*/ PROCEDURE; SUBSTR(UOSEL,33,32)=SU8STR(LM,33,32); END; .OLIUO: /^SELECT LO LEFT 1 BIT TO UH«/ PROCEDURE; CALL LOL1U004; CALL L0L1U057; END; 9/29/69 Section 2.2.7-3 - 1/3 L(OL1U004: /*SrLECT LO LEFT 1 B I T JT)^ U^O,^ BYTES 0-4*/ PROCEDURE; SUBSTRIUOSELt 1 t 40 ) = SUBS TR ( LO, 2 , 40 ) ; END; L(OL1U057: /^=SELECT LO LEFT 1 BIT TO UO, BYTES 5-7-/ PROCEDURE; SUBSTR(U0SELt^1t24) = SUBSTR(LPj42,23) | | 'O'B; END; L0L4U0: /=i=SELECT LO LEFT 4 BITS TO UO, ALL BYTES*/ PROCEDURE; CALL LOL4U003: CALL L0L4U047; END; LOL4U003: /^SELECT LO LEFT 4 BITS JOJJO, BYTES 0-3j:i/ PROCEDURE; SUBSTR(U0SEL,1,32)=SUBSTR{L0,5,32) ; END; LOL4U047: /''^SELECT LO LEFT 4 BITS TO UO, BYTES 4-7*/ PROCEDURE; SUBSTR(U0SEL,33,32) = SyBSTR(L0,37,28) | (NiEPB; END; L0L8U0: /=: