LIBRARY OF THE UNIVERSITY OF ILLINOIS AT URBANA-OHAMPAICN btO.%4 top. a The person charging this material is re- sponsible for its return to the library from which it was withdrawn on or before the Latest Date stamped below. Theft, mutilation, and underlining of books are reasons for disciplinary action and may result in dismissal from the University. To renew call Telephone Center, 333-8400 UNIVERSITY OF ILLINOIS LIBRARY AT URBANA-CHAMPAIGN 1 Q I98) f£C 10 IP L161— O-1096 Digitized by the Internet Archive in 2013 http://archive.org/details/sabumasafebundle412coom (4, , REPORT NO. 1+12 />i^Lij C^p %> SABUMA - SAFE BUNDLE MACHINE by DANIEL COOMBES August, L970 IHE UBRARY OF THE SEP 2 1 1970 UNIVERSITY OF ILLINOIS AT UR^ANA-CHAMPAIGN REPORT NO. 412 SABUMA - SAFE BUNDLE MACHINE* by DANIEL COOMBES August, 1970 Department of Computer Science University of Illinois Urbana, Illinois 61601 ^Supported in part by Contract Number N000 14-67-A-0305-0007 and submitted in partial fulfillment of the requirements for the degree of Master of Science in Electrical Engineering at the University of Illinois, Urbana, Illinois, August, 1970. Ill ACKNOWLEDGEMENT The author wishes to thank Professor W. J. Poppelbaum for his original suggestion for this thesis topic and for his continued support and guidance. In addition, he would like to thank Assistant Professor W. J. Kubitz for reading and correcting the content of this thesis, Miss Car la Donaldson for the typing, and all the members of the fabrication group under Mr. Frank Serio for their individual efforts. IV TABLE OF CONTENTS Page 1. INTRODUCTION 1 2. FAILSAFE BUNDLE PROCESSING . 2 2.1 General 2 2.2 Binary Logic Gate Operations k 2.2.1 AND Gates k 2.2.2 NOT Gates 5 2.3 Two Level Mappings 5 2.3.1 General 5 2.3.2 The Mapping: t = 2W - 1 6 2.3.3 The Mapping: t=l-2W 8 W 2.3.^ The Mapping: t = C n (77=) - C_ 9 1 Wp 2 2.k Threshold Logic for Ternary Systems 11 2.U.1 General U 2.U.2 Threshold Operators 11 2.^.3 Diametrical Negation 11 2.5 Three Level Mappings 12 2.5.1 General 12 2.5-2 The Failsafe Mapping: t = W 12 2.5.3 Ternary Bundle Multiplication 13 2.6 Failsafe Operations 15 2.6.1 Multiplication 15 2.6.2 Division 15 2.6.3 Addition 16 2.6. h Subtraction j£ V Page 3. ATTRITION PROBLEM l8 3.1 General 18 3.2 Useful Solution 18 k. SABUMA - SAFE BUNDLE MACHINE 20 k.l General 20 k.2 Analog to Bundle Converter 20 U.2.1 General 20 U.2.2 Analog Inputs 20 k.2. 3 Rough Input Approximation 23 k.2.k Comparator Reference Voltages 23 U.2.5 Fifty Wire Driver 27 k.2. 6 Five Wire Driver 27 ^+.2.7 Fine Input Approximation 27 U.2.8 One Wire Driver 32 U.2.9 Numbers Greater Than One 32 k.3 Arithmetic Unit 32 U.3.1 General 32 U.3.2 Multiplier 3)+ k.k Decoder 36 k.3 Circuit Failures 38 5. CONCLUSION 1+0 LIST OF REFERENCES kl vi LIST OF FIGURES Figure Page 1. SABUMA System Design 21 2. Analog to Bundle Converter 22 3. Analog Input Voltage Circuit 2k k. Course Voltage Decoder Circuit 25 5. Voltage and Sign Control Circuit 26 6. Fifty Wire Driver Circuit 28 7. Five Wire Driver Circuit 29 8. Difference Circuit "with Fine Voltage Decoder 30 9- One Wire Driver Circuit 33 10. Multiplier Circuit 35 11. Complete Analog Display Circuit 37 12. Error Detection Circuit 39 1. INTRODUCTION Under the direction of Professor W. J. Poppelbaum, a system was investigated whose purpose was to realize the four basic operations of arithmetic in a failsafe manner. Using this system, called Failsafe Bundle Processing, a number is represented on a group of wires, and its magnitude is determined by the difference of wires at one level from those at another level. The advantages of such a system over conventional processing methods are speed and reliability. Very fast arithmetic operations which are independent of physical or electromagnetic intrusions are possible by operating on all of the wires in parallel. A discussion of the various failsafe mappings investigated and a system design for one of these mappings follows. 2. FAILSAFE BUNDLE PROCESSING 2.1 General Failsafe Bundle Processing was developed to represent a number on a group of wires in a failsafe fashion. These failsafe number representations are used in the operations of addition, subtraction, multiplication, and division with the resulting outputs being failsafe also. The wires in the group are set to some fixed arbitrary voltage, plus or minus V or GND, with the magnitude of the number being determined by the difference of wires at plus V from those at minus V. The operation of division in Failsafe Bundle Processing dictated the use of a numerator and a denominator group of wires to represent numbers in machine form. The group of denominator wires makes possible the representation of a much larger range of numbers than is possible with just one group of wires. The denominator group is used to produce failsafe machine number representations To facilitate further discussion a number of variables will be defined at this time. The logic states 1, ON, and + are synonymous and have the numerical value plus one. The logic states and MAYBE are synonymous and have the numerical value zero. The logic states -1, OFF, and - are synonymous and have the numerical value negative one. The variables x, y, z represent the number of wires in the logic states +, 0, and - respectively. Where x+y+z=N, N being equal to the total number of wires in a group. A number in machine form (W) is defined by the equation W=2L T^ (2.1) for either binary or ternary logic. Since W is determined only by the ratio — ^ — , it is independent of which particular wires are ON or OFF in the group. The possibility of having either a most significant or least significant wire does not exist since all wires have the same significance. With all wires being equally important, a group can be randomly separated into smaller groups (h) of arbitrary size with each group having the same value as the original. If a group of wires is randomly separated into two halves then x and z will be halved. W is now defined by the equation x z 2 The value of W for equation 2.2 is the same as that for equation 2.1. The term bundle, a basic unit of wires, will be substituted for group since the number of wires becomes significant only when the accuracy of a number (h) xv z representation is considered. The fractions — , *:, and — will be represented by X, Y, and Z respectively. The value of each wire equals its logic state value divided by the total number of wires N. For the range [-1,1] W may approximate any number with a maximum error of + — . Let P be the probability that a wire is not broken . By combining a numerator and denominator bundle together in a random fashion the proba- bility "P" will be the same for both bundles. For either ternary or binary logic broken wires will be synonymous with the logic state. Broken wires change the value of both numerator and denominator towards zero, but the value of the ratio remains unchanged. W^^ p(x x - z 1 ) W^ = p(x 2 - z 2 ) (2 * 3) 2.2 Binary Logic Gate Operations 2.2.1 AMD Gates If two inputs to a logical AND gate have probabilities P and P of being a "1", then the output has a probability P, P„ of being a "1" (2) provided the inputs are independent. This can be written as 0P(P x P 2 ) = P X P 2 (2.U) which indicates that the operation of an AND gate on two inputs produces an output which is equal to the product of the input probability values. For stochastic systems the AND gate is a simple and inexpensive multiplier. If two bundles of equal size with logic states and 1 have x and x wires respectively in the 1 state, then the probability of randomly selecting and ON wire from the first bundle is X, and likewise from the second X . Therefore a pair of N-wire bundles can be multiplied together usin£ N two-input AND gates. For the first gate an input is randomly selected from each bundle with the resulting product being XX. For the second gate a different pair of input wires is randomly selected with the resulting product being X,X which is the same as that for the first gate. If this is carried out for all N gates the resulting product for each gate will be X,X . Since all wires of the product bundle have the same probability of being a "1", the value of the bundle will also be XX. The product of two bundles can be written opCx^) - x ± x 2 (2.5) Using binaxy logic (states and 1, W = X), the product of two bundles can also be written as opCw^g) = w x w 2 (2.6) 2.2.2 NOT Gates The operation of a NOT gate is to invert its input. Consider a bundle, logic states and 1, with x wires at 1 (leaving N - x wires at 0) . The value of this bundle is X. Now connect each wire to a NOT gate. The resulting bundle has x wires at and N - x wires at 1. The new value of the bundle is 1 - X. The equation for a NOT operation is OP(W) = 1 - W (2.7) All other Boolean functions can be formed from combinations of AND and NOT functions. Therefore the value of a complex Boolean function can be determined from the values of AND and NOT gates. 2.3 Two Level Mappings 2.3.1 General The logic states and 1 will always be used for two level mappings To map the range [-1,1] onto [0,1] the linear transformations t = 2W - 1, W l t = 1 - 2W, and t = C, (— ) - C_ can be used, where t is the number being -L Wp 2 represented and W is the machine or bundle value. The range [-1,1] was chosen because the magnitude and accuracy of number representations are acceptable for the bundle used in later discussions. The negative of a number is obtained by inverting each wire in the bundle for the first two transformations above. -t = -(2W - 1) = 1 - 2W 1 - 2W = 2W - 1 = 2(1 - W) - 1 1 - 2W = 1 - 2W -t = 2¥ - 1 (2.8) 2.3-2 The Mapping: t = 2W - 1 \ Let T = t— for all of the following cases. t 2 2W - 1 2W - 1 T l = 2W 2 - 1 T 2 = 2W^ - 1 ^ 2#9 ' ) Associate a probability P with W and W and a probability P with W Q and W, where again P and P are the probabilities that a wire will not break. The new equations are 2P W - 1 2P W - 1 T = - 1 - - 1 - t - £_2 (p in) 1 "" 2P X W 2 - 1 2 2P W^ - 1 V^.-i-w; ^P P W W - 2(P W + P W ) + 1 " 1 2 " i+P^W^ - 2(P 1 W 2 + P 2 W^) + 1 ^' ; Since P-iPp i s n °t common to all terms, the mapping is not failsafe, but the possibility of operating on the terms to make P-, P~ common exists. The functions to be generated within the machine are determined by the equation 2W - 1 T = 2W, - 1 = T l * T 2 (2 ' 12 > The two functions "being W 5 = SP^W.^ - (P^ + P 2 W 3 ) + 2 (2.13) W 6 = 2P 1 P 2 W 2 W 4 - (P^g + P 2 W U ) + 2 (2.14) At first glance a solution seems possible by using still another bundle for each T. By randomly combining this bundle (whose value is one) with the numerator and denominator bundles , the machine value of the bundle of ones is the probability "P" associated with the three bundles. Upon scaling and rearranging the function from equation 2.13, the resulting equations become W„ 1 - P„W, - PJJ. i = PPM + ( — 2 -2) 2 12 13 2 ' W c P n W, + PJJ 2 = P^^w + ( 1 X 2 2 3 ) (2.15) By multiplying P W, by P and P p W p by P. , a common multiplier of each term seems possible. After doing this P P W + P P W W 5 = P 1 P 2 W 1 W 3 + ( 2 } (2 * l6) Unfortunately P-,P p cannot be taken out from under the bar to generate a failsafe mapping. This is proved by the following equations: 8 OP(PW) = 1 - PW (2.17) OP(PW) = P(OP(W)) = P(l - w) (2.18) OP(PW) ^ op(pw) (2.19) The mapping t = 2W - 1 proved to be of no value for failsafe operations . 2.3.3 The Mapping: t = 1 - 2W 1 - 2P 1 W 1 1 - 2P g W T l = 1 - 2P X W 2 T 2 = 1 - 2P 2 W^ (2,20) Combine a third bundle with each input so that the values of P and P are readily available. The product T T is the same as equation 2.11. The two new functions are determined from the equation 1 - 2W T = T * T = (2.21) 1 x l 2 1 - 2W 6 K J The two new functions being W c - P,W n + P W - 2P 1 P W 1 W. (2.22: p 11 d 3 1 e 1 . j W 6 = P 1 W 2 + P 2 W 4 " 2P 1 P 2 W 2 W ^ (2 * 23 ' which looks like something which could be obtained from an exclusive-or operation. op(p 1 w 1 e p g w 3 ) = op(p 1 w 1 p 2 w 3 v p-^p^) = PW -PPWW PW -PPWW 11 12 13 2 3 12 13 OPCP^ 9 P^) = P^ + P^ - 2P 1 F^ 1 ^ 3 (2.24) From Boolean Algebra it seems apparent that if W is multiplied by P P the result is W 5 = P l P 2 W l + P 1 P 2 W 3 " 2P 1 P 2 W 1 W 3 (2,25) This is not correct however. P of the third bundle has the same value as P in the product PW , but the product P P W- =/ P W . If the two bundles are randomly combined into N number of AND gates, there is no guarantee that a broken wire in the P bundle will always be paired off with a broken or value zero wire in the P-.W bundle. This mapping must also be rejected as unsatisfactory for failsafe arithmetic operations. W 2.3.4 The Mapping: t = C 1 (~) - C 2 C and C are constants. A symmetrical mapping about zero is desired to be able to perform addition and subtraction equally. This requires T = -T . . Let N be the number of wires in the bundle. T is a maximum max mm W when the value of the ratio — is a maximum. The ratio has a finite maximum w 1 2 for W-. = 1 and W = — where W equal to zero cannot occur thereby excluding the infinite case. 10 W ■ C 1 (N) - C 2 (2 - 26 ' t is a minimum when the value of the ratio is zero. t . = -c_ (2.27) nun 2 ' J t = -t . max mm ^(N) - C 2 = -(-C 2 ) 2C c i = ir (2 * 28) To represent numbers in the range [-1,1], let C = 1. The mapping is defined by the equation 2W * = w 2 - x < 2 - 29 > If division is to be possible the mapping must be 2W T= W < 2 '30) — - - 1 The mapping is undesirable even if it can be made failsafe because four bundles are now needed to represent a number. Since two level linear mappings are unsatisfactory, three level linear mappings were investigated. 11 2.k Threshold Logic for Ternary Systems 2.^.1 General Although ternary logic is generally much more complicated and less definite than binary logic, it has a definite application for Failsafe Bundle Processing. A failsafe mapping can be generated with ternary logic with the advantage of having one basic multiplier circuit to perform the four basic arithmetic operations. 2.U.2 Threshold Operators t (3) The threshold operator ( ) is defined as follows +1 if .Z_ H. > t i=l i - H 1 t H 2 t H 3 t . . . H^ = ^ -1 if i | 1 H ± < -t (2.31) for all other values where 1 < t < n. His any input variable of values 1, or -1. The binary operations AND and OR can be adapted to ternary logic with the use of threshold operators. As threshold operators AND and OR are defined by minimum (H, , H , . . . , H ) and maximum (H, , H , . . . , (5) respectively. H n' 2.U.3 Diametrical Negation Although diametrical negation has the same operator, 0P( ) 5 as the NOT gate, the values of the two operations are not equivalent. For two level logic 12 OP(H) = 1 - H (2.32) where H = or 1. For ternary logic diametrical negation is defined as OP(H) = -H (2.33) where H = 1, 0, or -1. A functionally complete basic set of operators can be realized from (5) the ternary threshold operator and diametrical negation. 2.5 Three Level Mappings 2.5.1 General For three level mappings the logic states + and - are used to represent numbers in machine form. The logic state represents a broken wire. To map the range [-1,1] onto [0,1] the simple transformation t = W can be used. 2.5.2 The Failsafe Mapping: t = W W W T i = T 2 T 2 = % (2 - 3U) By mixing the numerator and denominator bundles together in random fashion, a probability P can be associated with W and W , and a probability P can be associated with W and W, . 13 p w T - 1±A 1 " P 1 W 2 T III 2 " P A (2.35) With inputs T and T being failsafe it is a simple exercise to show that the four basic arithmetic operations are also failsafe. (1) 2.5-3 Ternary Bundle Multiplication For the mapping t = W = X - Z, the product of two bundles is t = t ± • t 2 = w x w 2 t = x x x 2 + z x z 2 - x x z 2 - x 2 z x (2.36) Since the value of a bundle is equal to the value of its individual wires, a two input gate, whose output agrees with the bundle product, can be used for multiplication. The gate product function is realized by making the output probability of being + equal to the probability of both input wires being + (X,X ), plus the probability of both input wires being - (Z Z ), minus the probability of one wire being + and the other - (X-.Z ), minus the probability of the other combination of one wire being + and the other - (X Z ) . The gate function with the appropriate output can be represented in the following way where A and B are logic states of individual wires. A x B *\ B + + - - + Ik If A is randomly selected from a bundle, then the probability that A is + or - is X and Z respectively. Likewise, if B is randomly selected from a different bundle, the probability that B is + or - is X and Z respectively. Now the gate function can be represented as follows A x B a\ b X 1 z l X 1 X 2 X 1 Z 2 t Z 1 Z 2 Which can be described as OP(A x B) = X X X 2 + Z X Z 2 - (X X Z 2 + X 2 Z ± ) (2.37) Using ternary logic gates OP(A x B) = AB v A B (2.38) The above ternary expression is called a conjunction for Bochvar's three valued system. OP(A x B) = OP(A/\B) :a.39) 15 If two N wire bundles are to be multiplied together, then N two input conjunction gates are needed. If an input for each gate is randomly selected from both bundles, the output of each gate will have a value of X,X + Z Z - (X,Z + X Z ). Since all wires of the product bundle will have the same value, the value of the bundle will be the value of a wire. As for the binary case, fast multiplication can be realized by operating on all of the gates in parallel. 2.6 Failsafe Operations 2.6.1 Multiplication Consider two numbers T, and T (previously defined as equation 2.35) 1 " Pl W 2 2 " P A P W P w 11 2 3 1 2 " P 1 W 2 P 2\ PP WW WW T = $ = 3 (2 U0~ P 1 P 2 W 2 \ W 2 \ 2.6.2 Division ^ P^P^ - T 2 - Pl W 2 P 2 W 3 P P w W^ w W^ p p w w ww ^-^--w 12 2 3 2 3 16 2.6.3 Addition For the operations of addition and subtraction, the output bundle is affected by a scale factor of one-half. This scaling problem is called the attrition problem. More will be said about this in the next section. For now assume that the denominator can be scaled appropriately to cancel out the scale factor of the numerator. P W P W ll + 2 W 3 T = T + T = 1 2 P;L W 2 p^ PPWW, +PPWW 12 1% 12 2 3 r l r 2 2 k W..W,, + w w_ 1 ■ w A 3 ^ The process of adding two bundles can be performed by randomly selecting half of the wires of each bundle to be added to form a new bundle, with the resulting bundle being multiplied by a scale factor of one -half . 2.6.k Subtraction P W P W 11 2 3 1 2 - P X W 2 " P 2 W 4 w n w, - w o w 1 ■ J %^ (2 -^» To subtract two bundles each wire of the subtrahend bundle must pass through a diametrical negation gate first. Then the procedure for addition is followed. 17 For all of the above cases T is unchanged by broken wires. W Therefore, the mapping T = — can be used to realize the four arithmetic w 2 operations in a failsafe manner. Also, the above equations suggest that only one basic circuit is needed to perform the four operations. 18 3. ATTRITION PROBLEM 3.1 General The attrition problem is associated with the operations of addition and subtraction for bundle systems. The addition of two bundles can be described as follows x l " z l X P " Z P Randomly select half of each bundle to form a sum bundle with value t= 2 ~ 2 M 2 ~ 2 (3.2) t = |(w 1 + w 2 ) (3.3: where the scale factor of one-half causes what is called the attrition problem. This same scale factor is associated with the output bundle for subtraction. 3.2 Useful Solution W For the mapping T = — a very simple solution exists. The solution w 2 involves the cancellation of the numerator scale factor by an appropriate scale factor in the denominator. The denominator scale factor can be obtained by adding to the denominator a bundle whose value is zero. * - *i + * 2 = - — Sr^ — - i3 - k) 19 Where x = z and x + z = N t =|w 1 (3.5: The solution is not entirely satisfactory since the numerator and denominator values approach zero as the number of addition and subtraction operations required to form the desired output function are increased. 20 k. SABUMA - SAFE BUNDLE MACHINE k.l General A model of SABUMA was built which successfully demonstrated that the operation of multiplication was failsafe for the mapping t = W. The system consisted of two input bundles where each bundle consisted of 10 wires. The model proved that the theory and the system design are correct. As shown in Figure 1, the final system will consist of two analog inputs which are converted to numerator and denominator bundles of 100 wires each. The bundles will then be randomly input into the multiplication circuits whose outputs are the failsafe product bundles of addition, sub- traction, multiplication and division. The product bundles in turn feed summing networks whose outputs are the analog values resulting from four operations of arithmetic being performed on the two analog inputs. k.2 Analog to Bundle Converter 4.2.1 General To make Bundle Processing more attractive and practical, a system was designed to convert analog inputs to bundle values. Cost and simplicity were the main design criteria. Systems of varying complexity ranging from one as simple as a matrix of switches to a very complex one involving analog to digital converters were considered. The system chosen will use comparators to determine the bundle value of each input as shown in Figure 2. 4.2.2 Analog Inputs The analog input voltages will be obtained by using very sensitive variable resistors. To increase input voltage sensitivity the voltage + I >< -I- <<<< 21 DC 0< ocso< 1 0/ £ hi- < <°0 ' k oh ^0 < 22 -P u > O o Ti CQ O -P w o 23 reference levels will be of smaller value for numbers less than one than for those that are greater than one. A multiple pole switch will be used to change the voltages as shown in Figure 3« This switch will also change the series resistance of the output display meters to obtain a maximum range of readings for all input values. The analog voltage now has to be converted to a bundle value. 4.2.3 Rough Input Approximation The first step of the conversion process involves the rough approximation of the input value as shown in Figure k. The comparators determine the input sign and magnitude. When the input voltage is greater than the comparator reference voltage the comparator will turn on. Comparators for numbers of magnitude less than one have a range of one hundred millivolts. When the voltage on a wire is changed from - to + or + to -, the value of the 2 bundle changes by + — respectively. When a comparator turns ON, five wires are changed from - to +. Therefore the bundle value increases by one hundred millivolts. For input values of magnitude greater than one, the bundle value can be set to a limited number of values. The cost and complexity of showing that the denominator bundle can carry useful information is greatly reduced by keeping the numerator bundle fixed at + 1 and setting the denominator bundle to the desired values. k.2.k Comparator Reference Voltages The magnitude and sign of the reference voltages for the various comparators are determined by the sign control bit (SCB) which is set by the sign of the input. SCB becomes the input for the voltage and sign control circuit as shown in Figure 5. The function of this circuit is to supply the 2k o u •H O r.sv 7> ±.4V 7> ± .3V ±.2V i. iv 12. ov I5.ov 25 5- WIRE r NUMERATOR DRIVERS -^ SIGN COklTROL BIT (SCB) DENOMINATOR DRIVERS mote: ALL COMPARATORS ARE F77IC ± IO.OV Figure k. Course Voltage Decoder Circuit 26 AM A— > > wC\J c - 1 — AM— • >> Offl +• r -AM^ CO +" i* -a»AA/- > > C +■ r -AAA/- Q o V^-» <,;■•— VN^> HI ■AM !i 'O <£ 2 en 1 ••— AAA^- in n 'O ID CO 2 O •H O H O fH -P a o u bD •H CO PI n5 0) W) ■P H O > ID •H CD U en 27 comparators with various reference voltages according to the input sign. The reference voltages for the twenty millivolt comparators are not symmetrical about ground. The reason for such an odd arrangement will be explained later in connection with Figure 8. 4.2.5 Fifty Wire Driver The sign of the bundle is controlled by the fifty wire driver circuit. SCB is the input to this circuit as shown in Figure 6. The driver was designed for minimum output impedance because the multiplier circuit of Figure 10 would fail to function properly otherwise. The low output impedance is achieved by driving the output wires through saturated transistors connected to fixed voltage levels . The numerator wires are normally in the OFF position with the bundle value being -1. When SCB goes +, half of the wires will be randomly turned ON with the bundle value being zero. k.2.6 Five Wire Driver The inputs to the five wire driver circuits are the one hundred millivolt comparators as shown in Figure 7« Each comparator has control over five randomly selected wires in the bundle. The driver has a low impedance output. When the input goes +, the output will be driven + which results in the value of the bundle being increased by one hundred millivolts. The out- put also feeds a difference node. 4.2.7 Fine Input Approximation As shown in Figure 8, the difference node is the input to an operational amplifier. The value of the input is equal to minus the number of one hundred millivolt comparators that are + divided by the total number of 28 o u •H O U > •H in O Q) ■H ^ >3 -P CH ■H (D CD o 29 111 2 Ui z ui u. n AAA^ o •H O •H u Q 0) •H & > •H UJO 30 , < K W 51 Of o J.-3 a u a •H -p ■H !* -P •H o •H O 0) O a) U 0) CH <+H •H Q 00 0) •H 31 comparators which is nine. The function of the diode in the output of Figure 7 is to change the logic level of - to that of zero which makes the previous statement correct. Therefore, by adjusting the feedback resistor the output can be made equal to minus the total number of comparators that are + divided by ten. For positive analog inputs the output is equal to minus the one hundred millivolt approximation of this input. For negative analog inputs the output is not so easily related to the input. Let C be the magnitude of the input value rounded off to the next lowest tenth of a volt. Let D be the output value. Therefore the output is related to the input by the equation D = -(.9 - C) (lf.l) Outputs of this operational amplifier are inverted. By feeding the output of the operatinal amplifier through a resistor to another node and feeding the input voltage through a resistor of equal value to the same node their difference can be obtained. For positive analog inputs the non-inverted output of the second operational amplifier is compared with the expected reference voltage levels . The voltage levels differ by twenty millivolts because by changing the logic level of one wire the value of the bundle is changed by twenty millivolts. Let E be the analog input value, and F be the amplifier output value. Then for negative analog inputs the non- inverted output is found from the equation F = E + D F = E + C - .9 (1+.2)- 32 Which means that the values of the reference voltage levels must be decreased by .9 volts from their expected values. U.2.8 One Wire Driver The twenty millivolt comparators control the one wire driver circuits as shown in Figure 9» The impedance which a driver sees is much higher for one wire than it is for five or fifty wires. Therefore, a single wire can be driven by a transistor with a small collector resistor. k.2.9 Numbers Greater Than One For numbers greater than one the numerator bundle is fixed at +1 or -1 depending on the input sign while the value of the denominator bundle is varied to approximate the input voltage. Wires in the denominator bundle are normally in the + state. The denominator drivers have the same design as the numerator fifty and five wire drivers . The only change is the addition of an inverting transistor before the output stage. The analog to bundle converter is capable of approximating any number in the range [-1,+1] with a maximum error of ten millivolts. A limited number of values greater than one can also be approximated by the converter. The converter demonstrates a simple way of converting analog inputs to bundle values quickly. h.3 Arithmetic Unit 1+.3.1 General W n W_ 1 W 2 2 \ 33 Of m OUl 00 nJO 02 -P •H O ^H •H U ■H Q 0) •rH 0> a o faD •H 3^ To perform addition, subtraction, multiplication, and division five products have to be formed. They are WW, WW,, WW,, WW, and -WW. Since the five products will be formed at the same time, the machine will be capable of performing simultaneously the four arithmetic operations. By passing these products through summing networks the analog values of the various arithmetic operations will be formed. U.3.2 Multiplier The multiplier circuit of Figure 1.0 multiplies the logic values of its inputs. The output value agrees with that of a two input conjunction gate. 0P(A x B) = AB v A B (k.k) The circuit uses a combination of discrete and integrated circuits to produce the necessary output function. Many simplier designs were tried with resulting impedance and latching problems. This circuit is very reliable and capable of operating at high speeds . The four SM1660 transistors check for breaks on both lines. If the wires are not broken the logic value of the AND function of the input and the second SM1660 transistor from the left is -. For broken wires the AMD function will rise to some value greater than zero. Therefore, the first 2N706 transistor from the left is cut off for no breaks. This causes one input of SW7401 to have a + logic value which makes the NAND gate act like a simple inverter. For a broken wire the 2N706 transistor is saturated which forces one input of SN7^01 to have a - logic value. The output of SN7UOI will have a + logic value for all inputs in this case. The third 2WJ06 35 I + O •f i -p •H o •H O U 0) •H H Ph •H +3 rH I o H •rH Wv ||i 36 transistor from the left is also saturated for a broken wire. The function of this transistor is to drag the output down to zero when a break occurs. Otherwise it is cut off, and has no affect on the output. The SF7U0I integrated circuit has an open collector output. By using a pull up resistor the positive reference level is fairly constant from circuit to circuit. The negative and zero reference levels are not as fixed but the small fluctuations have little effect on the final analog value obtained from the summing networks. The offset voltage associated with the - logic state can be compensated by a power supply adjustment. The offset voltage associated with the zero logic state cannot be easily compensated. Fortunately the error for neglecting this problem is about 1% for every ten circuits with a zero logic state output. k.k Decoder Now that the product bundles have been formed, a circuit is needed to convert the bundle value back to an analog value. This is done very easily by feeding each wire of the product bundle through a resistor connected to a node point. The resistor values must be the same for all wires if each wire is to be equally important. As shown in Figure 11, the node points for the numerator and denominator bundles are the non-inverting inputs of operational amplifiers. The output of the amplifier being equal to some scale factor times the number of wires + minus the number at - divided by the total number of wires in the bundle. Which is the same thing as some scale factor times the bundle value W. The analog values of the numerator and denominator bundles enter the divider. The output is displayed on a current meter. Although the Hi' 37 s v> ft H -p •H o u •H O & H ft w •H Q O H 05 a) -P o CM H (1) •H h 01 2a REPORT SECURITY CLASSIFICATION Unclassified 2b GROUP REPORT TITLE SABUMA - SAFE BUNDLE MACHINE DESCRIPTIVE NOTES (Type ol report mnd inclualva dataa) Technical Report, Masters Thesis August, 1970 AUTHOR(S) |La«t nama. Ural name. Initial) Coombes, Daniel J. REPO RT DATE August, I97O 7a- TOTAL NO. OF PAGES ^ 7b. NO. OF REFS a. CONTRACT OR GRANT NO. N000 14-67-A-0305-0007 b. PROJECT NO. 9«. ORIGINATOR'* REPORT NUMalERfS; 9b. OTHER REPORT NOfSJ (A r\y other number* that may be aeetgned thla report) 3 AVAILABILITY/LIMITATION NOTICES SUPPLEMENTARY NOTES 12. SPONSORING MILITARY ACTIVITY Office of Naval Research 219 South Dearborn Street Chicago, Illinois 6060A I ABSTRACT To overcome the problem of transmission failures a system was developed to realize the four operations of arithmetic in a failsafe manner. Using this system, called Failsafe Bundle Processing, a number is represented on a group of wires, and its magnitude is determined by the difference of wires at one level from those at another level. Ternary logic gates were used to realize the lecessary functions needed to perform the arithmetic operations independent of physical or electromagnetic intrusions. FORM 1 JAN 84 1473 UNCLASSIFIED Security Classification UNCLASSIFIED Security Classification KEY WORDS Failsafe Bundle Processing Attrition Bundle Sabuma Analog to Bundle Converter Failsafe Mapping LINK A LINK B ROLE LINK C V»T INSTRUCTIONS 1. ORIGINATING ACTIVITY: Enter the name and address of the contractor, subcontractor, grantee. Department of De- fense activity or other organization (corporate author) issuing the report. 2a. REPORT SECURITY CLASSIFICATION: Enter the over- all security classification of the report. Indicate whether "Restricted Data" is included Marking is to be in accord- ance with appropriate security regulations. 2b. GROUP: Automatic downgrading is specified in DoD Di- rective 5200. 10 and Armed Forces Industrial Manual. Enter the group number. Also, when applicable, show that optional markings have been used for Group 3 and Group 4 as author- ized. 3. REPORT TITLE: Enter the complete report title in all capital letters. Titles in all cases should be unclassified. If a meaningful title cannot be selected without classifica- tion, show title classification in all capitals in parenthesis immediately following the title. 4. DESCRIPTIVE NOTES: If appropriate, enter the type of report, e.g., interim, progress, summary, annual, or final. Give the inclusive dates when a specific reporting period is covered. 5. AUTHOR(S): Enter the name(s) of author(s) as shown on or in the report. Enter lest name, first name, middle initial. If r.-.ilitary, show rank and branch of service. The name of the principal author is an absolute minimum requirement. 6. REPORT DATE: Enter the date of the report as day, month, year; or month, year. If more than one date appears on the report, use date of publication. la. TOTAL NUMBER OF PAGES: The total page count should follow normal pagination procedures, i.e. , enter the number of pages containing information. lb. NUMBER OF REFERENCES: Enter the total number of references cited in the report. 8a. CONTRACT OR GRANT NUMBER: If appropriate, enter the applicable number of the contract or grant under which the report was wTitten. 8b, 8c, & 8d. PROJECT NUMBER: Enter the appropriate military department identification, such as project number, subprojec t number, system numbers, task number, etc 9a ORIGINATOR'S REPORT NUMBER(S): Enter the offi- cial report number by which the document will be identified and controlled by the originating activity. This number must be unique to this report. 9b. OTHER REPORT NUMBER(S): If the report has been assigned any other report numbers (either by the originator or by the sponsor), also enter this number(s). 10. AVAILABILITY/LIMITATION NOTICES: Enter any 1 im- itations on further dissemination of the report, other than those imposed by security classification, using standard statements such as: (1) "Qualified requesters may obtain copies of this report from DDC" (2) "Foreign announcement and dissemination of this report by DDC is not authorized. " (3) "U. S. Government agencies may obtain copies of this report directly from DDC. Other qualified DDC users shall request through (4) "U. S. military agencies may obtain copies of this report directly from DDC Other qualified users shall request through (5) "All distribution of this report is controlled. Qual- ified DDC users shall request through If the report has been furnished to the Office of Technical Services, Department of Commerce, for sale to the public, indi- cate this fact and enter the price, if known. 1L SUPPLEMENTARY NOTES: Use for additional explana- tory notes. 1Z SPONSORING MILITARY ACTIVITY: Enter the name of the departmental project office or laboratory sponsoring (pay- ing for) the research and development. Include address. 13. ABSTRACT: Enter an abstract giving a brief and factual summary of the document indicative of the report, even though it may also appear elsewhere in the body of the technical re- port. If additional space is required, a continuation sheet shall be attached. It is highly desirable that the abstract of classified reports be unclassified. Each paragraph of the abstract shall end with an indication of the military security classification of the in- formation in the paragraph, represented as (TS), (S). (C), or (V). There is no limitation on the length of the abstract. How- ever, the suggested length is from 150 to 225 words. 14- KEY WORDS: Key words are technically meaningful terms or short phrases that characterize a report and may be used as index entries for cataloging the report. Key words must be selected so that no security classification is required. Identi- fiers, such as equipment model designation, trade name, military project code name, geographic location, may be used as key words but will be followed by an indication of technical con- text. The assignment of links, rales, and weights is optional. DD FORM 1 JAN Si 1473 (BACK) UNCLASSIFIED rifi* P 1 1 a ta c i f i rofinn