LIBRARY OF THE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN 510.8^ ho.£|-&0 >3 eo Digitized by the Internet Archive in 2013 http://archive.org/details/designingcompute72leic UNIVERSITY OF ILLINOIS GRADUATE COLLEGE DIGITAL COMPUTER LABORATORY REPORT NO. 72 DESIGNING COMPUTER CIRCUITS WITH A COMPUTER By Gene H. Leichner September 17, 1956 This work has been supported by Contract N6ori-71 Task XXIV United States Navy ONR NR 048 094 II I DESIGNING COMPUTER CIRCUITS WITH A COMPUTER* by: Gene H. Leichner Digital computer circuits require that a number of tolerance conditions be met at one time. The number of these tolerance conditions which must be simultaneously satisfied in some circuits, such as a flipflop using transistor switching elements, is very large. The design of these circuits can be materially aided by using a digi- tal computing machine to solve the resulting simultaneous equations. 'This paper discusses the derivation and solu- tion of the five simultaneous non-linear algebraic equa- tions resulting from an analysis of a flipflop circuit using transistors. The method has been carried out using the Illiac at the University of Illinois. *This work was supported oy the Office of Naval Research under Contract N'6ori-07124o This paper was presented at the eleventh annual meeting of the ACM at Los Angeles August 28, 1956. A i DESIGNING COMPUTE] ITH A COMPUTER Gene H. Leichner, University of Illinois The circuit to be considered is that of a transistor flipflop as shown in Figure 1. All polarities are chosen for NPN transistors. In this analysis, the transistor r , r. , and r will be assumed negligible for simplicity. It will also be assumed that i = 5 (i-b)r, (l-B)R, (4) | V^ I > (1 + B) R. (1*B)R, (5) • ♦ V (1+B)R, i> (1-B)R 2 (6) <» — • (l-B)R, (1-A)E 2 Smallest acceptable negative outout (1*A)B 2 Smallest acceptable positive outout (1-A)E 2 Maximum collector voltage (1+A)E 2 Minimum collector voltage Figure 2. The considerations involved in the four conditions will be dis- cussed briefly. Smallest acceptable negative signal outout. Aside from choosing the supply voltage and resistor tolerances in unfavorable directions, the collector current of the transistor has been chosen as the ndnimum value I,, i.e. that which would result from oC = Y, a large value of R, , and a small E . In addition, this is the condition requiring the greatest power dissipation from the transistor so V, has been expressed as a function of W and I. . Smallest acceptable positive signal outout. ■ain the most unfavorable directions for resistor and supply volt- age tolerances have been chosen. Also the largest current, I,., from the output terminal has been chosen. Ij. is the load current, 1^, plus the largest base current drawn by the emitter follower part of the flipflop, i.e. «C= Y, small R. , and large E . 4 ^ -2- Maximum collector voltage. In this case the transistor is assumed to be completely cut off, and the current I,, which would normally be present is assumed to be zero, i.e. °C = 1 and I~ = 0. The resistor and supply voltage tolerances also have been appropriately chosen. I'iinimum collector voltage. All the conditions which would cause the collector of the transistor to go most negative are represented here. The largest output current I~ and the largest collector current are used, i.e. °( = X, small R, , and large E~. The emitter follower is cut off so its base current is zero. When a gate circuit is attached to the collector, its current and toler- ances must be included in this condition. If it is of a type in which the current is essentially determined by an emitter resistor, as in the flipflop proper, the collector current of the flipflop can be doubled to include the gate. This is not shown here. The circuit is described by writing the node equations at the marked nodes. W/I 1 - (1+A)E 1 W/I - V 2 N ° de (1) (1-B)^ + h + (1-B)R 2 = ° V - W/I V - (l-A)E N0de < 2 > (1-B)R 2 + (1+B)R 3 = ° V - (l-A)E V - (1+A)E N ° de < 3) (1^B)( V R 2 ) + h + (1-B)R 3 " ° V - (1+A)E 1 V - (1-A)E 2 N0de (4) (1-B)R 1 + (1+B)(R 2 +Rj = ° V c - (1-A)E 1 V 5 - V ( (1+B)R 1 I 3 + (l-B)R, Node (5) > TTTtt + I, + /? P \ P - -3- V, - V V, - (1+A)E, Mode (6) T £ 3J g| * I, * (i-B)R 3 " ° («) * 5 -(¥)(£I)(££h * h Equations (8) and (7) are to be substituted in (3) and (5) respec- tively. Equations (5) and (6) may be combined to eliminate V/. Five simultaneous non-linear equations in E, , I., R, , R~, and R... result. Note that the base current used by the emitter follower portion of the flipflop has been included in the analysis as part of I_. This is necessary because the design is quite sensitive to I_. It is clear that the given specifications may be contradictory so that no solution exists. This is because several of the specifications place restrictions on the same quantities. Even if a solution exists, it is quite possible that some requirement will be more than just met. Therefore, it is not possible to do a brute force simultaneous solution of the five equations. In order to solve the five equations obtained above, a program was prepared for a digital computer, Illiac. Note that the values for V , V, , and I , in the specifications are limiting values so V, , V_ , and I. a a 4 ? k will not necessarily be equal to them. The code was prepared, however, to operate the transistor at the specified maximum collector dissipation, W, to obtain the lowest possible circuit impedance. This should give the maximum speed of operation for a given transistor. Also, the V and V requirements will be just met, so in the worst tolerance cases the output voltages Vp and V_ will be equal to these values. If so desired, differ- ent choices as to which conditions are to be just met could be made. The organization of the code for Illiac is as follows: 1. Read the specifications from a tape. 2. Set E, to the largest value to be considered. -4- 3. Set I, = I , the largest permitted. So far a maximum gain network -L cL has been assured. 4. Solve equations (l), (2), and (3) for R-, , R^, and R~. No solution exists if one or more of these is negative or complex the first time, with largest E. and I, . 5. Set I, = !„, a value which is certain not to work, and repeat Step 4. 6. Continue to converge on the smallest value of I, for which a solu- tion in Step 4 exists by a binary chop procedure. That is, at each step try I, halfway between the last value which worked and the highest value which did not work. 7. Check the saturation condition by equations (5) and (6). No solu- tion exists if this condition is not met the first time since the network has maximum gain and the collector current has been re- duced as far as possible. 8. Set E, = V , a value which is certain not to work, and repeat Steps 4 through 7» If there is no solution at Step 4 the first time, skip to Step 9. 9. Continue to converge on the smallest value of E, for which there is a solution in Step 4 and for which the saturation condition is met. Use a binary chop procedure as in Step 6. 10. Check the maximum collector voltage condition by equation (4). No solution exists if this condition is not met since the collector supply voltage is now as small as possible and the network gain has been reduced as far as possible. The code used on the Illiac prints the given requirements and the conditions which are not met, followed by the values of E. , I, , R.. , R~, R~, V, , and V_ so the designer can see by how far the conditions were not met and perhaps make some changes in the specifications to make a solution possible. In case all the conditions were more than just met, he may be able to increase the tolerances to permit the use of less precise components. ^//y^JL Gene H. Leichner -5-