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 « fUJNBR 
 
 UNIVERSITY OF ILLINOIS - li} °U 
 
 GRADUATE COLLEGE UbNARV 
 
 DIGITAL COMPUTER LABORATORY 
 
 REPORT NO, 92 
 
 THE ARITHMETIC UNIT 
 
 hy 
 
 David J. Wheeler 
 
 August 21, 1959 
 
 This work was supported in part by the 
 Atomic Energy Commission and the Office of Naval Research 
 under AEC Contract AT ( 11- 1) -415. 
 
THE ARITHMETIC UNIT 
 by David J. Wheeler 
 
 1,0 Objectives 
 
 The object of the report is to give the design details of an 
 asynchronous arithmetic unit using logical elements developed by the circuits 
 group in which: 
 
 a. High speed of operation is possible, 
 
 b. The unit is not too expensive. 
 
 c. The unit is designed primarily for floating point operations 
 with the additional requirement that the accumulator should 
 hold results to double precision. 
 
 The last requirement is in order that double precision operations should be easy 
 to code. Thus parts of long calculations may be performed to double precision 
 with little complication in coding. 
 
 The appropriate compromise for the arithmetic unit has been made in the 
 following way. 
 
 The main arithmetic unit which deals with the fractional part of each 
 floating point number contains an operand register M and a double length double 
 rank shifting register AQ, SR. Each register contains h6 bits, and the fractional 
 part in the store is 4 5 bits, the exponent 7 bits. 
 
 Fixed point numbers will be operated on only to 4 5 bits, the exponent 
 digits not being used. A single up gate or down gate consists of an addition 
 6f the operand to the more significant half of the accumulator and a shift. The 
 following measures ensure speedy operation: 
 
 1. Base k carry storage is used as described in Report 80. 
 
 2. A non- restoring adder with delay time of less than 9 mu.s ., is used. 
 5. A shifting selector follows the adder and allows the result 
 
 to be displaced one or two base k places to the left or right. 
 
 -1- 
 
k. The add shift operation is possible both on the up gate and 
 
 down gate . 
 5» A push pull gating system is used* 
 
 6. A base four multiplication scheme is used with a short cut 
 for zero base four digits. The number of steps for multipli- 
 cation is about 20. 
 
 7. A base k division process due to J. E. Robertson results in 
 only about 26 steps being necessary for division, 
 
 8. The shift options of the arithmetic unit allow a variety of 
 schemes for floating point addition. These are selected by 
 control to minimize the time. 
 
 9» The fast carry generator has been made non iterative ly to 
 ensure a small time of operation. (Maximum 33 rajas) 
 
 1. 1 Representation of Numbers in the Store 
 
 The word length is 52 bits. Most numbers are represented in a floating 
 point form, in which the word X is split into two parts, namely a fractional 
 part having the value f and an exponent having the value p. 
 
 f is represented by h^ bits, the binary point is assumed to be between 
 the more significant two digits. Negative numbers are represented in a 2's 
 complement form. Thus if f . represents the value of the ith binary digit of f, 
 
 namely zero or one; then 
 
 kk 
 f = -f + Z 2~ X .f. 
 ° i=l 
 
 so that -1 < f < - l/k or + l/k < f < 1 or f = . 
 
 p is represented by 7 digits, and if p. represents the value of the binary digit 
 of p, then 
 
 p = -e^pg + gs 1 p. 
 
 so that - 6k < p < + 6k. 
 The word X represents the number 
 
 N(X) = f . k V or more precisely, N(X) = f (X) • k 9 ^ 
 
 -2- 
 
1.2 Operand Splitting 
 
 An operand is split into its two parts as it enters the arithmetic unit. 
 The fractional part is used in the main arithmetic unit (MAU) which can 
 represent signed fractions with a precision of sign and 88 bits. The exponent 
 part is operated on in the exponent arithmetic unit (EAU), which can represent 
 exponents with sign and seven bits. 
 
 1.3 The Formation of Words 
 
 Numbers held in MAU and EAU are used to form words which can then be 
 stored. Because of the fewer bits used to represent numbers in the store, 
 this grouping process requires a rounding and truncating which may cause 
 "rounding errors" and "overflow errors." The fractional part is normalized before 
 storing floating point numbers. 
 
 Fixed point operations are usually performed by using floating point 
 orders together with a "store-fixed point" order. This order causes the 
 fractional part to be shifted until the exponent is zero, and the result 
 rounded and stored. Thus fixed point numbers are represented as 
 
 f • k where p = and f may not be normalized. 
 
 l.k The Overflow Indicator 
 
 An overflow indicator is set when an instruction cannot obtain a true 
 result because of the restricted range of numbers within the arithmetic unit. 
 
 70 
 
 For example: storing .5 x V in floating point form or dividing by 
 
 zero. 
 
 -3- 
 
2 . Representation of Numbers within the Main Arithmetic Unit 
 
 The heart of the MAU is two double-rank shifting registers, A, S and 
 Q, R, each of which represents 46 bits. At the end of an arithmetic instruction 
 the registers A, Q contain the two parts of a double precision number, f (A,Q)„ 
 
 by 
 
 then 
 
 Let the binary values of the digits stored in A and Q be represented 
 A 4 A A 1 — A ^ ™&W •-■ % 6 i 
 
 f (A,Q) = -2A . + Z 2~ n A + k~ 2d Z 2~ n Q 
 v ' ' -1 n 1 n 
 
 This assumes that the "carry storage" digits are zero,, These carry 
 
 storage digits are part- of A, S Q, R. In fact, these carry digits are 
 
 represented by A* , r = 0oo<,44, Q* and Q#, Q-tf.? a:nd when these are non-zero 
 we define 
 
 hk 22 
 
 f(A,Q) = -ai. 1+ Z 2" n A n + J 2- 2n J^ 
 
 ^ 22 (.| 1 2" n % + Q| ■ 2" 2 + QJ • 8"*) -Qf 6 2-5° _ 
 
 It follows from the definition above that f(A,Q) is represented by A 
 to single precision and that no digit of Q corresponds to a sign digit. 
 Conventionally at the end of each instruction, both Qr_ and Q, r are zero. 
 
 f(S,R) is defined similarly, 
 
 2 . 1 Notes about the Main Arithmetic Unit (Figure l) 
 
 The 45=bit fractional part of the operand is normally placed in M. 
 By the two sets of selectors, connected to M, each of which is followed by a 
 level restorer connected to a pseudo-adder, we can add or subtract multiples 
 of one or two times the operand to or from the number in A or S„ The result 
 of this pseudo- addition can be snifted left or right as indicated, as it is 
 gated into the destination jregisters. There also exists a straight-down path 
 from S, R to A, Q, without a shift and an interchange path, which routes 
 A— *R, Q,H>S<, When the carry generator is selected, then the output of the adder 
 gives the true sum with the carry outputs zero. 
 
 -j^ 
 
-p 
 
 •H 
 
 B 
 
 a 
 
 •H 
 
 -P 
 
 0) 
 
 u 
 
 < 
 
 •H 
 0) 
 
 ■p 
 
 O 
 
 o 
 
 •H 
 
 -P 
 
 o 
 
 
 CO 
 
 to 
 w 
 o 
 
 o 
 
 CD 
 O 
 •H 
 
 t»0 
 
 Q 
 
 -5- 
 
3.0 The Exponent Arithmetic Unit 
 
 This unit serves three purposes. The first is to hold the exponent of 
 the number corresponding to the arithmetic unit. The second is to count shifts 
 and steps of multiplication and division, and to increase or reduce the exponent 
 as the number in the main arithmetic unit is normalized or shifted. The third 
 is to perform the additions, and subtractions and comparisons of exponents, in 
 floating point operations. 
 
 3.1 Notes about the Exponent Arithmetic Unit (Figure 2) 
 
 Registers eM, eA and d each contain 8 bits. Thus the sign digit of the 
 exponent on input to eM feeds the two more significant digits of eM. eM normally 
 holds the exponent of the operand and eA holds the exponent associated with the 
 arithmetic unit. Register d holds the difference or sum of two exponents before 
 being transferred out or to eA. 
 
 The adder with complete carry chain which is connected to eM and eA 
 has a discriminator attached to its two wire output. This discriminator has 
 outputs indicating that the sum is zero, +ve, -ve, > +12, >23, etc., which 
 are used by control in floating operations. 
 
 The pair of registers sh and ch each hold five bits, and form a shift 
 counter which is operated by the up and down gates in the main arithmetic unit. 
 The associated adders can add zero, one, or two, or clear in each up or down 
 shift. 
 
 There is a discriminator attached to each adder which can detect if 
 the result is 0, -1, or -2, and possibly other values also u 
 
 -6- 
 
eA 8 bits 
 
 IN 
 o- 
 
 -°OUT 
 
 Discriminator 
 
 Figure 2 
 Diagram of the Exponent Arithmetic Unit 
 
 .7- 
 
4.0 The Multiplication Process 
 
 We describe here the operation of an order which replaces f (A,Q) by 
 f(A,Q) f(M), i.e., it replaces the number in the accumulator by its product with 
 the operand. It is assumed that f (A,Q) is initially normalized. 
 
 The first step is to place f (AQ) "f in R, by the interchange operation, 
 load M, set up 23 in the shift counter, and clear S to zero at the same time. 
 
 The following steps each add a multiple of f (M) to f(A) or f(S) and 
 shift right 2 or k bits. The multiple in each case is determined by the last 
 four digits of Q or R. 
 
 The last step may be special if only 2 more digits of the multiplier 
 are left. In this case, only 2 bits are sensed. The product is now assimilated 
 with a right shift of two places, and moved back directly into A, Q, or with a 
 left shift of 2 or h places, according to its size. eA which has been replaced 
 by eA + eM is increased by -1, 0, +1 in the three cases respectively. 
 
 The overflow indicator is set if eA exceeds 127. f(A,Q) is cleared to 
 zero if eA < -128 and then eA is set equal to -128. 
 
 k.l The Rules of a Single Step of Multiplication 
 
 The multiple of M, which is added or subtracted at a single stage, 
 is determined by the values of Ql „ . . . Ql r 9 or R. p ...R,^. Because time is of 
 value, the sensing circuits are at the input to the registers rather than the 
 outputs, and control has to set the selectors before the gating waveform at 
 the input is removed. A table. is given on the following page of the rules for 
 selection of the multiples, etc. Initially R*> is cleared. There are 
 analogous rules for the down gate. If QJ 6 Q^ Q, Q^ Q, are complemented, 
 then Rj£ is complemented, the shifts remain same, the multiples are complemented, 
 and the counts remain the same. 
 
 Under certain assumptions the mean number of steps in multiplication 
 is close to t 19- 
 
 f If rounding causes N(AQ) = +1, then the multiplication is replaced by an 
 addition. 
 
 •8- 
 
%6 
 
 % 3 
 
 %k 
 
 0*5 
 
 %6 
 
 He 
 
 Shift 
 
 Multiple 
 
 Count 
 
 
 
 
 
 
 
 
 
 
 k 
 
 
 
 2 
 
 
 
 
 
 
 
 
 
 1 
 
 
 
 k 
 
 +1 
 
 2 
 
 
 
 
 1 
 
 
 
 
 
 k 
 
 +2 
 
 2 
 
 
 
 
 1 
 
 1 
 
 1 
 
 h 
 
 -1 
 
 2 
 
 
 
 
 
 
 
 
 
 
 2 
 
 
 
 1 
 
 
 
 
 
 1 
 
 1 
 
 
 
 
 
 1 
 
 1 
 
 
 
 
 
 
 2 
 2 
 
 +1 
 +2 
 
 1 
 1 
 
 
 
 
 1 
 
 1 
 
 1 
 
 2 
 
 -1 
 
 1 
 
 
 
 
 
 
 
 
 
 
 2 
 
 
 
 1 
 
 
 
 1 
 
 1 
 
 
 
 1 
 
 
 
 2 
 
 +1 
 
 1 
 
 
 
 
 1 
 
 
 
 1 
 
 h 
 
 -2 
 
 2 
 
 
 
 
 1 
 
 1 
 
 1 
 
 k 
 
 -1 
 
 2 
 
 -9- 
 
5.0. Division 
 
 To perform this order the divisor, herein assumed to he normalized and 
 non-zero, is placed in register M, and the dividend which may be double precision 
 is assumed in (A,Q). The quotient is generated in register Q, and at the end of 
 the division process is normalized and transferred to A. The exponent and overflow 
 operations are simple and not discussed., 
 
 5-1 One Step of the Robertson Division Process 
 
 Each step consists of estimating the multiple of m to be added, adding 
 it, and multiplying the result by k. Simultaneously 2 more digits are introduced 
 into Q and a "borrow" may be propagated. The multiples that are added to the 
 partial remainder are +2m, -2m, +-m, -m, or zero; and the new base four digit of 
 the quotient is -2, +2, -1, +1, or zero. If the quotient digit is -2 or -1, then 
 borrows propagate across all zeros immediately preceeding it. By using the carry 
 generator circuit to inspect the sign digit of A every second step of division, 
 we can arrange that no borrow propagates more than 6 stages. 
 
 5.2 Precision of Predictor Circuits 
 
 The predictor inspects the signs of such quantities as (a - §), (a + -) 
 
 \ a 2'* ' a + 2) in order to discover the closest multiple of m to a, where "a" 
 
 is the current partial remainder and "in" is the divisor. We show below that these 
 prediction quantities need not be calculated precisely, but may be made with an 
 error . We can assume without loss of generality that both "a" and "m" are 
 positive. 
 
 o 
 
 1. The largest value that "a" can take is — for 
 
 3 
 
 (a-2m).4 < a i.e. a < % . 
 max — 3 
 
 2. If the comparison quantity is in error by£ , then for example 
 
 (a - Tj) " ^ ma y be negative when (a - |J) is positive. Thus we subtract the zero 
 
 multiple instead of the unit multiple and 
 
 new partial remainder = Ma- ^) < h$, 
 
 thus a > hS and£< ^. 
 max 6 
 
 -10- 
 
By considering each case separately, we find that each comparison must 
 he made with an error of less than | r | . ni has a range of ■% < |m| < 1 when 
 it is normalized so that if we arrange that all comparisons are made with the 
 same precision, then the error of each comparison must he less than -^. We may 
 perform the comparison (a - -) "by truncating a and m at A,_ and M, . 
 
 Then the truncation error of a = X A + E A* < j- and is positive. 
 
 m « n 3 ^ n * 4 
 
 The truncation error of representing -r by its digits up to Mr is positive and less 
 
 than -rp. The truncation error of representing ~ hy the one's complement of ~ 
 and truncating at the same digital position is likewise less than — . Thus two 
 
 comparisons can be made hy simply truncating at the fifth digital positions. To 
 
 3m 
 find a sufficiently precise representation of ~ is more difficult. We can form 
 
 —r using the digital positions up to 2 and truncate the result. 
 
 This has a maximum positive error of 6 < ^ .2 + 3.2 < -^y- . 
 
 -3m 
 However — — cannot be formed sufficiently precisely by taking the one's complement 
 
 3m 
 of the truncated represention of ^ , so this would entail a separate adder to 
 
 .p -3m 
 form -^. 
 
 A more economical rule is given following: We form a representation of 
 
 3m M -*5 
 
 *=■ by truncating — and M at 2 ■* and adding these together forming k. Form an 
 
 3 -^ 
 extra digit C^ = M/-(M._ + M_) . We represent ^ m by k + 2 J C C . Similarly we 
 
 ^3 1 ° 5 ( 2 _ _ 5 _ 
 
 represent -^m by the one's complement of k and d = M,- (lyL + M ). The truncation 
 
 error is positive in both cases and has a maximum less than 2 + ^ 2 ■' which is 
 
 1 3 
 
 less than -rr. This rule has the merit that we require only a single ^-m circuit 
 
 but this advantage is slightly offset as the comparison circuit has one extra 
 
 digit to deal with, 
 
 5.3 Prediction Circuits 
 
 nj _ j.i • .... j.. x. j. • • j-t. -u-j.. m -m +3m -3m 
 
 At the initiation of a division process, the quantities — , — , -p, — p 
 
 are represented as described above and are formed by restoring circuits. During 
 
 the process whenever a new partial remainder is gated into A, it is at the same 
 
 time gated into the two-wire asynchronous prediction circuits, consisting mainly 
 
 of adders. The outputs are used to set the selectors for the next stage. 
 
 To avoid waste of time in division it is desirable that the comparisons 
 be made quickly. Thus, four comparators are provided which work in parallel, and 
 each uses the unassimilated gated partial remainder. 
 
 -11- 
 
The carry generator is used to find the true sign of A, and if the 
 zero multiple is added during the up gate, then the sign is used to cause a non- 
 zero multiple to be added during the following down gate. (it is in this case 
 still the true sign of the partial remainder.) For example, if a is positive, 
 
 and a ' ' positive, and a — L_L- positive, then we form (a - - i -^) i <- as the 
 new partial remainder. This can easily he shown to be within the allowable 
 range for partial remainders. 
 
 5. if Intermediate Overflow 
 
 o 
 
 Although ' ■ ' is larger than 2 so that a partial remainder can be out 
 of range as far as the registers are concerned, the comparison circuits can 
 work modulo 8, because the extra digits are available at the input to the 
 registers as a consequence of the left shift of two bits. Thus, the digits 
 required for the comparison circuits are those from digital portions 7 through 
 at the output of the adder. 
 
 5°5 Notes Co ncerning Division Process 
 
 While the comparison circuits are being set up at the initiation of 
 the process, (A,Q) is moved to (S,R). During the first step, the digits -2, 
 -1 are not allowed to propagate in Q and thus possibly affect the dividend. 
 Then 23 or 2k- ateps are performed so that the quotient is normalized in Q. 
 The final adjustments depend on the division variant which is being performed., 
 
 -12- 
 
6.0 Store Floating Point Number 
 
 The content of A, Q is assimilated and normalized if this has not 
 already been done. Then, digits q , q , q , q^, q , q^, a^ are examined; 
 2~ q x (q^ + q, + q^ + q^ + q^ + a^) is added to A, Q using the assimilator. 
 The result is combined with the exponent. If the exponent > 63 then the overflow 
 indicator is set, if <-6k then the inaccuracy indicator is set and the numerical 
 part made zero. If, however, the round-off causes the numerical part to equal 
 +1 then the numerical part is divided by k and the exponent increased by 1. 
 
 6.1 Round Off Bias 
 
 If the number in A, Q has many non zero digits in Q, then this 
 
 . , -6.2 -kk -ik -kk 
 
 method gives a bias of (1/2 .2 ) .2 = 2 ' ,2 .If the number in A, Q 
 
 has at most the first six digits of Q non zero, then the bias is 
 Z(error) = 31.2' 12 .8"** = 2" 7 .8" W . 
 
 This is non- negligible, but less than the bias would have otherwise been. For 
 
 -2 -kk 
 example, if A, Q is halved the simple rules give a bias of 2 .2 , which 
 
 is 32 times as large. 
 
 6.2 Store Fixed Point 
 
 The number AQ is shifted till the exponent eA is zero, and then A,Q is 
 rounded as described above, and stored. Overflow causes the indicator to be set. 
 
 -13- 
 
7.0 Floating Point Addition 
 
 This is the most complicated operation of the computer because the 
 method used for performing the operation depends considerably on the magnitudes 
 of the operand and augend, and because we have arranged that the result is 
 correct to double precision. 
 
 Given the accumulator containing f(AQ) • h e and an operand f (M) 'k 
 then the sum may be written as 
 
 [f(AQ).^ d + f(M)] h eK 
 
 or 
 
 [f(AQ) + f(M)4"^ ^ ' 
 
 Because the registers are of fixed length, and numbers are normalized so that 
 their fractional parts are as large as possible, an arithmetic left shift will 
 give the wrong result due to overflow. 
 
 Thus the arithmetic operations we must perform are 
 either [f (AQ) ^ d + f (M)| k eM when d < 
 
 or jf (AQ) + f (M) k' d j h eA when d > 
 
 both of which may be performed by right shifts. 
 
 Thus we may do the first operation by arithmetically right shifting 
 f (AQ) (-d) places and then add M to the shifted accumulator. eA is replaced by 
 eM. The only "digits lost" in this process are those right shifted out of Q, so 
 that the result has about 88 bits of precision. 
 
 The second operation is more difficult. It is performed by a cyclic 
 left shift of d places of f(AQ), followed by an addition of f(M), followed by a 
 cyclic right shift of d places. In this case, the cyclic right shift must 
 incorporate means for propagating carries or borrows according to the result 
 of addition. The procedure we have chosen to deal with this problem is described 
 in Section 7.1. 
 
 To minimize the time spent in shifting in floating point additions, use 
 may be made of the interchange operation which is a cyclic shift, right or left, 
 
 -Hi- 
 
of 25 places. As a result of this desire to minimize the time, a large number 
 of separate cases, each requiring a different procedure, must be distinguished 
 by control in floating point addition. 
 
 7.1 Sign Propagation for Floating Point Addition 
 
 The special floating point addition may be regarded as one in which 
 both M and the cyclic shifted f (AQ) are positive. The result of this addition 
 in the stored carry type of adder will always be in range if the accumulator 
 carries were assimilated before the operation (this is necessary anyway to 
 allow cyclic left shifts), and we cyclically right shift in the same operation 
 as we add. For, in this case, the sum is representing using an extra carry 
 digit which is shifted into one of the carry storage F elements. However, 
 there remains one correction. M was represented as a positive number, so this 
 will only be arithmetically correct if a "borrow" is subtracted from the last 
 d base four digits of register Q whenever M is negative. 
 
 This is done by arranging for the borrow to propagate over two or 
 four bits of Q and using the corrected digits of Q, to cyclic shift into A. 
 To allow the borrow to propagate further, we use a borrow storage F element in 
 Q and R, so arranged that this will remain one until the propagation is terminated. 
 
 The condition for starting the borrow is simply to propagate when f (M) 
 is negative and we are adding, or when f(M) is positive and we are subtracting. 
 
 7.2 Discussion of the Separate Cases Arising on Floating Point Addition 
 
 d = eA - eM 
 
 Case 1 d > kk 
 
 Proceed to the next instruction. 
 
 Case 2 - kk > d > 23 
 
 Step 1 A— ►R; Q-*Sj load operand in M 
 Step 2 S-#A; R-+Q 
 Step 3 Clear S$ A-*R 
 
 -15- 
 
Step 4 S + M-iA 
 
 Step 5 Shift A right d-22 places; R-*M 
 
 Step 6 M + S =>A 
 
 Step 7 Assimilate A— *R; Q-*S 
 
 Step 8 S + Propagated sign of M-*A; R— »Q 
 
 Case 3 d = 22 or 23 
 
 Step 1 If d = 22, we shift A,Q right one place 
 
 Step 2 A-tR; Q-*S 
 
 Step 3 (S + M)-*A; R-*Q 
 
 i * 
 
 Step 4 Assimilate A-*R; Q— #S; x* — *S.. 
 
 Step 5 Sign of operand x2~^ 4 + S-*A; K-tQ 
 
 Case 4 22 > d > 12 
 
 Step 1 A-lSj Q-#6 
 
 Step 2 Shift right cyclically 23-d places 
 
 Step 3 Add operand and arrange for sign propagation 
 
 Step 4 Shift right cyclically d places 
 
 Case 5 12 > d > 
 
 Step 1 Shift left cyclically d places 
 
 Step 2 Do step 3 case 4, etc. 
 
 Case 6 d = 
 
 Step 1 Just add without shifting 
 
 Case 7 -22 < d < 
 
 Step 1 Shift right d places 
 
 Step 2 Add 
 
 Case 8 d = ^22 
 
 Step 1 Shift left one place 
 
 Step 2 Clear S. A-*R 
 
 Step 3 (M + S)-*A; R-*Q 
 
 Step 4 Add propagated old sign digit of A to A— *S Q— fcR 
 
 -16- 
 
Case 9 d = -23 
 
 Step 1 Steps 2, 3, k of case 8 
 
 Case 10 -kk < d < -2k 
 
 Step 1 Shift right - d -23 places 
 Steps 2, 3, k of case 8 
 
 Case 11 d < -kk 
 
 Step 1 Clear S, R 
 
 Step 2 (S + M)-f A R-»Q 
 
 At the conclusion of the first part the A, Q number is assimilated; 
 shifted right one place if too large and the two final digits of Q cleared to 
 zeros . 
 
 7.3 Notes 
 
 1„ The description is modified in the obvious way for subtraction, 
 except that now where necessary the sign of m is propagated. 
 
 2. The exponent is dealt with in the straight -forward way. It has 
 an allowed range of + 128 in the eA register. The overflow 
 indicator is set when necessary. 
 
 3. When the result of an addition is not precise, then an indicator 
 is set. 
 
 k. A precision indicator may also be kept in the arithmetic 
 exponent unit its function being to indicate the position 
 of the least significant digit f (A,Q). 
 
 -IT- 
 
8.0 Construction Details of the Arithmetic Unit 
 
 This will consist of a number of units, many of which will he 
 identical. Each unit will correspond to all the F elements, and selectors and 
 adders corresponding to a single base four digit. The first four and last three 
 such units will he special so that the "end connections" can be incorporated. 
 Thus the MAU may be considered to split into 23 units of which 16 are identical. 
 
 The carry generator is a special unit because its base h elements 
 vary according to the in digital position. It has to be connected with each 
 unit. 
 
 The logical diagram of one of the standard units is almost directly 
 that of the diagram of Section 2.1. The selectors and F elements are given in 
 the circuit book. The adder is made using the "relation" described in Report 80 
 and "the equations follow of a single base four adder. 
 
 8.1 Boolean Equations for Relation Adder 
 
 Let x and XL be the two wire output of the level restorer connected 
 to the A adder. 
 
 3 2n+l " X 2n+1 * a 2n+l + ^n+l ' *2n+l 
 
 S 2n+1 ~ X 2n+1 ' a 2n+l + X 2n+1 ' a 2n+l 
 
 I I i l : i i i r sag 
 
 t 2n = a *2n + X 2n+1 ' a 2n-t-l 
 
 *2n ~ a *2n ' a 2n+l + a 2n+l ' X 2n+1 
 
 S 2n+1 " a 2n+l ® X 2n+l 
 
 Internal Carry 
 
 S 2n ~ X 2n* a 2n + X 2n ' a 2n 
 
 Sr> = x_ . a^ + x_, a„ 
 
 2n 2n 2n 2n 2n 
 
 s 2n = x o~ © a c 
 
 Y 2n " S 2n *2n + S 2n t 2n 7 
 
 Y 2n-1 " S 2 n-lVi rS 2n-lVl j Y 2n-1 = S 2n-l® U 2n-l 
 
 Z = S TI 
 
 2n-2 2n-l 2n-l Output Carry 
 
 -18- 
 
Notes: 
 
 1. Double underlining indicates AND circuits connected to two 
 OR circuits. 
 
 2. Single underlining indicates outputs, i.e., Y ,Y , Z . 
 
 3. Each input is driven directly from a level restorer or F 
 element emitter follower. 
 
 h. Each output can drive two emitter followers of the following 
 selector. 
 
 5. The relation a* a n = is assumed and a relation y_ 
 
 J 2n 2n+l ,7 2n-l 
 
 Ap p = is generated. 
 
 6. In the standard units, the adder is made using diode matrix logic, 
 
 7. Some of the "end units" use transistor AND OR complexes, to 
 increase the fanout and reduce the voltage dispersion. 
 
 8.2 Carry Generator Circuit 
 
 The carry generator is permanently connected to register A and A* 
 and digits Q . ,.Q. Q* and Q£ of register Q. It generates for each base k 
 position of A, the incoming carry that results when all the carry digits to 
 right are assimilated. The adder at the output of A is then used via the 
 selector from M to produce the final sum. The carry outputs of the adder are 
 disregarded, although they could be used to check the action of the carry 
 generator. The carries from C^ through C _ require generating, as the 
 assimilator of Q deals with the remaining digits. 
 
 Boolean Equations of the Carry Generator: 
 
 (1) 
 
 C kn = a Wl a W a \n+2 + a %n 
 
 (1) 
 
 P lm = a 4n+l a ^n+2 a kn+3 a kn+k 
 
 (1) 
 
 Ckk = Hh + ( 3i q 2 q *2 + q i q 2 q 5 V% 
 
 -19- 
 
 n = 0,2,... 10 
 
(2) 
 
 C 32 
 
 = 
 
 (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) 
 
 C 32 + P 32 C 36 + P 32 P 36 C ko + P 32 P 36 7 ko C hk 
 
 (2) 
 
 
 (1) (1) (l) (l) (1) (1) 
 
 C 8+12n 
 
 — 
 
 C 8+12n + P 8+12n C 12+12n + P 8+12n P 12+12n C l6+12^ 
 
 (2) 
 
 
 (1) CD (1) / 
 
 P 8+12n 
 
 ~ 
 
 P 8+12n ' P 12+12n P l6+32n Wor values 
 
 (2) 
 
 P 12n+4 
 
 = 
 
 \ of n=0 and 1 
 
 p(D 
 
 P 12n+^ / 
 
 (3) 
 
 = 
 
 (2) 
 
 (3) 
 
 C 32 
 
 = 
 
 (2) 
 C 5 2 
 
 (3) 
 
 C 20 
 
 = 
 
 (2) (2) (2) 
 C 20 + P 20 C 32 
 
 (3) 
 
 C 8 
 
 9B 
 
 (2) (2) (2) (2) (2) (2) 1 
 C 8 + P 8 C 20 + P 8 P 20 C 32 
 
 C 8+12n 
 
 = 
 
 (3) 
 
 C 8+12n 
 
 CO 
 
 = 
 
 (1) (2) ^ (3) 
 C k+12n + P Wl2n ° C 8+12n 
 
 (M 
 
 
 (1) (1) (1) (1) (2) (3) 
 
 C +12n 
 
 ■ 
 
 C 12n + P 12n C Wl2n + P 12n P 12n-+4 C 12n+S 
 
 n 
 
 aa 
 
 3, 2, 1, 
 
 (5) 
 
 
 PO 
 
 C W 
 
 = 
 
 8 • c i, m 4 ' a 4n+3 "W 
 
 (5) 
 
 C hn+h 
 
 ss 
 
 
 where n 
 
 = 
 
 0, 1, o . o 10 
 
 -20- 
 
(5) 
 
 c 
 
 
 
 (5) 
 
 c -i 
 
 (*0 - 
 
 = g. c, 
 
 M 
 
 = g« c. 
 
 X 
 
 x o 
 
 where g is the selector gate 
 
 Further notes: 
 
 1. This generator is made entirely with transistor AND OR complexes 
 and each line corresponds to a single AND OR complex. 
 
 2. The exponent indicates the level of logic, so that the final 
 outputs from the selector are those from 5 levels of logic, 
 with a maximum voltage dispersion of 1.^5 v « 
 
 3. Component Estimation 
 
 Logic Level 
 
 Transistors 
 
 Diodes 
 
 1 
 
 97 
 
 157 
 
 2 
 
 29 
 
 51 
 
 3 
 
 11 
 
 21 
 
 k 
 
 40 
 
 76 
 
 5 
 
 81 
 
 131 
 
 TOTAL 
 
 260 
 
 kl6 
 
 We also require carry suppression circuits which take 22 transistors 
 and 22 diodes, and cause the carry outputs of the A adder to he made 
 zero when signal g is present. 
 
 The load on the inputs is as follows: 
 - 2EF 
 
 a Wl 
 
 a W = 2EF 
 
 a kn+k 
 
 a* 
 2n 
 
 l 4n+3 
 
 2EF 
 
 a* 
 
 kn 
 
 2EF 
 IEF 
 1EF 
 
 All intermediate values drive 3 o r fewer emitter followers. 
 
 (5) 
 
 k. It should he noted that C 1 © A , gives the true sign of register A, 
 and "because the carry generator is permanently connected to A, 
 the true sign is available shortly after A has been changed. 
 
 -21- 
 
9.0 Requirements for End Connections 
 
 The scheme for arithmetic so far outlined requires that: 
 
 1. f(A,Q) can he shifted right arithmetically; i.e., with sign 
 copying on the left of A, losing digits on the right of Q, 
 and assimilating stored carries from A as the corresponding 
 digits are moved into Q. 
 
 2. f(A,Q) can be shifted left arithmetically; i.e., zeros must be 
 inserted in the right hand positions of Q and overflow must be 
 sensed as digits are lost from the left hand end of A. 
 
 3. f (A,Q) can be shifted right and left cyclically, with the cyclic 
 right shift propagating borrows when necessary. 
 
 4. The operation [f (A, Q)+2f (M}J A must be performed correctly even 
 though [ f (A,Q)+2f (M)] may exceed 3. 
 
 5. Quotient digits must be capable of being inserted in the right- 
 most digits of Q and the resulting borrows propagated along Q. 
 
 6. f(A) must be capable of being shifted right and left as a single 
 length shifting register. 
 
 -k-6 
 
 7. 2 must be added to a sum whenever a negative multiple of M 
 
 is manufactured by a selector as a one's complement. 
 
 The correct operations are attained at the ends of the registers by a 
 two-step process. The first step is to generate all the inputs required for all 
 the shifting options. This step may have a voltage dispersion and delay as large 
 as the psuedo-adder in a standard base four unit. The second step is to pick 
 out the appropriate digit from the array of possible digits by means of a 
 selector. 
 
 In the following sections, we shall describe only the connections for registers 
 A,Q. The connections for S, R are similar. 
 
 -22- 
 
9. 1 Exterior Connections to the Main Arithmetic Unit 
 
 There are a number of connections from the digits in the arithmetic 
 unit to the control. Thus the digits Q},,.-Q},r select steps in multiplication; 
 digits A -,-A(- are used in the division predictor, etc. In a detailed logical 
 design these must be taken into account because they increase the loading on 
 certain elements. They will not be further considered here,, 
 
 9.2 Interconnections between A . and Q 
 
 The psuedo— adder connected to A. _ and A. ,- is the only one which is 
 logically different from those in the standard base four units. It has as input 
 B. . instead of Aj*. and it does not have a connection to a less significant adder. 
 Thus it does not use the relation kfu A. _ = but generates the relation 
 xj* x, = 0. B. k i s defined to be one whenever the M selector uses a complement 
 of M or 2M. It can be generated trivially, by taking the two selector drivers 
 to an OR element the output of which is connected to a two-wire level restorer. 
 
 There exist in Q, . two carry storage digits Q* and Qg. These are 
 connected together with Q_, Q_, Q_, Q^ and Aj*. to an assimilator whose outputs 
 are xj*. and y , y , y_, y^. The assimilator utilizes the fact that the only 
 carry input for which the psuedo adder relation is not true is least significant 
 non-zero carry. This fact is true because Q* or Qj* can only be non-zero if 
 the previous operation were a right shift and x£i (the least significant carry) 
 were shifted into one of them. 
 
 The connections in the selector are given in a later section. 
 
 9.3 Interconnections between A, and Q . 
 
 The psuedo adder connected to A and A_ generates two extra outputs 
 
 x „ and x , which are used when arithmetically shifting right. In fact, if M n 
 -d -5 -i 
 
 is the selected sign digit from register M 
 
 X -2 = A -1 @M -1 
 
 x , - A n + M t . 
 -5 -1 -1 
 
 -23- 
 
Thus x ._ which is copied twice when shifting four bits right, is generated with 
 very little voltage dispersion and sufficient fanout is easily obtained. 
 
 There is a subtractor which is connected to digits Qj,-, • • 'fy,/- an d Qjtr- 
 This produces a difference yj, T «« »Jhfi together with the borrows jf and y£, . 
 By assigning a negative value to the borrows we can represent the difference 
 as 
 
 Y h\> J h2' y ky 7 hk> y ky J k6 
 or Q 1+1 , Q^ 2 , y% 2 , Y^y 7]^$ Y^y Y^ 
 
 or Q 1 ^ 1 , Q^ 2 , Q^, Q^, yj^, y^, y^. 
 
 The first representation is used in division, the second when cyclic right shifting 
 four binary places, and the third when cyclic right shifting two places. 
 
 9.^- Boolean Equations of Assimilator Connected to Q _ 
 
 Inputs Qj*, Q*, AJl , CL, (^L, Q,, Qr, and their complements. 
 
 C 3 = QJ Q^ \ 
 
 c 3 = % + % 
 
 C 2 = Q{ Q^ Qj + Q* 
 
 c 2 = Q* QJ + Q* q, k + Q* Qj 
 
 J 
 
 Y h = %% + % % \ 
 
 y 5 = C 3 Q 5 + C 5 S 
 
 y 2 = c 2 "^ + c 2 q 2 
 
 C l " C 2 ^ 
 
 C 1 = C 2 + Qg 
 
 / 
 
 -aH- 
 
*1 - C 1 Q 1 + C 1 Q 1 
 
 where y. are the assimilated Q. outputs and x£, the carry out which 
 in a not shift operation would go to SJj,. 
 
 9.5 Boolean Equations of the Six Bit Subtractor of Q, . 
 
 In the equations given below, QJ^ should really be written as 
 Qj±6 + ^ ♦ C + M ' D • UL, and Qj*> as its complement 
 
 where 
 
 M = sign of M when adding or complement when subtracting 
 s 
 
 C = condition for cyclic shifts 
 D = division condition 
 UL = shift left condition 
 
 \k = %6 + %6 + %5 
 \ 2 = %6 %6 \5 \k %3 
 
 
 \l = h k2 + %2 
 
 *k6 = %6 %6 + %6 %6 
 
 -25- 
 
y 45 = 
 
 "U5 © V 
 
 y k3 • 
 
 S 3 © S3 
 
 y kl - 
 
 \i ® Si 
 
 y kk - 
 
 s*®v 
 
 y k2 = 
 
 b te©Sa 
 
 y% k - 
 
 V 
 
 ^2 - 
 
 V 
 
 According to the demands of other elements connected to this end of Q, 
 it will be necessary to increase the fanout of various quantities such as Qw-j ^Uo' 
 This depends on certain unknown details, and is not shown above. 
 
 9.6 Selector Boolean Equations 
 
 Let the outputs of the adder be 
 
 x.; i = -2 . . .kk a.nd x*; i j -2, 0, 2, . . .k-2 . 
 Let the outputs of the & . assimilator be 
 
 Y ± > i = h 2, 3, h and xj^ 
 
 and the outputs of the Q n assimilator be 
 
 Let the selector drivers be named as follows: 
 U Interchange 
 UR Shift right one place 
 URR Shift right two places 
 UL Shift left one place 
 
 -26- 
 
ULL Shift left two places 
 
 C Cause cyclic shifting 
 
 H Cause single register shifting 
 
 D Division 
 
 Z Z Two quotient digits 
 
 The general selector Boolean equations are as follows: 
 The gated input to: 
 
 S n = W U + W* + X n-4*™ + X n+2 #UL + X ^ #ULL 
 
 R n = X n-2' U + %-2 m + %-k' WR + W UL + Q ta + 4' ULL 
 for all values of n not explicitly given below. 
 
 Then the gated input to: 
 
 s kl = Q ^' U + x if3 ,UL + yi'^L-3 + x 59 -UR + x 37 • UER 
 
 s k 2 = <V' U + x kk mUL + 7 2 mJ!LL9 * + X ho' m + x 38* ' URR 
 
 s $2 = + x fo #UL + Ho' m + x 38 " ^ 
 
 Sw = Qj^'U + y 1 'UL-H + y -ULL-H + x^-UR + x • URR 
 
 S l^ = %6' V + ^2^'^ + y^* ULL *S + x^.UR + x^ Q . URR 
 
 s tU = X V U + x ?2 ' m + x $o' nBH 
 
 R = x »U + y *UL + Q»ULL + x^,«UR + x^ .URR 
 
 R 2 = X 0* U + y ^ ,UL + Q 6* ULL + X ^ ,UR + x 42 ,URR 
 R* = x*-U + x| 4 -UR + x£ 2 -URR 
 
 TL^ = x.-U + Q S 'UL + Q 'ULL ++J., *UR + x^ -URR 
 R^ = x 2 -U + Q 6 «UL + Qg-ULL + y . UR + x^ -URR 
 R£ = x*-U + xj^ ^URR 
 
 -27- 
 
R 
 
 n 
 
 R 
 
 ^ 
 
 R 
 
 kh 
 
 R 
 
 ^5 
 
 = x n _ 2 -U + y n+2 *UL + ^-ULL + Q^UR. + Q^jjURR for n = 59-^2 
 
 = x 1 ^ 1 • U + J kf - -UL + x_ x -ULL-C + Q^ 1 *UR + Q^ -URR 
 
 = x h2 • U + y^ 6 -UL + x Q 'ULL'C + Q^- UR + Q^-URR 
 
 = x^ -U + x_ 1 'UL-C + x • ULL-C + Q w *UR + Q^,- URR +Z • UL • D 
 
 R>,£ = x ),), *U + x_ • UL-C + x . 'ULL-C + Q,,,, 'UR + Qj.^-URR +Z • UL • D 
 
 \6 
 S -l 
 
 %h 
 
 "0 
 
 +1 
 
 + yJ^UR-C + yJ 2 -URR.C 
 
 = y * U + x * UL + x, • ULL + x • UR-C + x -URR-C 
 11 5 -5-5 
 
 + y^-UR-C + y^-URR-C 
 s r> = Jo' * U + x • UL + x. • ULL + x • UR-C + x •URR'C 
 
 % 
 
 .2 ~* - -3 
 + y^UR-C + y^-URR-C 
 
 s s 
 
 x* • UL + xj • ULL + x* 2 « UR 
 
 S-, = y • U + x, -UL + x,_ «ULL + x • UR + x ^URR-C 
 15 5 n -1-5 
 
 + y U5 
 
 •URR'C 
 
 y k - 
 
 s l 
 
 U + x. »UL + Xg -ULL + x «UR + x -URR.C 
 
 + y^-URR-C 
 + x* -UL + x* -ULL + x* -UR + x* •URRoC 
 
 
 
 -2 
 
 -28-