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 To renew call Telephone Center, 333-8400 
 
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 L161— O-1096 
 
UIUCDCS-R-77-872 
 
 cm 
 
 UILU-ENG 77 1721 
 
 1 
 
 BURSTLOCK: A DIGITAL PHASE-LOCKED LOOP 
 USING BURST TECHNIQUES 
 
 by 
 
 COLAN MICHAEL ROBINSON 
 
 May 1977 
 
 y 
 
 Libra 
 
 
 
 DEPARTMENT OF COMPUTER SCIENCE 
 UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN 
 
 URBANA, 
 
Digitized by the Internet Archive 
 in 2013 
 
 http://archive.org/details/burstlockdigital872robi 
 
UIUCDCS-R-77-872 
 
 BURSTLOCK: A DIGITAL PHASE-LOCKED LOOP 
 USING BURST TECHNIQUES 
 
 BY 
 COLAN MICHAEL ROBINSON 
 
 May 1977 
 
 This work was supported in part by Contract No. N00014-75-C-0982 and was 
 submitted in partial fulfillment of the requirements for the degree of 
 Master of Science in Computer Science at the University of Illinois. 
 
 Department of Computer Science 
 
 University of Illinois at Urbana-Champaign 
 
 Urbana, Illinois 61801 
 
Ill 
 
 ACKNOWLEDGMENT 
 
 The author wishes to express his appreciation to his advisor, 
 Professor W. J. Poppelbaum, for proposing and supporting this research, 
 and to the members of the Information Engineering Laboratory, who were 
 unfailingly generous with their time, advice and friendship. Thanks 
 are also due to Al Irwin for his experienced advice, Tom Kingery for 
 packaging the project, June Wingler for the typing, and Stan Zundo for 
 drafting lessons. Finally he would like to thank the National Research 
 
 Council of Canada, which has supported his studies for the past two 
 
 ii 
 
 in 
 II 
 
 years. 
 
 ii 
 
iv 
 
 TABLE OF CONTENTS 
 
 Page 
 
 1 . INTRODUCTION 1 
 
 2 . THE PHASE-LOCKED LOOP 2 
 
 2 . 1 Introduction and Background 2 
 
 2 . 2 PLL Components 5 
 
 2 . 3 PLL Parameters 6 
 
 2 . 4 Capture Behavior 8 
 
 2 . 5 Further Considerations 12 
 
 3 . BURST REPRESENTATION 13 
 
 4. THE BURSTLOCK CIRCUIT 17 
 
 4.1 BURSTLOCK Operation 17 
 
 4 . 2 BURSTLOCK Parameters 22 
 
 4.3 The BURSTLOCK Receiver 26 
 
 5. COMPARISON OF BURSTLOCK AND THE CONVENTIONAL PLL 30 
 
 LIST OF REFERENCES 32 
 
 APPENDIX 33 
 
1. INTRODUCTION 
 
 The past two decades have seen a revolution in the way in which 
 information is processed. Today computers and computer technology are 
 involved in almost every facet of our daily lives. The design simplicity, 
 low cost and high reliability of digital circuitry developed for computer 
 systems have produced an increasing trend towards the use of digital 
 circuits in real-time applications, long the sole province of analog 
 circuit techniques. 
 
 As a result, there has ;been a search for methods of digital data 
 representation which can combine high speed and reliability with noise 
 tolerance and low-cost processing elements. One proposed solution is 
 that of unary processing, in which the value contributed by a bit of data 
 is independent of its position. The data may be encoded either in a 
 stochastic or deterministic manner. In unary processing, it is typical 
 to employ averaging to improve the precision and noise immunity of the 
 encoding. 
 
 This thesis will describe BURSTLOCK, a digital phase-locked loop 
 implemented using a deterministic subclass of unary processing called 
 Burst Processing. It is employed in a receiver to demodulate commercial 
 FM broadcasting. It will be shown that BURSTLOCK provides a number of 
 advantages over conventional phase-locked loops, both practically, as 
 it consists of only a small number of digital components, and theoretically, 
 by reducing the interdependence of loop parameters to provide a broader 
 range of design tolerance when attempting to maximize conflicting quantities. 
 
2. THE PHASE-LOCKED LOOP 
 
 2.1 Introduction and Background 
 
 A phase-locked loop (PLL) is a feedback system which attempts to 
 synchronize a voltage-controlled oscillator (VCO) with an input signal. 
 Figure 2.1 gives a basic block diagram of the PLL, which consists of a 
 phase comparator (PC), low pass filter, amplifier and VCO. 
 
 With zero input, the VCO operates at a set frequency referred to 
 as the "quiescent frequency" (f n ) . The phase comparator produces an output 
 that is proportional to the phase difference between the input and VCO 
 signals. This output is filtered, amplified and applied to the control 
 input of the VCO, forcing the VCO frequency to vary in the direction that 
 will decrease the phase difference between the two signals. If the 
 difference between the input frequency and the quiescent frequency is 
 sufficiently small, the VCO will be forced closer to the input frequency 
 until the two frequencies are equal. When this occurs the loop is said 
 to be "in lock." The range of frequencies over which this locking behavior 
 can occur is called the "capture range." 
 
 If the input frequency changes once the loop is locked, the VCO 
 will follow the change due to the feedback properties of the system, as 
 long as the deviation of the input is not too large. The range of frequencies 
 over which the PLL will remain locked is called the "lock range." 
 
 I l is necessary that a phase difference between the input and 
 VCO signals Ls maintained in order to generate a control voltage sufficient 
 
/A 
 
 
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 1 
 
 1 
 
 Lowpass 
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to shift the VCO from f to the lock, frequency. This static phase error 
 is inversely proportional to the gain around the loop, represented in the 
 diagram hy an amplifier with gain A, where A represents the change in VCO 
 frequency per unit phase error. 
 
 Descriptions of phase-locked loops can be found dating back to the 
 twenties and thirties. However, the first important practical application 
 came in the early fifties, when PLL's were used to reconstitute the color 
 subcarrier in color television signals. "Flywheel" synchronization used 
 the property that if the input is removed, the VCO will drift away only 
 slowly from the lock frequency. Thus the color oscillator at the receiver 
 can be synchronized to that at the transmitter by locking on to a short 
 color burst transmitted once each frame, and relying on the memory of the 
 loop to coast through the period between bursts [9]. 
 
 The application of the PLL to radio reception became important with 
 the inception of the American space program. Narrow band signals trans- 
 mitted from a satellite could be received despite uncertainty about the 
 signal frequency, which could range over a frequency interval 1000 times 
 the signal bandwidth due to transmitter drift and Doppler shift, because of 
 the tracking action of the PLL. 
 
 At the present time the PLL is widely used for demodulation in high 
 quality FM receivers due to its superior performance over a conventional 
 discriminator. In this application the output of the system is the 
 filtered output of the phase comparator, which corresponds to the program 
 signal as it forces the VCO to follow the modulation of the carrier. 
 
 By inserting a frequency divider in the feedback loop between the 
 VCO and the phase comparator, the PLL functions as a frequency multiplier. 
 
It can also act as a frequency translator by adding an offset voltage to 
 the VCO control input. 
 
 The PLL can be made to lock on to only one of several signals at 
 its input by setting f~ of the VCO correspondingly. The undesired 
 frequencies are attenuated, thus improving the signal-to-noise ratio. 
 
 2.2 PLL Components 
 
 The phase comparator closes the feedback loop, producing an output 
 which depends on the phase difference between the input and the VCO signal. 
 Since it cannot distinguish between different cycles of the signals, its 
 output must be a periodic function of the phase difference, with period 
 equal to 2tt radians. Most practical phase comparators have an output that 
 is directly proportional to the sine of the phase error. However, the 
 sinusoidal nonlinearity of the phase error <$> is usually disregarded by 
 
 Ei 
 
 assuming a small <J> so that the loop operates in the region where sin <\>„ 
 it, Ei 
 
 is approximately equal to <J> . This assumption is accurate to within 5% 
 for <J> < tt/6. Since the PC converts a frequency difference into a phase 
 
 Ei 
 
 difference, and phase is the integral of frequency, the PC functions as an 
 integrator. 
 
 It is necessary that the VCO be highly linear over a wide range, 
 with high phase stability. Depending on the application certain requirements 
 may be sacrified to improve others, as there is conflict between them. 
 
 The order of the loop is equal to the number of finite poles in the 
 open-loop transfer function. A first-order loop contains no filter. (The 
 integrating action of the PC contributes one pole.) Second-order loops, 
 which contain one integrator, are the most common. High-order loops are 
 very sensitive to circuit parameter changes, difficult to stabilize and 
 
unnecessary in most PLL applications. The lowpass characteristic of the 
 filter F(s) attenuates fast changes in the phase error due to noise or 
 phase jitter in the input signal. 
 
 The amplifier shown in Figure 2.1 may or may not be physically 
 present and simply represents the combined dc gain of all the components 
 in the loop. 
 
 2.3 PLL Parameters 
 
 The lock range R^ is the distance from f that the VCO, once locked, 
 
 can be moved while still maintaining lock. For a linear phase comparator, 
 
 the lock range is equal to ttA radians per second [5]. For a sinusoidal 
 
 phase comparator, since the sine function cannot exceed 1, the lock range 
 
 is equal to A radians per second [2], This value will be used for further 
 
 derivation, following the convention in the literature [2,5,12]. The 
 
 capture range R is the maximum distance from f that the loop will lock 
 
 on to an input signal from an unlocked state. R is always less than or 
 
 equal to R . 
 L 
 
 It should be pointed out that when a frequency step is applied to 
 the input of a locked loop, the loop may lose lock for a few cycles if the 
 frequency variation is too large, even though it remains within R^ . There 
 is a maximum rate of input frequency change for which the loop will not 
 lose lock temporarily. For a second-order loop, by applying the final 
 value theorem to the expression for the phase error, this rate may be shown 
 to be equal to the square of the natural frequency of the filter (units 
 of radians per second per second) [2]. 
 
 As mentioned above, when the loop is locked, there is a static 
 e error required to keep the VCO at the lock frequency. In many cases 
 
a small phase error is desired, but for discriminators, where this phase 
 
 error is the output, this is not necessarily the case. For a first-order 
 
 loop with a lock frequency f and a quiescent VCO frequency f , the static 
 
 L Q 
 
 phase error is (f -f )/A. The phase error can be reduced to zero by using 
 a third-order loop [12]. 
 
 Another useful loop parameter is the loop bandwidth B , which is 
 
 Li 
 
 defined as the dB frequency of the open-loop gain. For a first-order 
 loop or a second-order loop with cutoff frequency greater than B , the gain 
 
 Li 
 
 decreases with frequency at 6 dB/octave due to the 1/s term provided by 
 the integrating action of the PC, and thus B = A. In this case R = R . 
 For FM detection, B must be large enough to track the modulation. 
 
 J_i 
 
 However, the bandwidth should be as small as possible to attentuate noise 
 in the input. Any change in B will also affect R^ and R r , since all these 
 quantities depend on A. 
 
 If the cutoff frequency of the low-pass filter is reduced below A, 
 the attenuation of noise can be increased while keeping R^ the same. How- 
 ever, there is a penalty to be paid for the decrease in B . The system 
 
 L» 
 
 response to an input frequency change becomes an underdamped ringing. Also 
 R is reduced. For a simple RC filter the reduction in R is approximately 
 equal to the reduction in B caused by the decrease in filter bandwidth. 
 
 Li 
 
 Using a lag network filter the reduction in R is approximately equal to 
 the square root of the B reduction [5]. Moschytz [7] has derived a 
 
 Li 
 
 general parametric approximation to R : R = A|F(R )|. Since F(R C ) cannot 
 be greater than unity, R cannot be greater than R^ (R, =A) . Note that the 
 gain of an active filter is included in A. 
 
8 
 
 It is often convenient to think of a PLL as acting as a bandpass 
 
 filter on the input signal, as in the satellite communications application 
 
 described above. The filter has a center frequency equal to the input 
 
 frequency and a noise bandwidth B„, on each side. For a first-order loop 
 
 N 
 
 B = A/4 Hz. For a second-order loop with F(s) = 1 + a/s, B = (A+a)/4 [12]. 
 
 In most applications it is desirable to have both a wide R and a 
 narrow B . It can be seen, however, that these requirements conflict with 
 each other. 
 
 2.4 Capture Behavior 
 
 The capture behavior of a PLL is extremely complicated and difficult 
 to describe mathematically. However, it may be easily understood in a 
 qualitative manner. 
 
 Consider a first-order loop with a linear phase detector. For the 
 
 first-order loop R = R . Figure 2.2 describes the operation of the 
 
 loop [5]. The VCO frequency appears on the vertical axis and the phase 
 
 difference between the VCO and the input signal on the horizontal axis. 
 
 Each curve represents the VCO frequency as a function of the phase difference 
 
 for a particular choice of f , and is periodic in 2tt . The horizontal axis 
 
 represents the frequency of the input signal. Thus locking can occur 
 
 only if the curve for a given f intersects the axis. For example, the 
 
 curve for f _ crosses the axis twice in the interval to 2tt . As shown, 
 
 only one of these intersections is stable, the other corresponding to 
 
 positive rather than negative feedback. The distance from the vertical 
 
 axis to the intersection is the static phase error. The lock range can be 
 
 seen to be (f .-f „)/2. If the VCO operates at t M , lock cannot be achieved. 
 Q4 Q2 Ql' 
 
 The operating point will move along the curve in the direction of the arrow, 
 prodn' Lng frequency modulation. 
 
o 
 
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10 
 
 It is instructive to consider the operation of the loop when the 
 input frequency is outside the capture range, as on the f curve. Since 
 the VCO and input frequencies are different, the output of the phase 
 comparator is a beat frequency. If the VCO is modulated away from the 
 input frequency the beat frequency increases and the operating point 
 moves rapidly, whereas if the VCO is modulated toward the input frequency 
 the beat frequency decreases and the operating point moves more slowly. 
 The output of the phase comparator can be shown [5] to be a series of 
 back-to-back exponential curves with flat regions as the operating point 
 hesitates at its closest approach to the input frequency, and sharp cusps 
 as the VCO moves rapidly at its furthest excursion. 
 
 When the more common sinusoidal phase comparator is used, the 
 triangular shape of the curves becomes sinusoidal, but the operation will 
 be similar otherwise [2,12]. So far, the first-order loop, in which 
 IL = R = B , has been described. The discussion may be extended to the 
 second-order loop. If the frequency difference between the VCO and input 
 signals is less than B , locking will proceed directly and almost 
 
 J_i 
 
 instantaneously, as in the first-order loop [2]. When the operating 
 point does not intersect the input frequency axis the phase error looks 
 like a series of cusps as before. Because of the asymmetrical shape of 
 the waveform, it contains a dc component. This was why the first-order 
 loop tended to linger at its closest approach to lock. The filter in the 
 second-order loop integrates this dc component, pushing the VCO closer 
 to the input frequency. For a second-order loop with a perfect integrator 
 the capture range is theoretically infinite. With a more normal type of 
 loop filter the capture range is proportional to the filter response as 
 a 1 ready descr i bed . 
 
11 
 
 Viterbi [12] has used an analog computer to produce a number of curve 
 families of the type in Figure 2.2 for second-order loops with different 
 filter characteristics. These curves show a spiral tendency in the path 
 the operating point takes due to the underdamped ringing described above. 
 
 A study of the capture behavior of a PLL leads to another quantity 
 used to characterize the loop: the "capture time" T . This is the time 
 taken for the loop to lock once the input signal is applied. For a first- 
 order loop, if capture is possible, T will be on the order of 1/A 
 seconds [2]. For a second-order loop with a loop filter characterized 
 by a natural frequency w and a damping factor £ , if the input signal is 
 
 within B T then T_ is of the order of l/w„ seconds. If this condition is 
 L C N 
 
 not true, an explicit formula for the capture time is somewhat difficult 
 to derive. Gardner [2] gives an approximation derived by Viterbi for a 
 
 difference between input frequency and VCO frequency of Aw radians/second: 
 
 2 3 
 T = Aw /(2Cw ). Thus acquisition is faster with a wider loop bandwidth. 
 
 L* IN 
 
 Note that if the VCO had previously been tracking another frequency, Aw 
 
 would be measured from the VCO frequency, not from f . Thus R extends 
 
 on either side of the current VCO frequency, but cannot exceed the limits 
 
 of R, which is centered on f . 
 L Q 
 
 The capture time can be exceedingly long if Aw is large compared 
 with A or B . As an example [2], consider a high-gain second-order loop 
 
 with C = 0.707, a commonly selected value, and a frequency difference of 
 
 2 3 
 
 Af Hz. Gardner shows that T is approximately equal to 4.2 (Af) /B 
 
 seconds. For a narrow-band loop with Af = 1 KHz and B. T = 10 Hz, 
 
 N 
 
 T = 1 hr. 10 min. ! 
 
 Because of such long capture times a commonly used technique in 
 this type of situation is to apply a sweep voltage to the VCO to search 
 
12 
 
 for the input frequency. The maximum sweep rate is limited by B [12]. 
 Once lock has occurred the sweep voltage must be removed. Otherwise, if 
 the input signal fades out momentarily, the VCO will be carried away from 
 the lock frequency. Locking during sweep is by no means certain and the 
 loop must be designed carefully to give a high probability of capture [2], 
 
 2.5 Further Considerations 
 
 If the input signal to a first-order loop fades out, the VCO will 
 return to f . In a second-order loop, because of the integration of the 
 filter, the VCO frequency will tend to remain the same. Thus the loop may 
 be said to have memory. With a perfect integrator, the frequency will 
 never change. Using a realistic filter, the holding time is proportional 
 to the gain of the filter. This property is used in flywheel synchroniza- 
 tion as described above. 
 
 Some mention should be made of the relatively uncommon third-order 
 loop. Analysis is much more complex than the second-order case. Design 
 is also more complicated as the third-order loop is only conditionally 
 stable, whereas first and second-order loops are unconditionally stable. 
 However, the third-order loop is advantageous in some applications. The 
 addition of a second integrator also gives the loop an acceleration 
 memory. If the input signal has a constant acceleration, such as a 
 Doppler shift, when the signal fades out the loop will continue to track 
 at the same rate of change of frequency. This is particularly useful 
 in space communications. 
 
 A PLL is by no means the best way to measure the frequency of a 
 constant input. Its principal advantages are its ability to track the 
 'juency of a varying input and to improve the signal-to-noise ratio. 
 
13 
 
 3. BURST REPRESENTATION 
 
 Burst representation is a method of encoding information in pulse 
 form proposed by Professor W. J. Poppelbaum as a middle ground between 
 weighted binary and stochastic representations [10]. It retains the 
 noise tolerance and processing simplicity of stochastic schemes while 
 offering increased precision and speeds approaching that of weighted 
 binary. 
 
 In essence, Burst representation is a unary (unweighted) encoding. 
 A serial pulse stream is viewed as a sequence of n-bit blocks. The value 
 of each block is defined to be the fraction of the number of l's in the 
 block to the total number of slots, and can vary between and 1. If 
 negative numbers are required, they may be mapped into the range of the 
 representation, as in two's complement binary encoding, or a sign bit 
 may be transmitted separately. As the blocks pass through an n-bit shift 
 register, the value represented in the register provides an interpolation 
 between the values of successive blocks and thus is valid at all times. 
 No synchronization is necessary. 
 
 By selecting a value of n, the designer may trade off precision 
 and speed. The philosophy behind Burst processing is to select a low n 
 (typically 8 or 10) so that processing elements are simple and inexpensive, 
 and to obtain increased accuracy by averaging the result. The practic- 
 ability of this technique in a number of applications has been demonstrated 
 by members of the Information Engineering Laboratory. 
 
14 
 
 Decoding of Burst encoded information is accomplished by a block 
 sum register (BSR) , which is an n-bit shift register, each stage of 
 which controls a unit current source. The currents are summed on the 
 output bus to provide a quantized analog output proportional to the Burst 
 value contained in the register. Figure 3.1 shows a 5-bit BSR which 
 contains the value 0.6. Bursts may also be converted into weighted 
 binary by the use of a simple up-down counter. 
 
 As the BSR acts as an integrator with a finite memory, it is not 
 surprising that higher frequencies are attenuated by a low pass filtering 
 action. Obviously, with a clock frequency of f , frequencies higher 
 than f r /2 cannot be represented at all. Since the value in the BSR is 
 constrained to change by only 1/n in each clock period, a limit is placed 
 on the maximum amplitude at a given frequency. The cutoff frequency of 
 a BSR has been defined by Taylor [12] to be f /2n. At the cutoff 
 frequency the maximum amplitude of a signal is 2/tt . 
 
 There is no requirement that the l's in a block be contiguous, 
 although this may be advantageous in certain applications. If this is so, 
 it is termed a "compacted" Burst. A particular class of uncompacted 
 Bursts which will be of interest is Delta Block Encoding (DBE) , which is 
 analogous to conventional delta modulation. In this case the serial 
 inputs of a bidirectional BSR are tied to logical one and logical zero, 
 and the Burst input controls the direction in which the BSR shifts. In 
 each clock period the value in the BSR is either increased or decreased 
 by 1/n to correspond to the changing value of the encoded signal. 
 
 One obvious disadvantage of this scheme is that there is no way 
 to encode a constant value — the closest approximation gives granular 
 noise with an amplitude of 1/n. This can be remedied by providing two 
 
15 
 
 BURST 
 INPUT 
 
 SOURCE ( 
 VOLTAGE 
 
 
 
 ( ANALOG 
 OUTPUT 
 
 Figure 3.1 A 5-bit BSR 
 
 <D- 
 
 
 
 DBE 
 ENCODER 
 
 
 
 
 
 DECREASE 
 
 INCI 
 
 3EASE 
 
 
 
 
 \ 
 
 SHIFT 
 , LEFT 
 
 SHIFT 
 r RIGHT 
 
 
 1 
 
 1 
 
 1 
 
 
 
 
 
 
 
 
 
 
 
 Figure 3.2 Decoding a Tristate DBE-Encoded Burst 
 
16 
 
 control lines, one to increase the value in the BSR and one to decrease 
 it. If both lines are inactive, the BSR value remains constant. (The 
 situation in which the lines are simultaneously active is not permitted.) 
 This encoding will be termed "tristate" DBE, as there are three possible 
 actions to take in each clock period. Figure 3.2 shows the means by 
 which tristate DBE is decoded. 
 
 Although in some situations it may not be considered worthwhile 
 to use two lines instead of one merely to remove a small amount of noise 
 (which could just as easily be filtered out), this encoding is vital to 
 the concept of BURSTLOCK. In this case, the two control signals do not 
 originate at a single encoder which encodes an externally derived signal, 
 but rather are produced separately in order to encode the relationship 
 between two external signals. 
 
17 
 
 4. THE BURSTLOCK CIRCUIT 
 
 4.1 BURSTLOCK Operation 
 
 BURSTLOCK is a phase-locked loop designed using burst techniques [8] 
 From the discussion above, it should be clear that the design of a PLL 
 depends largely on the intended application. The BURSTLOCK circuit con- 
 structed was designed for FM demodulation, and in conjunction with 
 appropriate reception and output circuits forms a receiver that will pick 
 up commercial FM broadcasting. It will be shown that the BURSTLOCK design 
 has certain theoretical advantages over conventional PLL's. 
 
 Figure 4.1 shows the BURSTLOCK circuit. The system clock is not 
 shown on the diagram, but should be understood to input to all counters and 
 shift registers. All clocked components are positive edge-triggered. 
 
 Since all the information in an FM signal is contained in the 
 frequency, the waveshape may be adjusted to any convenient form. The input 
 signal is represented here by a pulse one clock period long produced when 
 the sinusoidal broadcast signal passes through zero with a negative slope. 
 The zero-crossing detector synchronizes the pulse with the system clock. 
 This signal is denoted EXT ZERO (external zero) . 
 
 The VCO in the conventional PLL corresponds here to a local 
 oscillator consisting of a local oscillator counter, a comparator and an 
 averaging counter. The averaging counter controls the period of the 
 oscillator, and is adjusted to follow the variation of the input signal. 
 It may be considered to contain the average value of previous input periods 
 over some finite time interval. The local oscillator counter is set to 
 

19 
 
 zero at the beginning of a period and counts up until it is equal to or 
 greater than the value in the averaging counter, whereupon it is reset to 
 zero. Note that it is not sufficient to reset the local oscillator 
 counter solely when it is equal to the averaging counter, because if the 
 averaging counter is decremented during the same clock period that the 
 local oscillator counter is being incremented to equal the old value, 
 equality will never occur. The output of gate 1 is considered the output 
 of the local oscillator, and is termed INT ZERO (internal zero). It has 
 the same format as EXT ZERO, that is, one pulse per oscillator period. 
 Since the local oscillator count begins at zero, the value in the averaging 
 counter will be one less than the period of the local oscillator (measured 
 in clock periods) . 
 
 The operations of phase comparison and lowpass filtering are combined 
 in the balance register, a bidirectional shift register with length n bits 
 denoted B(0) ... B(n -1). The left serial input is tied to logical one, 
 
 D 
 
 and the right to logical zero. The balance register is thus a decoding 
 register for a tristate DBE-encoded burst. As a first approximation to its 
 action, the shift left control input is INT ZERO and the shift right 
 EXT ZERO. The local oscillator is cleared whenever either INT ZERO or 
 EXT ZERO is high. Thus, in contrast to the conventional PLL, the phase 
 comparator can distinguish between different cycles of the signals and the 
 response is not periodic in 2ir . 
 
 Consider the case when the local oscillator has just been cleared 
 by EXT ZERO. Then if EXT ZERO is the next signal to go high, the value in 
 the balance register is increased by one, indicating a positive phase error, 
 that is, the frequency of the local oscillator is too low. If EXT ZERO 
 
20 
 
 and INT ZERO go high simultaneously, gate 9 disables both the shift left 
 and shift right control inputs. (If both were high simultaneously the 
 register would load from the parallel inputs.) The value in the balance 
 register remains constant, and the loop is in lock. 
 
 If INT ZERO goes high first, the value in the balance register is 
 decreased by one, indicating a negative phase error, that is, the frequency 
 of the local oscillator is too high. Without further modifications, the 
 next pulse on EXT ZERO would simply return the balance register to its 
 previous value. To solve this problem, a D flip-flop is included in the 
 design. Its value is updated every time the local oscillator is cleared, 
 either by INT ZERO or EXT ZERO, and it is set to the value of INT ZERO. 
 Thus in the case being discussed, the pulse on INT ZERO sets the flip-flop. 
 The Q output then goes low, thereby blocking the next pulse on EXT ZERO 
 through gate 6 and preserving the decrementation of the balance register. 
 The circuit is now returned to the initial conditions of the discussion. 
 Note that if the phase error is less than -it (the local oscillator is more 
 than twice the input frequency) , the balance register will be decremented 
 more than once. This demonstrates the claim that the phase comparison 
 is not periodic in 2tt . 
 
 The value in the balance register is updated by only one bit per 
 cycle of the higher frequency signal. Thus the comparator output has a 
 precision of only one bit for every tt radians of phase error. (Here "bit" 
 is used in the burst sense of the number of positions that can be filled, 
 not in the meaning used in information theory.) To obtain improved 
 performance, the burst philosophy of averaging over a longer time period 
 is employed, using the integrating action of the balance register. B(0) 
 
21 
 
 and B(n -1) are monitored, and only when the balance register is at its 
 
 D 
 
 maximum or minimum value is the averaging counter (and thus the frequency 
 of the local oscillator) altered. Since EXT ZERO is synchronous with the 
 clock, whereas the external signal from which it is derived is extremely 
 unlikely to be harmonically related to the clock frequency, there will 
 always be some phase jitter in EXT ZERO. This jitter is removed by the 
 loop. 
 
 If there is a consistent negative phase error, the integrated value 
 in the balance register will eventually be reduced to zero the clock period 
 
 after a pulse on INT ZERO. The COUNT input of the averaging counter goes 
 
 low, enabling counting. B(n -1) is low so the counter will count upwards. 
 
 Since the local oscillator was just cleared, and the two counters count 
 
 up at the same rate, the local oscillator can never clear. The averaging 
 
 counter will continue to be incremented every clock period until the clock 
 
 period after that in which EXT ZERO goes high. Although the flip-flop 
 
 operates as before, B(0) overrides the operation of this part of the circuit 
 
 by passing a logical 1 through gate 8, enabling the EXT ZERO signal through 
 
 gate 6 to shift the balance register right one bit, halting the upward 
 
 count of the averaging counter. At this point the local oscillator 
 
 frequency will be exactly equal to the frequency of the input signal, and 
 
 the loop will be in lock. 
 
 If there is a consistent positive phase error, the integrated value 
 
 in the balance register will eventually reach n on the clock period after 
 
 B 
 
 a pulse on EXT ZERO. B(n -1) will go high, disabling the incrementation 
 
 B 
 
 of the local oscillator counter. Since B(n -2) was set high by the previous 
 
 B 
 
 EXT ZERO pulse, the local oscillator counter was not reset by the later 
 pulse due to the action of gate 3, and stands at one more than the correct 
 
22 
 
 value. During each succeeding clock period the value in the averaging 
 
 counter is decreased by one until it becomes equal to the value in the 
 
 local oscillator counter, at which point INT ZERO goes high. At the next 
 
 clock period, the local oscillator counter is reset, the value in the 
 
 balance register is decreased by one, and the value in the averaging 
 
 counter is decreased by one to the correct value, leaving the loop in lock. 
 
 The next pulse on EXT ZERO will synchronize the local oscillator to the 
 
 input signal. The balance register will not change because the pulse on 
 
 INT ZERO set the flip-flop. A phase error greater than tt radians can be 
 
 corrected because a pulse on EXT ZERO while the correction is taking place 
 
 will not reset the local oscillator counter, and cannot change the balance 
 
 register because it is already at its maximum value. If the pulse on 
 
 INT ZERO is coincident with a pulse on EXT ZERO, the balance register 
 
 will still be decremented as B(n -1) is high, enabling the INT ZERO signal 
 
 B 
 
 to the shift left control input of the balance register through gates 7 
 
 and 5 . 
 
 The output of the circuit when it is used as an FM demodulator is 
 
 provided by a second bidirectional shift register acting as a decoder for 
 
 a tristate DBE-encoded burst. The inputs are B(0) and B(n -1), the 
 
 B 
 
 correction pulses for the averaging counter. By integrating these signals, 
 the filtered phase detector output, and thus the modulation of the input 
 frequency, can be obtained. By making this register a BSR the output is 
 available in an analog form suitable for audio output. 
 
 4.2 BURSTLOCK Parameters 
 
 The first difficulty in describing the operation of BURSTLOCK is 
 Lning what, it means for the loop to be in lock, particularly when the 
 
23 
 
 input frequency is changing. For any digital PLL, operating in discrete 
 
 time, any change in the input frequency cannot be compensated immediately, 
 
 so that the loop may strictly be said to have lost lock. The situation 
 
 is similar to that of the conventional PLL when the input frequency changes 
 
 at higher than the maximum allowable rate and the loop unlocks for a few 
 
 cycles until it can catch up with the input again. Even for the conventional 
 
 PLL there is some theoretical difficulty in defining lock in other than a 
 
 statistical sense [2], However, for discussion purposes it is sufficient 
 
 to say that the BURSTLOCK circuit is "strictly locked" when the local 
 
 oscillator frequency is exactly equal to that of the input, and unlocked 
 
 when it is unable to move the local oscillator into strict lock. 
 
 Let the local oscillator counter and the averaging counter have 
 
 length n bits, and the system clock frequency be f_ Hz. Then the lock 
 L « 
 
 range is unconditionally equal to the capture range, and is the range of 
 frequencies from f„/(2 -1) to f~/2 Hz. Note that since the local 
 oscillator has no quiescent frequency, the lock range cannot be defined 
 as a deviation from the quiescent frequency as in the conventional PLL, 
 but is instead an absolute quantity. 
 
 The absence of a quiescent frequency means that when the loop is 
 strictly locked there is no need for a constant signal to displace the 
 local oscillator. Thus the static phase error is always zero. 
 
 The concepts of loop gain and bandwidth are somewhat troublesome 
 to define. This difficulty is due to the fact that BURSTLOCK is not an 
 attempt to transform a conventional PLL component by component into digital 
 form. Therefore, a one-to-one correspondence of system characteristics is 
 not to be expected. 
 
24 
 
 Taylor [11] has defined the cutoff frequency of an n-bit BSR as 
 f /2n, the point at which the maximum amplitude of the input signal has 
 fallen by a factor of 2/tt . Since the value of a burst-encoded signal is 
 constrained to change by only one bit every clock period, higher frequencies 
 must necessarily be attenuated by the nature of the encoding. However, 
 this result is not directly useful in describing the filtering operation 
 of the balance register, since only the rightmost and leftmost bits are 
 examined. 
 
 Instead, consider the operation of the balance register. The value 
 
 can only be changed once for each period of the higher frequency of INT ZERO 
 
 and EXT ZERO. For the signal to appear at all the value of the balance 
 
 register must vary from to n and back, requiring 2n -1 alterations. For 
 
 B B 
 
 this to occur, however, the input frequency must be changing, so the 
 
 alteration of the balance register does not take place at a constant rate. 
 
 Suppose that the input signal is being modulated by a square wave between 
 
 the frequencies f.. and f , f < f < f r /2. Then the frequency of the 
 
 modulation that can possibly appear at the output lies between f-/(2n_) 
 
 1 B 
 
 and f„/(2n T) ). Choosing the safer alternative, the bandwidth of the balance 
 L rS 
 
 register may be defined as f ,/(2n ). Note the similarity in form to 
 
 1 B 
 
 Taylor's result. 
 
 The capture time is defined to be the time taken for the local 
 oscillator to move from strict lock at f.. to strict lock at f„ when the 
 input signal undergoes a step frequency change from f to f . From the 
 operation of the circuit it can be seen that the path taken is always 
 direct — there is no underdamped oscillation. The capture time depends to 
 some extent on the past history of the circuit. If no noise is present 
 
25 
 
 in the input, when the loop is in strict lock the value contained in the 
 balance register will be either 1 or n -1, depending on the direction from 
 
 D 
 
 which lock took place. Thus, denoting the period corresponding to f as 
 p , and f as p , the capture time will be either | p -p | /f + min(p ,p )/f 
 
 or | P 1 ~P 2 J ^ f c + ^ n B -1 ^ min ( p i ' p ?^ f C' In the limit ' therefore, T is 
 inversely proportional to the system clock frequency and directly propor- 
 tional to the period difference. When the linearizing assumption to be 
 discussed in detail below is employed, the capture time may be said to be 
 linearly proportional to the frequency difference. 
 
 The previous discussion of the balance register value in strict 
 lock may be described by saying that the circuit expects the input frequency 
 to continue changing in the same direction that the loop has previously 
 been tracking it. If the input frequency moves in the opposite direction 
 
 the local oscillator will not follow for n -1 cycles of the higher 
 
 J3 
 
 frequency. Therefore, the recovered signal modulation will have flattened 
 peaks due to this integrating action of the balance register. The dis- 
 tortion increases as the filter bandwidth is reduced, i.e., as n is 
 increased, and of course is more severe with higher-frequency modulation. 
 This is not an unexpected result, since if high frequency noise is attenu- 
 ated by the filtering action the higher-order harmonics of the modulation 
 corresponding to rapid changes in the input frequency will also be 
 attenuated. For sinusoidal modulation at a frequency f„ of the input, 
 with the lowest excursion of the input frequency at f , distortion is less 
 
 than 5% if 2n„ f w < .05f n . In general, distortion of d% or less will be 
 B M 1 
 
 obtained if 2n f < df , . This approximation is valid for d < 30%. 
 B M 1 
 
26 
 
 BURSTLOCK differs from the conventional PLL in its behavior when 
 
 the input signal drops out. The balance register gives the circuit some 
 
 memory, and it will stay at the lock frequency for between 1 and n -1 
 
 B 
 
 cycles, as already discussed. As the memory of a conventional PLL 
 evaporates, the VCO returns to f . The BURSTLOCK local oscillator, having 
 no f , interprets the signal dropout as the input frequency being modulated 
 to zero and attempts to track. Since n is finite, the averaging counter 
 will eventually overflow, setting the local oscillator back to its maximum 
 frequency and forcing the search to continue. Because of this behavior, 
 and the small lower bound on frequency memory, BURSTLOCK is not suitable 
 for flywheel synchronization applications, although input signal dropout 
 for only a few cycles can be tolerated. However, for FM demodulation, the 
 continual increase in the averaging counter will quickly saturate the 
 output BSR, giving a dc output. Thus for this application the output is 
 similar to a conventional PLL returning to its quiescent frequency. 
 
 4.3 The BURSTLOCK Receiver 
 
 Figure 4.2 shows the means by which commercial FM broadcasts are 
 encoded into a form suitable for demodulation by BURSTLOCK. The output 
 of the encoder is used as the EXT ZERO input for a BURSTLOCK circuit with 
 n = 4 and n =8. The tuning of a station is done by an inexpensive 
 commercially built FM tuner. (David Wells of the Information Engineering 
 Laboratory is currently investigating digital tuning methods.) The 10.7 MHz 
 IF output of the tuner is mixed down to 200 KHz to enable the use of 
 moderate speed digital circuitry for the demodulation. (Standard TTL was 
 used . ) 
 
27 
 
 id 
 
 uj 
 
 N 
 
 1 
 
 O 'O 
 
 
 O IO 
 
 u 
 
 ^<-VW-|>K IvW— | 
 
 UJ * 
 
 So 
 
 s^M' 1 
 
 O-AA/V — 1| 
 
 ho 
 
 c 
 
 ■H 
 
 O 
 U 
 
 c 
 
 w 
 
 3 
 
 c 
 
 o 
 
 H 
 
 Pi 
 pa 
 
 01 
 
 u 
 
 3 
 t>0 
 
28 
 
 The FM signal is applied to one input of a comparator, the other 
 input of which is a dc level adjusted to the middle of the FM sinusoid. 
 The comparator output drives the input of a D flip-flop. The Q output of 
 the flip-flop is ANDed with the input. The output of the flip-flop will 
 be a pulse that occurs only when the input changes from zero to one, that 
 is, when the input signal passes through zero with a negative slope. A 
 second D flip-flop synchronizes the pulse with the system clock. 
 
 An analog audio output is provided by the output BSR of the 
 BURSTLOCK circuit. If the BSR has a length of n_ bits, its signal-to-noise 
 
 ratio (SNR) will be 2n. . This assumes that the signal varies from zero 
 to the maximum value. If the signal has a smaller amplitude, since the 
 quantization noise is constant, the SNR will deteriorate. If the signal 
 amplitude is larger than the register length, clipping will occur. Thus 
 it is of interest to discover how to obtain the optimum amplitude of the 
 BURSTLOCK output. This may be simply calculated as follows. 
 
 Suppose that the input signal is being modulated between the 
 frequencies f and f~, f < t y with periods p and p respectively. Then 
 with an output BSR of length n bits, the optimum amplitude may be obtained 
 by setting f = n_/(p -p 9 ) Hz. Since the frequency of the receiver IF 
 output is difficult to set exactly at 10.7 MHz without monitoring it with 
 a frequency counter, the BURSTLOCK receiver is provided with a variable- 
 frequency clock so that fine adjustments may be made aurally. 
 
 The BURSTLOCK circuit demodulates a frequency-modulated input by 
 integrating the corrections needed to keep the local oscillator tracking 
 the input frequency. A single correction pulse produces a change in local 
 oscillator period equal to one clock cycle, rather than a standard step 
 
29 
 
 frequency change. Thus the output represents the period change of the input 
 rather than the frequency change. Since period is inversely related to 
 frequency, this will cause distortion in the output signal. However, 
 by operating over only a limited range a close approximation to linearity 
 may be obtained. 
 
 In the BURSTLOCK receiver, a 200 KHz input signal is modulated up 
 and down 15 KHz. This modulation is derived from the transmitting station's 
 modulation of its carrier frequency, as detected by the monaural FM 
 receiver. Over the given range the relationship between frequency f in 
 KHz and period p in microseconds may be linearly approximated by the 
 relationship p = 10. 035-0. 02511f with an error of less than 0.5%. The 
 relationship was found using a simple linear regression. In general, the 
 departure from linearity increases with wider modulation and decreases as 
 the signal frequency is increased. 
 
30 
 
 5. COMPARISON OF BURSTLOCK AND THE CONVENTIONAL PLL 
 
 In addition to the well-known practical advantages of digital 
 designs over analog designs in many applications, the BURSTLOCK circuit 
 embodies a number of theoretical advantages over the conventional PLL. In 
 some ways, BURSTLOCK, a second-order (single integrator) loop, may be 
 said to combine advantages of first, second and third-order conventional 
 loops . 
 
 Like the first-order loop, R and R are the same. However, they 
 may be altered simply by changing the number of bits used by the local 
 oscillator, with no effect on any other properties of the loop. Thus R 
 is not reduced as the filter bandwidth is decreased. Like the third-order 
 loop, the static phase error is zero. The response to a change in input 
 frequency can never develop underdamped ringing, again like the first-order 
 loop. As BURSTLOCK expects the frequency of the input to continue changing 
 in the same direction, its action somewhat resembles the acceleration 
 memory of the third-order loop. 
 
 The capture time of a second-order conventional loop is proportional 
 to the square of the initial frequency difference if it is larger than the 
 loop bandwidth. In contrast, T of BURSTLOCK depends only linearly on 
 the initial frequency difference. Furthermore, decreasing the loop band- 
 width increases only a constant term in the T value, while the same action 
 affects T of the conventional loop by a cubic term. Therefore, it is less 
 likely that sweeping will be needed to obtain rapid locking. This 
 
31 
 
 improvement may be ascribed to the fact that the phase comparator does not 
 have a periodic response. 
 
 Since BURSTLOCK contains only a small number of components, it is 
 well suited for integration. In an integrated form it would not require 
 the connection of external components as is usual in currently available 
 integrated PLL's. 
 
 In the design of conventional PLL FM discriminators, it is usual 
 to employ a post-detection filter, often a five or six-pole Bessel or 
 Butterworth design [2]. In the BURSTLOCK receiver, only a simple RC filter 
 might be desired to smooth out the sharp edges of the BSR output. 
 
 Due to the limitations on loop memory and the lack of a quiescent 
 
 oscillator frequency, BURSTLOCK is not suitable for applications which are 
 
 based on these properties, such as flywheel synchronization or the 
 
 selection of one of several signals by setting f close to that of the 
 
 desired signal and using a small R . Without any f , the R^ of BURSTLOCK 
 
 ^ L Q L 
 
 is an absolute range rather than a deviation to either side of f . 
 It has been seen that the signal distortion encountered in 
 BURSTLOCK FM demodulation is inversely proportional to the filter band- 
 width. This is not an unreasonable result, as it must be expected that 
 some penalty be paid for a decrease in bandwidth. Distortion is encountered 
 in the conventional PLL also, due to a sinusoidal phase comparator 
 characteristic and VCO nonlinearity . 
 
32 
 
 LIST OF REFERENCES 
 
 [1] Byrne, C. J., "Properties and Design of the Phase-Controlled 
 
 Oscillator with a Sawtooth Comparator," The Bell System Technical 
 Journal , March 1962, pp. 559-602. 
 
 [2] Gardner, F. M., Phase-Lock Techniques , Wiley, New York, 1966. 
 
 [3] Goldstein, A. J., "Analysis of the Phase-Controlled Loop with a 
 
 Sawtooth Comparator," The Bell System Technical Journal , March 1962, 
 pp. 603-633. 
 
 [4] Grebene, A. B., Analog Integrated Circuit Design , Van Nostrand 
 Reinhold, New York, 19 72. 
 
 [5] McAleer, H. T., "A New Look at the Phase Locked Oscillator," 
 Proceedings of the IRE , June 1959, pp. 1137-1143. 
 
 [6] Mohan, P. L., "The Application of Burst Processing to Digital FM 
 
 Receivers," Department of Computer Science Report No. 780, University 
 of Illinois, January 1976. 
 
 [7] Moschytz, G. S., "Miniaturized RC Filters Using Phase-Locked Loop," 
 The Bell System Technical Journal , May 1965, pp. 823-870. 
 
 [8] Poppelbaum, W. J., "Application of Stochastic and Burst Processing 
 to Communication and Computing Systems," proposal for the Office of 
 Naval Research, Department of Computer Science, University of 
 Illinois, July 1975. 
 
 [9] Poppelbaum, W. J., Computer Hardware Theory , Macmillan, New York, 1972, 
 
 [10] Poppelbaum, W. J., "Statistical Processors," Advances in Computers , 
 Vol. 14, Academic Press, New York, 1976. 
 
 [11] Taylor, G. L., "An Analysis of Burst Encoding Methods and Transmission 
 Properties," Department of Computer Science Report No. 770, University 
 of Illinois, December 1975. 
 
 [12] Viterbi, A. J., Principles of Coherent Communication , McGraw-Hill, 
 New York, 1966. 
 
33 
 
 APPENDIX 
 RECEIVER DESCRIPTION 
 
 Figure A.l shows a photograph of the BURSTLOCK receiver. The 
 front panel controls consist of a clock frequency control, clock enable and 
 on/off switch. Mounted inside the cabinet and accessible through a port 
 in the rear panel is an inexpensive analog radio, which provides the IF 
 input to the BURSTLOCK circuit. 
 
 To tune in a station the clock enable switch should be set to the 
 off position and the volume control on the radio turned up. When the 
 desired station is tuned on the radio, the volume control should be reduced 
 to zero and the clock enable switch set to the on position. The output 
 from BURSTLOCK will then be audible from the speaker in the front panel. 
 The clock frequency should be adjusted to give the best possible output. 
 
 It is necessary to use this method for tuning because it is difficult 
 to tune the analog radio to the exact station frequency. An acceptable 
 audio output from the analog tuner will be produced when the IF is within 
 approximately 10% of its nominal value of 10.7 MHz. Even when monitoring 
 the IF signal with a frequency counter, exact tuning is a time-consuming 
 process since the frequency count deviates about the nominal value due to 
 the modulation, and the tuning control is affected by body capacitance when 
 adjustments are made. It is far easier to compensate for tuning errors by 
 adjusting the clock frequency in the manner described. 
 
35 
 
 The components of the BURSTLOCK circuit are mounted on three 
 printed circuit cards. The first card contains all the components shown 
 in Fig. 4.2, with the exception of the analog tuner. The IF input is 
 buffered with a unity-gain operational amplifier to avoid the adverse 
 effects of loading on the tuner. Mixing is done with a 76514 doubly 
 balanced mixer, and a 10116 comparator is used. 
 
 The second card contains all of the components shown in Fig. 4.1 
 except the output BSR, which is mounted on the third card. Since the 
 BSR output produces a relatively low volume when operating directly into 
 a speaker, a 386 audio amplifier on the same card is used to boost the 
 signal to a more useful level. The clock generator, consisting of two 
 74121 monostable multivibrators and a 7406 open-collector inverter to 
 increase the fanout, is also mounted on this card. The clock frequency 
 is controlled by the dual 50 KT2 potentiometer on the front panel, and is 
 variable from approximately 50 KHz to 5 MHz. The clock enable switch is 
 connected to the enable pin of all shift registers and counters in the 
 system. 
 
 A +5V and a -5V power supply are mounted inside the cabinet to 
 make the receiver self-contained. 
 
BIBLIOGRAPHIC DATA 
 SHEET 
 
 4. Tide .ind Subtitle 
 
 1. Report No. 
 
 UIUCDCS-R-77-872 
 
 3. Recipient's Accession No. 
 
 5. Report Date 
 
 May 1977 
 
 7. Author(s) 
 
 Colan Michael Robinson 
 
 8- Performing Organization Rept. 
 
 No UIUCDCS-R-77-872 
 
 9. Performing Organization Name and Address 
 
 Department of Computer Science 
 
 University of Illinois at Urbana-Champaign 
 
 Urbana, Illinois 61801 
 
 10. Project/Task/Work Unit No. 
 
 11. Contract /Grant No. 
 
 N000-14-75-C-0982 
 
 12. Sponsoring Organization Name and Address 
 
 Office of Naval Research 
 219 South Dearborn Street 
 Chicago, Illinois 60604 
 
 13. Type of Report & Period 
 Covered 
 
 Master's Thesis 
 
 14. 
 
 15. Supplementary Notes 
 
 16. Abstracts 
 
 BURSTLOCK is a digital phase-locked loop implemented using Burst 
 Processing. It is used in a receiver perform FM demodulation of 
 commercial broadcast signals. It is also shown that BURSTLOCK 
 has some theoretical advantages over conventional phase-locked 
 loops. 
 
 17. Key Words and Document Analysis. 17o. Descriptors 
 
 Burst Processing 
 Burst Phase-Locked Loop 
 Block Sum Register 
 Digital Receiver 
 
 17b. Identifiers /'Open-Ended Terms 
 
 17c. COSATI Fie Id/Group 
 
 18. Availability Statement 
 
 Release Unlimited 
 
 19. Security Class (This 
 Report) 
 
 UNCLASSIFIED 
 
 20. Security Class (This 
 Page 
 
 UNCLASSIFIED 
 
 21. No. of Payes 
 
 35 
 
 22. Price 
 
 FORM NTIS-35 ( 10-70) 
 
 USCOMM-DC 40329-P7I 
 

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