L I B HAHY OF THE U N IVLR.5 ITY Of ILLINOIS 510,84 I£6r no. 156-163 c o p 2 Digitized by the Internet Archive in 2013 http://archive.org/details/tunneldiodecircu158moto 5lO 84- no. \53 2, COO DIGITAL COMPUTER LABORATORY UNIVERSITY OF ILLINOIS URBANA, ILLINOIS REPORT NO. 158 TUNNEL DIODE CIRCUITS BASED ON LUMPED CONSTANT CIRCUITRY fcy Tohru Moto-Oka August 9, 1963 This work was supported in part by the Office of Naval Research under Contract No. Nonr-l83Ml5) ACKNOWLEDGEMENT The author wishes to express his appreciation to Professor W. J. Poppelbaum, Professor T. A. Murrell, and Mr. Henry Guckel for their invaluable help and encouragement, Foreword Investigation of the speed limit of tunnel diode circuit operation indicates that these circuits should be considered as distributed circuits, because the cut-off frequency of the tunnel diode is more than one thousand megacycles. Methods of obtaining maximum speed tunnel diode circuits may be classified into two groups. One method is that a circuit is designed as a lumped constant circuit originally and, after that, these lumped constant elements are replaced by distributed circuits, if necessary. The other method is that the characteristics of distributed circuitry are used positively and the circuits are designed as distributed circuits from the beginning. The latter method seems to have more difficulties and more possibilities for maximum speed circuits than the former. Several trials in this direction will be mentioned in a succeeding report . The former method is used in this report. The linear analysis of resistive networks which include negative resistance elements such as a tunnel diode, are mentioned in Part I. In Part II, the tunnel diode -transistor hybrid logical and switching circuits are mentioned as one example of the application of the theories which are described in Part I. The operating speeds of the hybrid circuits do not seem to be as high as those of all tunnel diode circuits, but they are much more easily designed and more practical in a large digital system. Part I Design Theory of Negative Resistance Amplifiers 1. Introduction Amplifiers which are composed of only resistors and negative resistive components, such as tunnel diodes, are expected to have wide band width. This means that they are useable from dc to a frequency that is strongly related to the time constant of the negative resistive element. The amplifier stages are considered as active, purely resistive, four- terminal networks in the low frequency range. In general, a four-terminal network is determined by three conditions. In the design theory which is mentioned below, an input impedance, an output impedance, and a voltage gain are selected as the three conditions which must be satisfied by a matched amplifier stage. As far as physical realizability is concerned, each component must be considered as a parallel circuit of a positive or negative resistance and stray capacitance . 2. Linear, Purely Resistive and Active Four-Terminal Networks The circuit equations of the four-terminal network which is shown in Figure 1 are: ► T A 1 i t 2 R 4t E (~) 1 n t t • ! V2 * I n R, Figure 1. Four -Terminal Network -1- ' V l\ / Z ll ^X/ 1 ! V V Z 12 WV 2 (1) V n = E - R.I. 1 l 1 (2) V 2 - -^ (3) From these equations, matching conditions axe given by the following equations: V l Z 12 in = ' I 1 ■ 11 ' R Q + Z 22 " i w z 3 out I E=0 12 R J 22 R. + Z. ' i 11 (5) Voltage gain G may be written as: G - ^r R Z 12 1 R Z 11 + Z 11 Z 22 ' Z 12 (6) -2- The following equations are obtained from Equations (K) and (5) R? = ^ A (7) i z 22 4 = ^* w R Z 22 (9) where A = Z 11- Z 22- Z 12 2 • Its value should be positive; otherwise, R. or R become negative, A backward voltage gain G' may be written as: R.Z, R. G ' = R Z + A = iT G (10) R.Z 22 + A R Q -3- Also, a power gain G and a current gain G may be written as follows: V ? 2r • R • G = ~^- JTG = G G' (11) V 1 R ° V„ E. R. g c = ?:r7 = r7 g = g ' (12) i It is apparent from Equation (ll) that the power gain in the forward direction has the same value as the power gain in the backward direction. Therefore, a power amplifier which has directivity is not realizable . A current amplifier is a voltage amplifier seen from the opposite direction. 3. TT-Type Amplifier The n-type circuit which is shown in Figure 2, has the following relations between its component values and the coefficients of the four-terminal network: V R 2 + V Z ll = R x + R 2 + R 3 (13) R 3 (R 1+ R 2 ) Z 22 = R + R 2 + R ^ ' R l R 3 Z 12 = R x + R 2 + R (15) -k- Figure 2. n-Type Circuit The following equations are derived from Equations (13)> (1*0 and (15) R, = 1 Z 22 " Z 12 (16) R 2=Z (17) 12 R„ = 3 Z ll- Z 12 (18) On the other hand, the following relations are obtained from Equations (6) through (9): A = R R. (19) R~ z - -^z Z 22 ~ R. Z ll l (20) Z 12 = G ( Z H +R i) -5- (21) Therefore : ■p A = z ii 2 r-° 2(z ii +R i )2 = R o R i < 22 > 1 TC ' ° 2 ) hi " 2G \hi " (g2r i + R o R i } = ° (22 ' } Zl1 = R ' r 2 i G 2 R. + R. R„ + G 2 R. R X " ° - -R, or -° ,-i R. (23) ^°-G 2 X R 0" GR i X l Two sets of solutions of Equations (l3)> (l*0> a nd (15) are obtained "by inserting Equation (23) into Equations (20 ) and (21). ^ Z ll ■ " R i Z 22 " " R Z 12 " ° (2k) R + GR. R Q + GR. 2GR Q R. (II) Zl1 = 7~T7t R i Z22 = TTft R ° Zl2 ~~ r~^ l i l -6- Also, two sets of values of circuit components are obtained from Equal i.6), (17), and (l8) by using the above relations. (I) R 1 = -R. R 2 = . R 3 = -R Q (26) R . (R n -G 2 R . ) R n - G 2 R . R (R -G^ . ) (II) R = x ° 2 x R 2 = % G x R, = ° ° 2 x R_ + G R. - 2GR. R^ + G R. - 2GR. Oil Oil (27) The set (i) is apparently not suitable, but set (il) shovs some design conditions which will be described in detail later. Equation (27) may be rewritten in a normalized form as: k - G 2 k - G 2 k(k-G 2 ) 1* = t» = r = * 1 P P PC ^ P k + G - 2G D k + G - 2Gk where k = R n /R. and r , r , r~ are R /R., R /R., R /R. respectively. Set (il) may be subdivided into eight regions which are shown in Figure 3. If it is assumed that a tunnel diode is used as a negative resistive element, these regions correspond to circuit configurations shown in Figure k. (2 T « ) -7- Figure 3. Regions of it-Type Amplifiers ■8- V s v^ Q M y s 2' 1' 2' (a) ^ tr 1 l < 2 I l' o 2' o (b) M 2' (e) 1' o— u u 2' — o (g) (h) Figure k. Circuit Configurations of it -Type Amplifier In regions "g" and "h" the voltage gain G is negative, so that it becomes a phase -inverter type amplifier. The current gain is G/k as given by Equation (12), so that a part of region "b," region "c," region "d, " and a part of region "e" are considered as current amplifier and parts of region "g" and region "h" are considered as phase -inverter type current amplifiers . However, backward voltage gain corresponds to a forward current gain and a circuit which has a k larger than 1 has an identical circuit configuration with a circuit which has a k less than 1, except that input terminal and output terminal are interchanged. -9- p The power gain is G /k as given by Equation (ll), so that regions "a," "e," "f," and "g" have a power gain of less than 1. In other words, one or zero tunnel diode amplifiers have no power gain. Two or three tunnel diode amplifiers have power gains, but they are not realizable physically as mentioned later. k. Physical Realizability of a fl-Type Amplifier As far as frequency characteristics are concerned, a, pure resistance or a pure negative resistance do not exist physically. Therefore, in order to consider physical realizability of a Jt-type amplifier, the frequency characteristic of each element must be considered. As the simplest assumption, a shunt stray capacitance is assumed on each element. This assumption changes the original ideal circuit configuration into the circuit shown in Figure 5. According to the stability criterion, the following equation should have roots only in the left half plane of the s -plane. 3 R J=l -^-J Z - ^ T = o (28) 1 + ST where R l = R i R iA R i +R l)' R 2 = R 2' R 3 = R 3 V (R o +R 3 ) and t = R'.C -10- This equation may be rewritten as follows : or where R^(1+st 2 )(1+st 3 ) + R^(1+st 3 )(1+st 1 ) + R^(1+st i )(1+st 2 ) = (29) p As + Bs + C = (29« ) A . R 1V3 + R.T 3 T 1 + R'T X T 2 = R i R 2 R^(C 2 C 3+ C 3 C 1+ C 1 C 2 ) B = R^(t 2 +t 3 ) + R 2 (t 3 +t 2 ) + R^(t i+ t 2 ) = R^R 2 (C 1+ C 2 ) + R 2 R^(C 2 +C 3 ) + R^C^) C = R^ + R 2 + R» The condition that zeros of this equation exist only in the left half plane might "be written as B/A > and AC > 0. That is, A, B, and C should have the same sign. Therefore, the necessary and sufficient conditions for circuit stability may be rewritten as the following equations by using Equations (27 ! ) and making use of the fact that all stray capacitances have positive values. -11- because > R i V -r 1 VH i R r Figure 5, -* o- k - G > (30) C + C (l+k-2G) + kC > (3D sien of A = sign of k - G g G(k-G)(l-G) sign of B = sign of "(c 1+ c 2 ) (c 2 +c 3 ) (cyc^) (k-G)G + C-(l-G) + (1-G)(k-G) sign of C = sign of Qj(k-G)(l-G)J -12- Therefore, regions "a," "e," "f," and "g" are alvays stable, and regi "b," "c," "d, '' and "g" are always unstable. The condition of Equation (3L) is included in Equation (30)^ In other words, one tunnel diode amplifier is stable and two or three tunnel diode amplifiers are unstable. Also, a power amplifier is not realizable under these restrictions. 5. T-Type Amplifiers A similar analysis can be applied to a T-type amplifier which is shown in Figure 6. T-type amplifiers are derived from it-type amplifiers by using the principle of duality. -o vA ,R. 1 ^E R > R 2 SR, Figure 6. T-Type Amplifier The following equations correspond to Equations (27) and (27' ) (L+Gl . -2GR_ )R . 2GR^R . r ° 1 1 R 1 R i = : :£; R 2 = : ~3 R Q - G R. R Q - G R. (R +G R -2GR )R R_ = -5 1 1 ° (32) R Q - G R. r i = k + G - 2Gk ~2 k - G r 2 = 2Gk k - G c k(k+G -2G) k - G (32') -13- Therefore, regions which classify characteristics of T-type amplifiers correspond to regions of n-type amplifiers, which are shown in Figure 3. Circuit configurations of T-type amplifiers are shown in Figure 7. They correspond to the regions which are shown in Figure 3= 1' o- B S (a) V^ 2' — o 1' o— v^ M m 2' — o ^> — 1 1 1 2 V 1' O- I > 2' (c) M (a) V^ 2* 1' o— <> e) 2' — o 1' o— ^A (f) >A 2' 1 1" V^ 2' — o 1' o— S % 2 1 — o (h) Figure 7- Circuit Configurations of T-Type Amplifiers Physical realizahility requires that at least dc stability conditions of the negative resistances are satisfied. They are written as follows: -ik- R 1 N I > R i + R 2 \ R3 + R Q ^3) (R +R )(R +R ) R I ~^ ^ f ^U 'l 2N ' ^ R. + R, + R_ + R^ V3 y i 1 3 R 2 (R i + V R 3N I > R + R. + R n + R (35) l 1 2 Equations (33) a-nd (35) are not satisfied. This is apparent from the matching conditions. Therefore, regions "a," "b," "c," "d," "e," and "h" are physically not realizable. Equation (3*0 may be rewritten by using Equation (32') as: G(k-G)(l-G) > (3V) This condition is not satisfied in region "g," so that any T-type circuit configuration is physically not realizable. 6. Conclusion The conclusion of the investigations of matched negative resistance amplifiers which have circuit configurations of Jt-type or T-type are: 1) a power amplifier is physically not realizable. 2) phase inverter type and inphase type voltage or current amplifier stages are realizable only in it -type circuit configurations. 3) any T-type amplifier stages are physically not realizable. h) in voltage amplifiers, the output impedance is larger than the input impedance. 5) in current amplifiers, the input impedance is larger than the output impedance, and these are voltage amplifiers in the reverse direction. -15- Hybrid circuits which are composed of these voltage amplifiers and transistor emitter followers, can be used as NOR, NAND, OR and AND circuits; that is, they are used as a set of logical circuits. Application of these inverter type amplifier stages to GOTO-pair tunnel diode circuits eliminates the demerit that a NOT circuit is difficult to realize as GOTO-pair „ The revised GOTO-pair circuit is shown in Figure 8„ The hybrid circuits are mentioned in detail in Part II. Input O y/ <► ^-v- J~L X is T ^-rS r S -o + Output Figure 8, The Revised GOTO-Pair Circuit ■16- Part II Hybrid Tunnel Diode -Trans istor Logic Circuits 1. Introduction It is difficult to determine which type of circuitry has the highest speed and is technically realizable as far as ultra high speed digital systems are concerned. When a large system is considered, a circuit which works at the highest speed as a single element is not necessarily the highest speed circuit for that system. Therefore, some hypotheses are given first. In the first hypothesis, asynchronous systems are considered, because asynchronous systems permit more flexibilities in logical designs and the difficulties which are caused by delay times of clock pulses and/or reset pulses are eliminated. Then a power source is essentially dc. In the second hypothesis, dc coupled circuits are considered, because inductances and/or capacitances which are necessary for ac coupled circuits are energy storing elements which work usually as delay elements on recovery times, and dc coupled circuits are easier to adjust than ac coupled circuits. As far as tunnel diode circuits are concerned, design methods of power amplifiers, directive circuits and negate circuits are the main problems under the former assumptions. There is no inherent difficulty on logical circuits such as AND and OR circuits and reshaping circuits, because tunnel diodes are considered as threshold elements inherently. As a result of the investigations of networks of positive and negative resistive elements, which were described in Part I, it is concluded that tunnel diode it-type circuits, which are matched completely to input and output resistances, work as inverted or non-inverted voltage or current amplifiers, but power amplifiers are physically non-realizable. Therefore, it is not easy to realize tunnel diode power amplifiers, even if directivity is given by the use of backward diodes. When the use of emitter followers or grounded base amplifiers which have the best frequency characteristic of all transistor circuits, is permitted, many difficulties seem to be eliminated, because these circuits work as power amplifiers with directivity. -IT- Amodei's circuits are examples of hybrid circuits of grounded base transistor amplifiers and tunnel diode circuits, in which power gain, circuit directivity, voltage gain, and negate characteristics are given by transistor circuits and current gain and other necessary characteristics are given by tunnel diode circuits. Hybrid circuits of emitter follower transistor circuits and tunnel diode circuits are described in this report. In these circuits, power gain, circuit directivity, and current gain are given by transistor circuits, but voltage gain, negate characteristics and other necessary characteristics are given by tunnel diode circuits. In Amodei's circuit, the non-linear characteristic of a transistor's base -emitter junction is used. This should match the non-linear characteristic of a tunnel diode. The output signal is always inverted. In the circuit which is described in this report, these demerits do not exist. Also, an emitter follower seems to have better high frequency response than a grounded-base amplifier. The signal level in this circuit is rather low, approximately 100 mv for a Germanium tunnel diode, so that the cutoff of emitter-base junction which occurs in a large signal pulse operation often is not a serious problem. 2. NOR and NAND Circuits The investigation of a completely matched tunnel diode amplifier shows that a hybrid circuit which is composed of a transistor emitter follower and a tunnel diode phase inverting voltage amplifier works a,s NOR or NAND circuit , which is shown in Figure 1. -A V^ o vA- ® ■o- S EF Figure 1. NOR or NAND Circuit J. Amodei and W. F. Kosonocky: High-speed Logic Circuits Using Common-Base Transistors and Tunnel Diodes; RCA Review, Vol. XXII, Pp. 669-684, Dec, 1961. -18- From the standpoint of matching conditions, the input, the output, the coupling resistance should have the following relationships: 1_ R' n - 1 R /m-l_ 1_ t R+R- + R. + R (1) R. = ^(R+R' ) 1 m (2) R = H R+ C^ + H7 " (3) where R., R , R are the input, the output, and the coupling resistance respectively, and R' is the resistance looking backward from the coupling resistance as shown in Figure 2. m and n are fan-in and fanout respectively. \ R l \ m A v° 1 1 1 1 R ■-V s n E >*, >*r (a) (b) Basic NOR or NAND Circuit Figure 2 . Schematic Diagram for Matching Conditions =19- From these equations <, R., R are given as functions of R, m, and n,, that is: m(2n-l) n(2mn-m-n) w n(2m-l) 'i " m(2mn-m-n) (5) ^0 = m 2 (2n-l) R i n 2 (2m-l) The relation between the input -output impedance ratio and the fanin, the fanout^ is shown in Eq. (6) and Ta,ble 1. (6) \ m 1 ^^S 1 2 3 4 5 6 7 1 1 1 = 333 1.8 2.286 2.778 3 = 273 3»769 2 0,75 l 1,35 I.71A 2.083 2.455 2.897 3 0.556 0.741 1 1.270 1.5^3 1.818 2.094 k O.Ij-38 0.583 0.788 1 1.215 1.4-32 1.649 5 0.36 0.48 0.648 0.823 1 1.178 1,357 6 0.306 0.407 0.55 0.698 0.849 1 1.152 7 0.265 0.354 ^— — - — — — 0.478 — — — — — O.606 0.737 0.868 1 Table 1. The Relation Between R n /R. and m, n 0' i -20- The voltage attenuation of the coupling circuit I 1 / m-1 l_ 2rrfL I R+R' + R. \ 1 -1 Pm(?n-1) (7) A tunnel diode voltage amplifier stage should have a voltage gain, G, which has the following relation, because the overall gain must be larger than one and the voltage gain of an emitter -follower is approximately one or less than one. G >^ (2n-l) n (8) Table 2 shows the relation of the necessary voltage gain of the n-type tunnel diode circuit. 1 1 : 1 j 2 | 3 4 5 — 1 6 7 1 2 U I 6 8 10 12 14 2 3 6 9 j 12 15 18 21 3 3.333 6.667] 10.00 • 13.33 16.67 20.00 23.33 4 3.5 7 10.5 l4 17.5 21 24.5 5 3.6 7.2 10.8 I l4.4 18 21.6 25.2 6 3.667 7.333] 11.00 1^.67 18.33 22.00 25.67 7 3.71* 7.428) u.l* 1 14.86 18.57 22.29 — , — 26 — , 1 Table 2. The Relation Between the Necessary Voltage Gain of the Tunnel Diode and "m," "n" -21- On the other hand, the product of the input-output resistance ratio of the emitter -follower and the input-output resistance ratio of the n-type tunnel diode circuit should satisfy the relation of Eq. (6). When it is assumed that R^/R. of 0' 1 the emitter -follower is a fiftieth and fanin and fanout have the same value, k = R n /R- of the JT-type tunnel diode circuit should be fifty. Since k and G have 2 the relation K - G > 0, which is described in Part I, m and n should satisfy the following relation: 2(2n-l) <\T50 that is, m = n should be one or two. In general, fanout and fanin are limited by the following relation: ' =- or (2m-l)(2n-l) < r l — ^ (2n-l) <, V 2/ Q ,n \R„ n (2m-lj ^Vr (9) Table 3 shows numerical examples of this relation: m or n i or m 1 2 3 k 5 6 7 1 k 12 20 28 36 kk 52 2 36 6o 8^ 108 132 156 3 100 lAo 180 220 260 k 196 252 308 3ft 5 32^ 396 U68 6 kQk 572 7 676 Table 3. The Relation Between (R./R ) of the Emitter -Follower and "m," "n M -22- These investigations show that it is difficult i rge fanin and fanout. A fanin of two and a fanout of three or four are reasonaole numbers, if an entire system is built from a single standard NOR or NAND circuit. When an ideal rectifier can be used as a coupling element as shown in Figure 3, the situation becomes better. Up to this point, the tunnel diode was considered as a linear negative element, but an actual tunnel diode has a nonlinear characteristic. Especially when the tunnel diode is used as a threshold element, waveform reshaper or noise suppressor, its behavior is not explainable by the linear approximation of the characteristic. One of the methods which is used to design a hybrid NOR and/or NAND circuit for signal operation is as follows: The equivalent circuit, which is shown in Figure 4(b) is used in the following analysis. The following relations between the equivalent circuit and the former circuit are apparent from a comparison of Figure 4(a) and (b): R = s m R. R'+Rl 1 1 -1 (10) R„ = R 6 R 3 1 R + R ^ (11) V. = Rl _ i m-1 R'+Rl -1 R' + Rl + l m-1 R'+Rl l -rl (12) -23- w ■*■ i m **—sA—r S s % {* Figure 3- Hybrid NOR Circuit With Rectifier Coupling Elements r! R' © 1 a A > 1 v^ V m ! i 1 > R i i> R 3 r° 1 A A 1 ^ V ^ E' r! 1 R' — — ~ = " Emitter Coupling Circuit n-t >e Inverte Emitter Follower Ampli: ier Fo.l lower (■ . 1/ B >R L Figure ^. Equivalent Circuit For Large Signal Operation . 2 U. 1. At. first, the operating region of a tunnel diode wh Figure 5(a>t>) is determined. 2. Two tangent lines are drawn to a tunnel diode voltage -current characteristic curve through points "a" and "b," and the steeper slope of two tangent lines corresponds to the allowable maximum value of (R +R*). When this value is used in the design, a maximum voltage gain is available, but switching speed tends to infinity. Therefore, some compromises between voltage gain and switching speed are necessary. Kv t -H Figure 5- The Operating Characteristic of a T.D. Inverted Amplifier When the switching speed is determined, the value of (R +R/>) is fixed and the output voltage and input voltage gain become functions of R or R„, as follows: -25- V o - ^i-V (13) \ - (V 2 - Vl ) - (R £+ R s )( h -I 2 ) (Ik) k = V. 1 R, V V 1 (VV (15) where (V , I ) and (V , I ) are coordinates of the points "a" and "b" respectively. The operating region determines the maximum voltage gain and the maximum output voltage. A decrease of the operating region of a tunnel diode usually increases the maximum voltage gain, because the characteristic is considered to be more linear in a smaller region. The maximum output voltage is determined by the shape of the tunnel diode v-i characteristic and if the voltage of the point "b" is less than the valley point voltage, the decrease of the operating region decreases the maximum output voltage . The relation of the maximum output voltage and the voltage at point "b," which gives the maximum gains, is shown in Figure 6. Equation (15) shows that the decrease of R increases the voltage gain, if V. does not decrease due to the decrease of R . In other words, if the arbitrary input resistance of the inverting voltage amplifier does not cause any trouble, the L-type circuit, which is shown in Figure 7 > has a larger voltage gain than the former rt-type circuit. In large signal operation, the nonlinearity of the tunnel diode characteristic causes large changes in the input impedance. In order to do the exact analysis of the L-type circuit and to find the optimum design conditions for large signal operation, the emitter -follower characteristics, such as input/output impedances, should be considered together with the tunnel diode characteristic. -26- ! 1 £ I NO -27- ■nA aA TD EF -O V^- s Figure 7, L-Type NOR or NAND Circuit The switching speed of the L-type circuit is given by the following equation, when the parallel circuit of the ideal non-linear resistive element, that is, i = f(v), and a shunt capacitance C is used as the tunnel diode equivalent circuit, as shown in Figure 8. C \\- M = R , *> 1 f(v) = i — r Figure 8. Switching Speed of a Tunnel Diode Circuit -28- -_,... , / , i, . \ difference of current coordinates of load and T.D. Switching speed (dv/dt) = (16) This follows from the circuit equation of the equivalent circuit shown in Figure 8: or s I . r— nr ~ f(v) ^=-S l - (16") dt C ^ ' The simplified calculation of tunnel diode switching time, which is based on an approximation of the tunnel diode characteristic by a curve of degree three, is described in Appendix 1. 3. OR and AND Circuits Most parts of the discussions on NOR and NAND circuits in the last chapter are applicable to OR and AND circuits, when slight changes are made. Therefore, differences only are described in this chapter. The investigation of a completely matched tunnel diode amplifier shows that the hybrid circuit, which is shown in Figures 9 and 10, works as an OR or AND circuit, i The equivalent circuit, which is shown in Figure 11, is used in the large signal analysis. The following relations exist between the equivalent circuit and the real circuit: -29- o a- o— V s - i m I I o — vA- <> EF M Figure 9„ OR or AND Circuit -Of- <>— v» ♦ vA m I % EF & Figure 10. OR Circuit with Rectifier Couplers •30- r: ill vA ■nA *2 ® W M vi lh-© A E' R! R' (a) V. 1 M v 00 Figure 11. Equivalent Circuit for Large Signal Operation 1 1 1 R s ~ R 6 R 2 + ~1 m RI + R'+Rl 1 l -1 (IT) V. i E R R i + R 6 + : (R'.+R«) + m R + R 2 l (18) -31- As far as large signal operations are concerned,, any matching condition is meaningless, so that resistances R' and R' can be eliminated. Then the following equations are derived from Eq„ (17) and (l8): 1 m R R< R' + R'. (17') s 1 \ 1 / R'E V = (18O i R' + Ri + mRI V ; 1 The following design method of the hybrid OR or AND circuit can be used as well as that of the hybrid NOR or NAND circuit. 1. At first, the operating region of the tunnel diode, which is shown in Figure 12 (a, b) is determined. 2. Two tangent lines are drawn to a tunnel diode voltage -current characteristic curve through points "a" and "b." The steeper slope of the two tangent lines corresponds to the allowable maximum value of R . When this value is used in the design, s 7 the maximum voltage gain is available but switching speed tends to infinity. Therefore, some compromises between voltage gain and switching speed are necessary. 3) When the switching speed is determined, the value of R , input voltage and voltage gain, are fixed: ■32- V = V - V v 2 1 V = (v -V ) - (I -I ) I K 2 1' V 1 2 } R (20) k = _0 v. i V 2- V l V v i l r l 2 (21) R where (V } I ) and (V , I ) are coordinates of points "a" and ""b," It is apparent from this design method that OR and AND circuits have larger voltage gains than NOR and NAND circuits. The large signal OR or AND circuit is shown in Figure 13. R Figure 12. Operating Characteristic of a Non-Inverting Voltage Amplifier -33- o sA Q o j-V^ EF s aA Figure 13. Large Signal Operation of OR or AND Circuit k . Storage Circuits The large signal operated logic circuits, which were described in the last two chapters have bi-stable states for some input voltage regions . Therefore, these circuits can be used as flipflops. They are shown in Figure Ik. Since a NOR circuit is a general purpose circuit, a, flipflop can be built by these circuits as shown in Figure 15(a). Binary counters are designed by using these flipflops. They are shown in Figure 15(b) and Figure l6. An example of a shift-register is shown in Figure 17 . -3k- Set A s R (D o it- *R Reset T EF (a) Set Y <>K SR Reset A <£ EF (b) Figure lU. Flipflop -35- (a) Flip flop (b) Counter Figure 15 . NOR-Type Circuits •36- The operating speed of the circuit Ls mainly limited by the operating speed of the emitter-follower, so that the increase in the number of emitter- followers, which are included in the feed-back loop, decreases the operating speed of the circuit. Therefore, a NOR type counter, which includes three emitter- followers in its loop, operates slower than counters shown in Figure l6, which include two emitter -followers. 5. Carry Propagation Circuit Every circuit can be built from the basic circuits which were described in the last three chapters, but some circuits have better characteristics than the standard circuits, when these circuits are designed from a different point of view. The carry propagation circuit which is described here is one example of this type of circuit. As far as digital arithmetic units are concerned, high speed units are, of course, designed easier in parallel systems than in serial systems. However, when a simple parallel adder is used as a main part of a digital arithmetic unit, sequential carry propagations from less significant digits to the more significant digits prohibit the unit from being of high enough speed to compensate for the expensive devices. Therefore, high speed carry propagation circuits are one of the most important problems in the design of high speed parallel arithmetic units. Solutions of this problem, generally, are divided into two classes, that is, l) logical design methods a) carry detecting logic b) carry restoring logic c) carry skip logic 2) high speed carry propagation circuits -37- o— • — v*- — — o ( J"L o-V — 4- ® Q s g (a) EF 4 > $ EF S> I > ■ < > EF S M 00 Figure l6. Counter vH2- ^ s -EHN ^ J e- v — |n ©■ -v — /\ ■QHi' 0- 1 ■QHh } ! -39- In the New Illiac, carry restoring logic is used. The circuit which is described here belongs to the second class. Carry propagation circuits are one of the most typical circuits which have characteristics suitable for tunnel diode circuits. A negate circuit is not needed and fanin and fanout are small. Also, resetting speed is not an important problem. When a 50-bit binary adder is assumed, five times the switching time of the tunnel diode circuits is short enough for the resetting time of the circuit. Even if the resetting time is 50 times the switching time, it is not serious. Therefore, tunnel diode carry propagation circuits can be designed by considering the switching speed, tunnel diode tolerance, directivity and cost only. A diode coupling circuit seems to be the most advantageous directivity circuit for a tunnel diode carry propagation circuit since, in this case, it is not necessary to worry about the resetting problem, which is the demerit of the diode coupling circuit. Now, let a binary adder be considered where addend, augent, and carry from a lower stage are X, Y, and C*, respectively. Then, a carry C from this stage can be explained as follows: C = C*(X © Y) v XY = (C* v XY)(X v Y) = XY v C*X v C*Y This equation means that simple majority logic with three inputs, X, Y, and C* may be used as a carry generating circuit. But in order to get higher operating speed, some modification may be necessary. Especially, the propagation speed of the succeeding carry C*(X © Y) must be high. Otherwise, switching speed of the first generated carry XY may be lower than the switching speed of C*(X © Y) . -ko- Generally, the switching speed of the tunnel diode increases with increasing input signal and decreasing load current. In order to prohibit back- ward propagation, the amplitude of the first generated carry XY is preferred to be equal to or smaller than the amplitude of the succeeding carry C*(X © Y) . The circuits are assumed to constitute simple majority logic with inputs X, Y, and C*. (C.f., Figure 18(a).) The design conditions of the diode coupling circuit are considered next. The forward resistance must be small for high speed switching. But, if it is assumed that the ratio of the backward resistance to the forward resistance of the coupling diode is constant, a smaller forward resistance is associated with a smaller backward resistance. This means that the first generated carry XY has some amplitude limit, because a signal XY which is too large, would be propagated backwards. On the other hand, simplification of the resetting circuit results in omission of the bias circuit. Therefore, in order to get high switching speed, the input signal X and Y must supply current of nearly the same amplitude as the peak current of the tunnel diode, because the input signal C* is limited by the tunnel diode characteristic of the preceding stage and the forward resistance of the coupling diode. These two conditions contradict. Then, simple majority logic with three inputs, X, Y, and C* is not recommended. The circuits with three inputs (X © Y), XY, and C* are investigated next. (C.f., Figure 18(b).) The logical equation is as follows: C-XYv C*(X © Y) In this case, two kinds of carries, that is, XY and C*(X + Y) are dealt with independently. It is possible to select the amplitude of the signal (X + Y) close enough to the peak point of the tunnel diode characteristic, because the signal (X + Y) and the signal XY do not occur at the same time. The amplitude of the signal XY may be selected large enough to switch the tunnel diode, with the restriction that it may not exceed some value which causes backward transmission. The demerit of this circuit is that it needs a large signal XY. -in- Examination of the third type of the circuit -with the three inputs (X ^ y), XY and C* shows it to be the most advantageous. (Cf., Figure 18(c).) In this case, the amplitude of the signal (X v- Y) is selected close to the value of the peak point of the tunnel diode characteristic. The amplitude of the signal XY must be nearly the same or less than C*, because this signal is always accompanied by (X ^ Y) . The logical equation of the circuit is given by: C = (XY v C*)(X y Y) °— 0+ X o— W- Y C* ■Of X © Y W — i -0+ XY C* & • o M o — Of X U Y o IX- XY o— Of- c* (a) 0?) (c) Figure 18. Carry Generating Circuit If each current of the signals XY, C*, and (X ^ Y) is equated to i , i , and i a' b- respectively, the above equation is rewritten as follows: Min(i +i , L+i ) > I - L > Max(i, , i ) a c b c p d V c where I is the peak current of the tunnel diode and L is the bias current. The load resistance must be large in order to improve switching speed. Therefore, the use of a diode in the input circuit of the signal XY is preferred. Also, the use of some inductive element, like a high impedance strip line in the input circuit of the signal (X ^ Y) is recommended. The output signal must go to an adder circuit 42- which generates the sum (X © Y ffi C*), as well as to the next stage. This outp circuit should also have large resistance. The designed circuit is shown in Figure 19. This circuit was designed for a high speed transistor parallel computer originally, but its speed is expected to be high enough for a hybrid circuit computer, because no transistor exists between carry propagating stages. The delay time of this circuit is expected to be less than four tenth nanosecond per stage. Figure 19. High Speed Carry Propagation Circuit ■43- 6. Conclusion In order to get an output larger than one hundred millivolts in Ge tunnel diode hybrid circuits, further theoretical and experimental investigations of large signal operation characteristics of these circuits should be done. Preliminary experiments on basic circuits and a binary counter were done in order to confirm principles of these circuit operations. When an ordinary transistor is used, a delay time of two or three nanoseconds per stage, which is caused by carrier propagation between base and emitter of the transistor, is inevitable . A tunnel diode and transistor hybrid circuit seems to be more practical than an all tunnel diode circuit in a high speed computer, which is the successor to the transistor high speed computer, because the design of an all tunnel diode circuit, which is used in a large digital system, seems to encounter many difficulties. One merit of these hybrid circuits, which was not described up to this point, is the feasibility of making micro-modules of these circuits. M- APPENDIX 1 Simplified Analysis of the Switching Speed of a Tunnel Diode The equivalent circuit of a tunnel diode which is shown in Figure 20 is used in this analysis in order to simplify the analysis and comprehend some physical concepts of the switching time. In this circuit, it is assumed that the series impedance of the tunnel diode can be neglected. ^ I