LIBRARY OF THE UNIVERSITY OF ILLINOIS AT URBANA-CHAMPAIGN 6 /a 84 no.577-<582 cop. 2. Digitized by the Internet Archive in 2013 http://archive.org/details/usedescriptionof580cull ve. ?f ,tGAJ UIUCDCS-R-73-580 huxj t ^ USE AMD DESCRIPTION OF THE CALCOMP PROGRAM TO DRAW NETWORKS OF LOGIC GATES by JAY CULLINEY June, 1973 THE LIBRARY OF THF AUG 9 1973 I ININ/FRSri V Ul- ILLINOIS aturbanIcm^mpaigm DEPARTMENT OF COMPUTER SCIENCE UNIVERSITY OF ILLINOIS AT URBANA-CHAM. UIUCDCS-R-73-580 USE AND DESCRIPTION OF THE CALCOMP PROGRAM TO DRAW NETWORKS OF LOGIC GATES BY JAY CULLINEY June, 1973 Department of Computer Science University of Illinois at Urbana- Champaign Urbana, Illinois 6l801 Programming work was supported by the National Science Foundation under Grant No. NSF GJ-503. Ill TABLE OF CONTENTS Introduction 1 Program Size 1 General Description • 1 Limitations 2 Exceeding Limitations 3 Gate Symbols . . . k Preparation of Input Cards 7 Construction of the Network 10 Multiple Output Networks „ 15 Future Modifications 16 Computation Time l6 Appendices Appendix A IT Appendix B 30 Introduction : The program described in this reference manual was developed as a means to quickly obtain a reasonably precise drawing of a logical net- work, given a description of that network. Due to the difficulties involved, the program does not guarantee the most "aesthetically pleasing" arrangement of gates and intercon- nection lines (e.g., crossovers are not minimized) in each network diagram. However, it is still felt that this program produces network diagrams which are reasonable in appearance (e.g., the method employed for routing interconnections possesses at least some degree of sophis- tication) and acceptable for general purposes. Program Size : The program consists of three subroutines. When these are compiled with the Fortran H (opt 2) compiler, the resultant pro- gram occupies about 80K bytes of memory. The source deck consists of about 750 cards while the object deck (Fortran H, opt 2) contains about 320 cards. General Description : Given the following information for each gate in a network, this program positions the gates, labels the gates, and determines interconnection paths among gates such that the paths do not overlap with each other or with gate symbols. Provision is made for several lines of information which may accompany each network. (The program listing appears in Appendix B. ) 1) Gate Type--e.g., AND, OR, NOR. 2) Gate Level--this is defined for a gate i as follows: the number of gates in the longest path through the network from gate i to an output gate. 3) Gate Inputs — i.e., a list of gates and external variables which feed this gate. Limitations : 1) Gate types are restricted to: AND, OR,' NOR, Wired-AND, Wired- OR, NAND, Exclusive-OR, and Exclusive-NOR 2) Maximum number of gates — 20 3) Maximum number of levels — unrestricted k) Maximum number of external variables — 9 5) Maximum number of gates specified per level — 10 6) Maximum fan- in — 7 7) Maximum fan-out — unrestricted 8) Maximum amount of information allowed with each network — 7 lines of 50 characters each Restrictions (2), (3), {k) above are imposed only by the size of arrays in the program, and hence, are relatively easy to alter. Restriction (5) can probably be increased with only a slight programming change. We should note here that although up to 10 gates may be specified per level, only up to 5 gates are actually drawn in the same level (the other gates specified as being in that level are actually drawn one level of gates higher). This is due to the fact that the width of plotting allowed on usual Calcomp paper is restricted to 10 inches. After allotting space for 7 lines of information, there is only enough space remaining for 5 gates per level. By eliminating the information block, or by moving it elsewhere, we can achieve 6 or maybe even 7 gates per level. If higher limits are desired, one can go to wider Calcomp paper. But any change in the maximum number of gates drawn per level may require moderately extensive program changes. Restriction (6) is 3 due to the fact that there are only seven positions on each gate where we may attach inputs, Ity" making special provisions, we might increase this to 9 or 11 inputs, but such changes would probably be of moderate difficulty. Restriction (8) would be fairly easy to modify (increasing the number of characters per line to 80 is especially simple) if we do not mind using more Calcomp paper, but it is unwise to write more infor- mation than is necessary since the amount of Calcomp time consumed in plotting characters is quite significant. Exceeding Limitations : If any of the 8 limitations above are exceeded, the following actions are taken by the program, respectively: 1) Gate type OR will be assigned to any gate not specified as one of the 8 allowed types. 2) The program does not check this limit, so if it is exceeded, memory overwriting will occur. 3) Specifying more than 20 levels (or specifying a level greater than 21) will result in memory overwriting. k) Exceeding this limit will also cause overwriting of memory. 5) The exact consequences of exceeding this limit are not known. Probably either memory will be overwritten, a pen fault will occur, or perhaps both. See Fig. A- 3 in Appendix A for the results of specifying more than 5 (but less than 10 ) gates per level. 6) The inputs to a particular gate are written sequentially on a data card. If more than 7 inputs are listed, only the first 7 are accepted, the rest ignored, and a message is written by the Calcomp plotter: "fan- in overflow, inputs beyond 7 ignored". (See the example in Fig. A- 5 of Appendix A.) The plot con- tinues normally so that the user may still obtain a complete network diagram by adding the missing connections later by hand (but in some cases, the error message may obscure a part of the network). If 8 or more lines of information are specified, the 8th line will be omitted , replaced by the warning message: "error — too many heading cards". Any other lines are written in a space to the right of the first information block. If the number of lines in this second block of information again exceeds 7> the whole process is repeated. See the example in Fig. A-k of Appendix A. Gate Symbols The following symbols are used in the networks drawn by this pro- gram (the symbols used for AND, OR, NOR, NAND, and Exclusive-OR are the "Uniform Shapes" of the American Standard Graphic Symbols). Also, for each gate, input and output lines are shown. See Fig. A-l in Appendix A for examples of these different gate symbols as they are actually plotted. AND Gate: MA -4 T 7. i. sample gate number OR Gate: - OR NOR Gate: NAND Gate: Exclusive-OR Gate: Exclusive-NOR Gate: Wired- AND Gate: ►7e* WA k sample gate number (for 5 input case) for 6 and 7 input cases, we have, respectively: WA k T 3 / 4 1 WA Wired-OR Gate: WO 3 (for 5 input case) (for 6 and 7 input cases, we have, respectively: WO 3 and WO 3 For each gate type there is a maximum of 7 inputs. Input terminals of a gate are assigned to input lines in the following order (there exist some rare cases when this order is slightly altered by the program to avoid superimposing interconnections): 7 1 2 3 4 5 6 For OR, AND, NOR, NAND, Exclusive- OR, Exclusive- NOR Gates For Wired-AND, Wired-OR Gates So a gate with k inputs will have those input lines attached to input terminals 1 through k. For example, a gate with 2 inputs would be: 7 The (possible) nine external variables and their complements are designated: A, B, C, D, E, P, G, H, I, A, B, C, D, E, F, G, H, I, in the output dia- gram. When two gate interconnections intersect, a small square at the intersec- tion will indicate the existence of a connection between the two lines (e.g., ). The absence of such a square will indicate that the two lines are not connected. Preparation of Input Cards Of course, there are many possibilities for combinations of JCL cards. In Fig. 1 is a typical deck setup for the Calcomp program (for the current system used at D.C.L. (June, 1971)). There are two things of note here. First is the inclusion of the parameter "CALCOMP=YES" on the ID card. Second is the "// EXEC CALCOMP" card (which physically consists of two cards in this example, i.e., "REGI0N=232K" is a continuation of the "EXEC CALCOMP" card). Two parameters must be specified on this card: Maximum length (in inches) of paper to be used; Maximum plotter time (in the form h.mm.ss where h is number of hours, mm is number of minutes, and ss is number of seconds). The example in Fig. 1 specifies a maximum of 75 inches of paper or 5 minutes of plotter time. The block of cards labeled "Data Cards" actually consists of one or more consecutive network descriptions. Each network description consists of four parts: l) First come the heading cards. On these cards we may write any information that is desired to be output along with the network 8 7/go.sysin DD * REGI0N=232K DATA CARDS // EXEC CALCOMP,PARM='PL=75,TIME=5.00', 7/ EXEC LKEDFORr,PAEM='LET, LIST, MAP' MAIN PROGRAM AND SUBROUTINES //FORT.SYSIN DD * EXEC FORT, LEVEL=G, REGION. FORT=232K ID CARD (USE THE PARAMETER "CALCOMP=YES" ) J J Fie. 1 9 diagram. There may be a maximum of 7 such cards and only columns 1-50 of each card may be used. 2) Next is a card which signals the end of the heading cards. In columns 13-16 must be the characters "b. .b" (where b=blank). Anything may be in the other columns. Naturally, such a com- bination in columns 13-16 must not appear in any of the heading cards. 3) Next is a group of cards, one card for each gate in the network. These must be arranged such that the card for Gate 1 (the first output gate must be number l) comes first, the card for gate 2 comes second, etc. In columns 5-6 of each card, we may write two symbols which will be written beside the output line of the corresponding gate (this provision is to enable the user to label outputs of a multi-output network). Normally, for a single out- put network, this field is left blank. In columns 12-13 , write the gate number (right justified). In columns 17-20 write the type of this gate; the following forms are currently accepted (b=blank): "bNOR" for NOR; "bAND" for AND; "(AND" for AND; "WORb" for Wired-OR; "WAND" for Wired- AND; "ORbb", "bORb", "bbOR" for OR; "NAND" for NAND; "bXOR" for Exclusive- OR; "XNOR" for Exclusive-NOR (any other forms, or any mistakes in the above forms will result in the default assignment of the gate type OR). In columns 27-28 , write the level number (right justified) of this gate. Level numbers need not be assigned in accordance with the definition (of gate level) given earlier. Actually, the only requirement is that the level number of a given gate must be greater than the 10 level numbers of all gates fed by that gate. Starting after column 3^-j we have 11 fields of k characters each. In these fields (columns 35-38 , 39-^2 , k'j-hG , . . . ) are listed the in- puts to this gate, one input per field. In each field we write either the name of an external variable or the number of a gate which feeds this gate. In either case, the characters used must be right justified in each field. (External variables x.. , x , x -i> x l\. } X 5> x 6> Xr j } x 8' x q' x i' x 2' x 3' x h' x 5 } x 6' x 7' X Q' x 9' should be punched on the input cards as, XI, X2, X3, X^, X5, X6, X7, X8, X9, Yl, Y2, Y3, Yk, Y5, Y6, Y7, Y8, Y9, respectively. Alternatively, the characters "U" and "V" may be used in place of "X" and "Y" respectively. ) Currently, the program will only use the entries in the first seven fields and give a warning message if there are more than seven non-blank fields. The fields are read left to right; reading stops in the first blank field. k) Last is a single card with the characters "END" in the first three columns. Construction of the Network The program determines which and how many gates are in each level. (The output gate(s), at level 1, is to the right of the network. The other levels are then labeled, from right to left, 2, 3- ^, • • ••) An imaginary horizontal line, whose vertical height is fixed (from the bottom of the Calcomp paper), serves as a horizontal axis about which the network is centered. Within each level, the gates are positioned symmetrically about this line and ordered such that the smallest numbered gate (in that level) is assigned the "highest" position within that level and the highest n numbered gate (in that level) is assigned the "lowest" position with- in that level. So, at this point, every gate in the network has its vertical position specified. Horizontal coordinates cannot yet be deter- mined (note that every gate of a given level will have the same horizontal coordinate) since the complexity of the interconnection patterns between each pair of adjacent levels is as yet unknown. Next, external variables are assigned to the input terminals of the corresponding gates. Then we go through the gates in order, gate 2, gate 3, • • •> deter- mining the routing for the output connections of each one. For example, for gate i, first all levels containing gates fed by gate i are determined. The right-most level fed by gate i is then selected. We locate the specific gate or gates at this level which are fed by gate i. An input line is created for each of these gates. These horizontal input lines (if there are more than one) are joined by a vertical line. To this vertical line is attached another horizontal line which is fed through the next level of gates to the left. Then we repeat the same process (of creating inputs to gates fed by i) in the next level to the left, treating the line we just fed through to that level (almost) the same as any inputs to gates in this new level. Finally we will reach the level containing gate i and we can connect it to its newly constructed output tree. Example: Output connections from gate i to other gates in the network are constructed. Assume gate i feeds gates 1, 2, k, 5, 1, 8. First we find that gate i feeds levels 1, 2, 3, and h. Of these, level 1 is the right-most. And gate i feeds gate 1 in level 1. 12 level level level level level 5^321 8 □ Fie;. 2 So we draw an input line to gate 1 (as shown). This line is then fed through level 2 (as shown in Fig. k) . At level 2 we find two gates which are fed by i, gates 2 and 5. Input lines are created for these gates . 2 5 ~fl Fig. 3 -0 b l 7 Fig. h The three horizontal lines in Fig. h are then joined by a vertical line (Fig. 5) and another horizontal line is used to feed through level 3« At level 3 we find that only gate 7 is fed "by i. An input line to gate 7 is created and then joined with the line fed through from level 2. level 5 level k H B level 3 □ i 8 7 level 2 13 level 1 rH □ Fig. 5 □ 1 — > 2 r b 1 — > 7 Fig. 6 Again, a horizontal line is fed through the next level to the left. At level h, input lines are created for gates k and 8. E □ □ □ Fig. 7 llf At level h the 3 horizontal lines are joined by a vertical line. It is found that gate i is in the next level, and so a horizon- tal line is drawn from the output terminal of gate i to its interconnection tree. level level level level level 5 k 3 2 1 □ □ Fig. 8 End of example. Similar steps must be repeated for i = 2, 3, » • » } R (where R is the number of gates in the network). The routes taken by interconnections are "memorized" as they are determined so that no two interconnections may coincide. Actually the interconnections are not physically "drawn" at the time of determining the routing of the outputs from each gate since the actual x- coordinates of the intersection points cannot be calculated until all interconnection routing is complete and the number of vertical lines necessary between each pair of adjacent levels is known. Instead, we specify the x- coordinates of each intersection point relative to either the previous or succeeding level. This information is stored, and later when the x-coordinates of the levels can be calculated we can easily determine the x-coordinates of all intersections of interconnection lines relative to the origin (which is located at the center of the output level (level l)). This 15 information is needed in order to do the actual plotting. Notice that there was no trouble determining the y-coordinates of intersection points. The y-coordinates are known immediately for each intersection, as opposed to the x-coordinates which cannot be determined until all interconnection routing is complete. It might be mentioned that interconnection lines are kept l/8 inch apart (except when crossing at right angles). And horizontal lines must be at least l/8 inch away from the side of a gate, while vertical lines are no closer than 3/8 inch to the right of a gate or l/2 inch to the left of a gate. Multiple Output Networks In assigning gate levels for gates in a multiple output network, all output gates which do not feed other gates should be assigned to level 1. All gates in level 1 will be drawn with an arrow (indicative of an output of the network): Output gates which do feed other gates should not be assigned to level 1. In order to distinguish the different output functions in a multiple out- put network, a provision was made (as mentioned earlier) so that we can label the different output functions. For each gate, we can specify a label (of 1 or 2 symbols) which will be written beside the output of that gate (e.g., we can label the outputs of a multiple output network: Fl, F2, F3, etc.). Fig. A-2 in Appendix A is an example of a multiple (5) output net- work with outputs labeled Fl, . . . , F5. 16 Future Modifications — Further modifications of this program may occur in the future. In particular: multiple output gates (NOR-OR, NAND-Affi)), flipflops, feedback loops, automatic calculation of levels. Currently", the paths of the output lines for each gate i are deter- mined in the order i=l, 2, 3> • • • t 19> 20. It is possible that assigning interconnection paths for gates in reverse order (i.e., i=20, 19, 18, . . . , 3, 2, l) would reduce the number of crossovers in the network diagram. But this change is not quite as easy as it appears since some parts of the program depend on the assignment of interconnec- tion paths for gates in ascending order. Computation Time --For an average size network of 8 gates, we might expect, typically: a computation time of about l/3 or l/k second; a plot time of about 1 minute; a cost of about ^0- rvi co uo r~ co oo cm >- i CE LU H CO h- LU _J CO OO 12 CE O —• T. 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LJ 29 cc o a. i: cr x uj ex tn to x dl CO CD CO CD ± cr CO CD cr CO CD ± cr CO CD cr CO CD CO CD CO O cr CO CD cr CO o cc o CO CD 30 APPENDIX B Program Listing c**** L c L C m: AL iNTe jIMc luu) 2 MIL 3NrtlK t,MAK 5 ,l*K uATa OATa DATA JATA CAT* L»ATA PkcS li£H* Nilu , INT l)LcI c<20 NL V ( Aw< 1 rs I K MU f NCR Z^K ZY, ZNA XNC cNT l(< t NAM. * VLbH 20) ,RVLbH20),GLEV<20 ) N GAkL(2G), GIYPd( *G) , r 1 08 Y ( i. 1 ), NF tLbY ( 1 1 ), NM 1 NL V ckc(<.0,20),icXVAR(ld,<:0),LLKH(t>G,20),lNcXTL<20), 20), SPACtUO),MARKGT(20),GATfcP5<2U,2)»NTAKtN(^u>, ), LRrl<6u, 20) ,INPGT(20), IbTPOSUO) 20), SYM(i GO, 2), Ii>YM1»AN02 / ,cND,TE:>T,ZAND / ,ZNGR,ZX,Zi, lc / ZG,ZV,NANG / N0»XCR, ZXOR / R,ZXNG* / ,ZLAd tL(20) , •WANC'/ MO* , ' WA« , Nbk« , • tiNO U' ,'N' , • Y' ,' 0' LIMITATIONS 20 GATci, 20 LcVELS, 5 EXTERNAL VARIABLtS / / •/ / / / 7 PAN-IN, 5 GATES/LEVEL, MOVE PcN AWAY FkCM BORDER Call CCPlbA UlL PLCK.25,.25,-3) KcAO HEACING GaRGS PRtCtOING NETWCKK UcSCkIPTION 1 N=0 TOP = 9.57b 2 KcAc ICOCCARC 1000 FGRMAT(2GA«t) N=N + 1 IMN.GE. 8)GuTG3 IF(CARLI4).EQ.TEST)G0TG4 IMN.Gc.2)GCTC5 CALL SYM8UL(0.,9.5 75,.15,CARD{1J,0.0,50) GGTC2 5 TCP = TOP - .225 GALL SYMB0L(.0,TGP,.15,CARD<1) ,0.0,50) GCTC2 cRROR MESSAGE FOR TOO MANY (.GT. 8J HEADING GAROS 3 TOP = TOP - .225 CALL SYMBULi.O, TOP, .15, 'ERROR - TGO MANY HEADING CARDS • f .0 ,30 ) MOVE ORIGIN ANC CONTINUE URITING CALL PLCT(8.0,.0t-3) G0TL1 READ CIRCUIT DESCRIPTION NEXT * DO 38 1=1,800 38 IDRAw(I)=0 NUM=0 NDRAH=C OG 7 1=1,20 NWlRt( I )=0 MIUOLE(I)=0 7 NMINLVu 3il 35.: 35* 370 *uG 5Gu 600 700 800 900 1000 1100 1150 1200 1300 1350 1400 1500 1600 1700 1800 1850 1900 2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000 3100 3200 3300 3400 3500 3600 3700 3800 3900 4000 4100 4200 4225 4226 *250 4251 4254 4255 4256 4257 4260 4262 32 2C 9«t :000 as 84 14j IcXVAR( J,I)=Q UU fa J=it20 [NTtRCC 1 » J)=0 VAXLcV=l 00 000 5100 5200 5300 5350 5375 5400 5500 5550 5555 5560 5562 5564 5566 5568 5570 5600 5700 5800 5900 6000 6030 6040 6050 6060 6100 6200 6300 6400 6450 6500 6600 6700 6800 6900 6950 7000 7100 7200 7250 7251 7252 33 12 1NTERC(NFEDBY=NTAKENlGLEVU)Ul DO 65 1=1, NUM IF(NWIREU).EQ.0)G0TC85 IF (INPTTLU).LE. 5 )GGTC85 KLAG=0 N0RAW=NCRAW+1 IDRA*(NCRAw)=GLEV( I) DRAW(NDRAW,1)=.375 DRA*(NCRAw,2)=-.2 5+KLAG*.50 NDRAW=N0RAW*1 7300 7400 7500 7510 7514 7516 7522 7526 7530 7534 7538 7542 7550 7554 7556 7556 7562 7566 7570 7571 7572 7574 7576 7578 7582 7600 7700 7800 8005 8010 8011 8012 8013 8014 8015 8016 8017 8018 8019 8020 8021 8022 8025 8026 8030 8031 8032 8034 8036 6038 8040 8042 6050 6052 8054 8056 8058 8060 8062 8064 8066 IU«Aw(NCRAW) = GLEV( I ) 8068 URAMNCkAw,U=.375 8070 L,KAW(NCkAW,2)=-.i76 + KLAG*.7 5 8072 NJRAw = NCRAk< + l 8074 IGRAw(NCRA*)=-l 6076 IF( INPTTLU).LE.to)GGTG85 807b iFlKLAG.EC.l )GuTC85 8080 KLAb=l 8082 GuTCae 80o4 83 CONTINUE &066 C CHECK EACH oATc FOK INPUT LINE CGNFLluTS AT POSITION 3 8100 CO cd J=l t NUM 8102 IF( INtXTLUI.GE.3)GGTG68 8104 K.CGUNT=INEXTLl J) 8106 UG 69 K=1,NUM 8108 irl INTERC(K,J).EQ.1)KCCUNT = KCCUNT«-1 8110 IF «-1.0k. IGTPGS < KK) .Nt. IGTPOSI JDGCT080 8122 MI0CLEIJ)=1 8123 C ABOVE STATtMENT MARKS GATE J AS HAVING AN INPUT CONFLICT AT POS. 3 8124 80 CONTINUE 8125 68 CONTINUE 8126 C 8250 C CALCULATt X-CGGRGINATES OF GATES 3251 C 8252 00 41 II=ltNUM 8260 IF( INEXTLI ID-EQ.INPTTH II) IGUTGhI 8262 INPTTL(II) = INPTTL(II)+MIDDLE< II ) 8263 IA=INPTTL(II) 8264 IF< IA.GE.7)IA=6 8266 IA=iA-INEXTL( II) 8268 I8=IGTPGS( IIJ + 3-INEXTLUIJ 8270 00 42 IJ=1,IA 8272 42 LRH(IB-IJ,GL£V(II ) >=1 8274 IF< InPTTLI II).NE.7)GGT04l 8276 LRH(IGTPCS( II )+3 v bLEVUIi)*l 8278 41 CONTINUE 82 80 00 28 I=2tNUM 8300 UG 29 1I=1,MAXLEV 8400 29 MARKLV(II)=Q 8500 IFLAG=0 8600 LtVFT=-l 8650 00 93 J=1,NUM 8700 93 IF( INTERC(I,J).EQ.1)MARKLV(GLEV( J )) =MARKLV ( GLE V< J))+l 8800 UG 32 J=1,MAXLEV 8900 IF(MARKLV(J).NE.O)GOT034 9000 32 CONTINUE 9100 GGT028 9 1 50 C J = RIGHTMOST LEVEL FEU BY GATE I 9 200 34 IF(J+1.EU.GLEV(I))IFLAG=1 9300 1F(MARKLVIJ).EQ.1.AND.IFLAG.EQ.0)G0T035 9400 C RcSERVE A VERTICAL LINE AT THIS LEVEL 9500 IF( IFLAG.EQ.DGGT046 9550 LINEV=VLBL( J)+l 96 °° VLBLI J)=VLBL( J)*l 9700 G0T047 9 ?50 35 40 LlNbV=RVLBL( J)+l 9752 RVLBL( J)=RVLBL(J)+1 9754 FIND MAX AND MIN Y-COORDS 9800 47 MAX=0 9900 MIN=60 10000 ICGUNT=0 10050 DO 36 JJ=l f NUM 10100 IFUNTERCi I,JJ).EQ.0)G0TQ36 10200 IF(GLEV(JJ) .NE.JJGQT036 10300 JJLEV=IGTP0S(JJ)+3-INPUT< JJ) 10350 IF*.125 DRAW, i)=. 375 DRAW,2)=Y NCRAWd NDRAW)=J+IFLAG DRAW,1 )=X DRAW,2)=Y NDPAW+1 NDRAW)=-1 EV.E0.MAX)G0T039 EV-EQ.MIN)G0T039 DRAW INTERCGNNcCTION POINTS IPTSYM ISYM( I SYMdP SYMdP CONTIN IF(LEV IF(LEV IF(LEV IPTSYM ISYM( I Y=(LEV SYM( IP SYMdP GOTOhO IF(LEV MAX=LE MIN=MA X=.75+ G0T040 DO 96 =IPTSYM+1 PTSYM)=JdFLAG TSYM, 1)=X TSYM,2)=Y UE FT.LT.O)GOT040 FT.EU.MAXJGOT040 FT.EQ.MiN)GGT040 =IPTSYM+i PTSYM)=JdFLAG FT-30)*.125 TSYM,1)=X TSYM,2)=Y FT.LT.0)G0T095 VFT X VLBLI J)*. 125*. 125 JJ=1 ,NUM 12300 12900 13000 13100 13200 13300 13400 13500 13600 13612 13614 13616 1361b 13620 13622 13624 13626 13628 13630 13632 13633 13634 13700 13750 13300 13900 14000 14100 14300 14400 14500 14600 14800 14900 15000 15100 15200 15300 15400 15500 15600 15700 15800 15900 16000 16100 16200 16300 16400 16500 16600 16700 16800 16900 16929 16930 16931 16932 16950 16953 16954 IF(GLEV( JJ) .NE.JJG0T096 IF< INTERU I ,JJ).EQ.0)GOTO96 MAX=IGTPOS( JJ)+3-INPUT(JJ) IF / DATA BB / ■ • / DATA ZD,ZOR,ZA,ZX,ZOE,ZZ/ • C NEGATE=0 ADJ=0. ICHAR=1 JO 5 1=1,20 IF( I. EQ. NUMBER I DIGIT* ANUM ( I) CONTINUE IF(NUMBER.GE.IO) ADJ=.065 IF(NUMBER.GE.IO) ICHAR=2 SET OFFSET SO PLOTS WILL CENTER ON GATE CENTER (P,Q) X0FF=-P YOFF=-Q CALL OFFSET(XOFF,1.0,Y0FF,1.0) WRITE SYMBOLS IDENTIFYING GATE TYPE AND NUMBER 10 IF(TY TYPE = NEGAT G0T04 IF(TY NEGAT TYPE = IF(TY TYPE = NEGAT IF(TY XSYM= YSYM = CALL GQT03 IFITY XSYM = YSYM= CALL G0T03 XSYM= YSYM= CALL XSYM= YSYM= CALL IF(ZL XSYM = YSYM= CALL CONTI PE.NE.ZZ)G0T09 ZX E = l PE.NE.ZD1G0T02 E = l ZA PE.NE.ZNJG0T06 ZO E=l PE.NE.Z0)G0T04 P-.275 Q-.125 SYMBOL(XSYM,YSYM,.25,ZOR,0.0,2) PE.NE.ZXJG0T01 P-.275 Q-.125 SYMBOL(XSYM,YSYM,.25,ZOE,0.0,2) P-.125 Q-.125 SYMB0L(XSYM,YSYM,.25, ZA ,0.0, I) P+.19-ADJ Q-.315 SYMBOL (XSYM,YSYM, . 12 5, DIGIT, 0.0, I CHAR) ABEL.EQ.BB)G0T010 P+.470 Q+.185 SYMBOL(XSYM,YSYM,.125,ZLABEL,0.0,2) NUE C C c DRAW NOR GATE CALL PL0T(.375,-.375,13) CALL PLOT( .375, .0,12) IF(NEGATE.EQ.0)G0T07 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000 3100 3200 3300 3400 3500 3600 3700 3800 3900 4000 4100 4200 4300 4400 4500 4600 4700 4800 4900 5000 5100 5200 5300 5400 5500 5600 5700 5800 5900 6000 6100 CALL PL0T(.405,.055,12) CALL PLOT(.470,.055,12) CALL PLOT(. 500, .0,12) CALL PLOT* .470, -.055, 12) CALL PLGT(.405,-.055,12) G0TO8 CALL PLOT(. 540, .0,12) CALL PLOTt. 375, .0,12) CALL PLOT(.375,.375,12) CALL PLCT(-.375,.375,12) CALL PL0T<-.375,-.375,12) CALL PL0T(.375,-.375, 12) RETURN END 1+3 6200 6300 6400 6500 6600 6700 6800 6900 7000 7100 7200 7300 7400 7500 SUBROUTINE WlREDC P , Q, NUMBER , TYPE , ZLABEL ) DIMENSION ANUM(20) OATA ANUM /• 1 • , • 2* , • 3' , • 4« , ■ 5 • , • 6 • , • 7 • , »8 ■ t »9 • , • 10 • t • 1 1« f » 12 • , 1 '13S •14 , , , 15«,«16', , 17»,« 18 f ,»19« ,'20» / DATA EB / ■ • / ADJ=0. ICHAR=1 DO 1 1=1,20 IF( I.E0.NUM8ER)DIGIT=ANUM(I ) 1 CONTINUE IFINUMBER.LT. 10JG0T02 A0J=.055 ICHAR=2 SET OFFSET SO PLOTS WILL CENTER ON POINT (P,Q) 2 X0FF=-P YOFF=-Q CALL OFFSET(X0FF,1.0,YOFF,1.0) WRITE GATE TYPE AND NUMBER XSYM=P-.266 YSYM=Q-0.0 CALL SYMB0L{XSYM,YSYM,.188,TYPE,0.0 f 2) XSYM=-.164-ADJ+P YSYM=Q-.188 CALL SYMBOL